1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2016,2017 IBM Corporation. 4 */ 5 6 #define pr_fmt(fmt) "xive: " fmt 7 8 #include <linux/types.h> 9 #include <linux/irq.h> 10 #include <linux/smp.h> 11 #include <linux/interrupt.h> 12 #include <linux/init.h> 13 #include <linux/of.h> 14 #include <linux/slab.h> 15 #include <linux/spinlock.h> 16 #include <linux/cpumask.h> 17 #include <linux/mm.h> 18 #include <linux/delay.h> 19 #include <linux/libfdt.h> 20 21 #include <asm/prom.h> 22 #include <asm/io.h> 23 #include <asm/smp.h> 24 #include <asm/irq.h> 25 #include <asm/errno.h> 26 #include <asm/xive.h> 27 #include <asm/xive-regs.h> 28 #include <asm/hvcall.h> 29 30 #include "xive-internal.h" 31 32 static u32 xive_queue_shift; 33 34 struct xive_irq_bitmap { 35 unsigned long *bitmap; 36 unsigned int base; 37 unsigned int count; 38 spinlock_t lock; 39 struct list_head list; 40 }; 41 42 static LIST_HEAD(xive_irq_bitmaps); 43 44 static int xive_irq_bitmap_add(int base, int count) 45 { 46 struct xive_irq_bitmap *xibm; 47 48 xibm = kzalloc(sizeof(*xibm), GFP_KERNEL); 49 if (!xibm) 50 return -ENOMEM; 51 52 spin_lock_init(&xibm->lock); 53 xibm->base = base; 54 xibm->count = count; 55 xibm->bitmap = kzalloc(xibm->count, GFP_KERNEL); 56 if (!xibm->bitmap) { 57 kfree(xibm); 58 return -ENOMEM; 59 } 60 list_add(&xibm->list, &xive_irq_bitmaps); 61 62 pr_info("Using IRQ range [%x-%x]", xibm->base, 63 xibm->base + xibm->count - 1); 64 return 0; 65 } 66 67 static int __xive_irq_bitmap_alloc(struct xive_irq_bitmap *xibm) 68 { 69 int irq; 70 71 irq = find_first_zero_bit(xibm->bitmap, xibm->count); 72 if (irq != xibm->count) { 73 set_bit(irq, xibm->bitmap); 74 irq += xibm->base; 75 } else { 76 irq = -ENOMEM; 77 } 78 79 return irq; 80 } 81 82 static int xive_irq_bitmap_alloc(void) 83 { 84 struct xive_irq_bitmap *xibm; 85 unsigned long flags; 86 int irq = -ENOENT; 87 88 list_for_each_entry(xibm, &xive_irq_bitmaps, list) { 89 spin_lock_irqsave(&xibm->lock, flags); 90 irq = __xive_irq_bitmap_alloc(xibm); 91 spin_unlock_irqrestore(&xibm->lock, flags); 92 if (irq >= 0) 93 break; 94 } 95 return irq; 96 } 97 98 static void xive_irq_bitmap_free(int irq) 99 { 100 unsigned long flags; 101 struct xive_irq_bitmap *xibm; 102 103 list_for_each_entry(xibm, &xive_irq_bitmaps, list) { 104 if ((irq >= xibm->base) && (irq < xibm->base + xibm->count)) { 105 spin_lock_irqsave(&xibm->lock, flags); 106 clear_bit(irq - xibm->base, xibm->bitmap); 107 spin_unlock_irqrestore(&xibm->lock, flags); 108 break; 109 } 110 } 111 } 112 113 114 /* Based on the similar routines in RTAS */ 115 static unsigned int plpar_busy_delay_time(long rc) 116 { 117 unsigned int ms = 0; 118 119 if (H_IS_LONG_BUSY(rc)) { 120 ms = get_longbusy_msecs(rc); 121 } else if (rc == H_BUSY) { 122 ms = 10; /* seems appropriate for XIVE hcalls */ 123 } 124 125 return ms; 126 } 127 128 static unsigned int plpar_busy_delay(int rc) 129 { 130 unsigned int ms; 131 132 ms = plpar_busy_delay_time(rc); 133 if (ms) 134 mdelay(ms); 135 136 return ms; 137 } 138 139 /* 140 * Note: this call has a partition wide scope and can take a while to 141 * complete. If it returns H_LONG_BUSY_* it should be retried 142 * periodically. 143 */ 144 static long plpar_int_reset(unsigned long flags) 145 { 146 long rc; 147 148 do { 149 rc = plpar_hcall_norets(H_INT_RESET, flags); 150 } while (plpar_busy_delay(rc)); 151 152 if (rc) 153 pr_err("H_INT_RESET failed %ld\n", rc); 154 155 return rc; 156 } 157 158 static long plpar_int_get_source_info(unsigned long flags, 159 unsigned long lisn, 160 unsigned long *src_flags, 161 unsigned long *eoi_page, 162 unsigned long *trig_page, 163 unsigned long *esb_shift) 164 { 165 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 166 long rc; 167 168 do { 169 rc = plpar_hcall(H_INT_GET_SOURCE_INFO, retbuf, flags, lisn); 170 } while (plpar_busy_delay(rc)); 171 172 if (rc) { 173 pr_err("H_INT_GET_SOURCE_INFO lisn=%ld failed %ld\n", lisn, rc); 174 return rc; 175 } 176 177 *src_flags = retbuf[0]; 178 *eoi_page = retbuf[1]; 179 *trig_page = retbuf[2]; 180 *esb_shift = retbuf[3]; 181 182 pr_devel("H_INT_GET_SOURCE_INFO flags=%lx eoi=%lx trig=%lx shift=%lx\n", 183 retbuf[0], retbuf[1], retbuf[2], retbuf[3]); 184 185 return 0; 186 } 187 188 #define XIVE_SRC_SET_EISN (1ull << (63 - 62)) 189 #define XIVE_SRC_MASK (1ull << (63 - 63)) /* unused */ 190 191 static long plpar_int_set_source_config(unsigned long flags, 192 unsigned long lisn, 193 unsigned long target, 194 unsigned long prio, 195 unsigned long sw_irq) 196 { 197 long rc; 198 199 200 pr_devel("H_INT_SET_SOURCE_CONFIG flags=%lx lisn=%lx target=%lx prio=%lx sw_irq=%lx\n", 201 flags, lisn, target, prio, sw_irq); 202 203 204 do { 205 rc = plpar_hcall_norets(H_INT_SET_SOURCE_CONFIG, flags, lisn, 206 target, prio, sw_irq); 207 } while (plpar_busy_delay(rc)); 208 209 if (rc) { 210 pr_err("H_INT_SET_SOURCE_CONFIG lisn=%ld target=%lx prio=%lx failed %ld\n", 211 lisn, target, prio, rc); 212 return rc; 213 } 214 215 return 0; 216 } 217 218 static long plpar_int_get_source_config(unsigned long flags, 219 unsigned long lisn, 220 unsigned long *target, 221 unsigned long *prio, 222 unsigned long *sw_irq) 223 { 224 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 225 long rc; 226 227 pr_devel("H_INT_GET_SOURCE_CONFIG flags=%lx lisn=%lx\n", flags, lisn); 228 229 do { 230 rc = plpar_hcall(H_INT_GET_SOURCE_CONFIG, retbuf, flags, lisn, 231 target, prio, sw_irq); 232 } while (plpar_busy_delay(rc)); 233 234 if (rc) { 235 pr_err("H_INT_GET_SOURCE_CONFIG lisn=%ld failed %ld\n", 236 lisn, rc); 237 return rc; 238 } 239 240 *target = retbuf[0]; 241 *prio = retbuf[1]; 242 *sw_irq = retbuf[2]; 243 244 pr_devel("H_INT_GET_SOURCE_CONFIG target=%lx prio=%lx sw_irq=%lx\n", 245 retbuf[0], retbuf[1], retbuf[2]); 246 247 return 0; 248 } 249 250 static long plpar_int_get_queue_info(unsigned long flags, 251 unsigned long target, 252 unsigned long priority, 253 unsigned long *esn_page, 254 unsigned long *esn_size) 255 { 256 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 257 long rc; 258 259 do { 260 rc = plpar_hcall(H_INT_GET_QUEUE_INFO, retbuf, flags, target, 261 priority); 262 } while (plpar_busy_delay(rc)); 263 264 if (rc) { 265 pr_err("H_INT_GET_QUEUE_INFO cpu=%ld prio=%ld failed %ld\n", 266 target, priority, rc); 267 return rc; 268 } 269 270 *esn_page = retbuf[0]; 271 *esn_size = retbuf[1]; 272 273 pr_devel("H_INT_GET_QUEUE_INFO page=%lx size=%lx\n", 274 retbuf[0], retbuf[1]); 275 276 return 0; 277 } 278 279 #define XIVE_EQ_ALWAYS_NOTIFY (1ull << (63 - 63)) 280 281 static long plpar_int_set_queue_config(unsigned long flags, 282 unsigned long target, 283 unsigned long priority, 284 unsigned long qpage, 285 unsigned long qsize) 286 { 287 long rc; 288 289 pr_devel("H_INT_SET_QUEUE_CONFIG flags=%lx target=%lx priority=%lx qpage=%lx qsize=%lx\n", 290 flags, target, priority, qpage, qsize); 291 292 do { 293 rc = plpar_hcall_norets(H_INT_SET_QUEUE_CONFIG, flags, target, 294 priority, qpage, qsize); 295 } while (plpar_busy_delay(rc)); 296 297 if (rc) { 298 pr_err("H_INT_SET_QUEUE_CONFIG cpu=%ld prio=%ld qpage=%lx returned %ld\n", 299 target, priority, qpage, rc); 300 return rc; 301 } 302 303 return 0; 304 } 305 306 static long plpar_int_sync(unsigned long flags, unsigned long lisn) 307 { 308 long rc; 309 310 do { 311 rc = plpar_hcall_norets(H_INT_SYNC, flags, lisn); 312 } while (plpar_busy_delay(rc)); 313 314 if (rc) { 315 pr_err("H_INT_SYNC lisn=%ld returned %ld\n", lisn, rc); 316 return rc; 317 } 318 319 return 0; 320 } 321 322 #define XIVE_ESB_FLAG_STORE (1ull << (63 - 63)) 323 324 static long plpar_int_esb(unsigned long flags, 325 unsigned long lisn, 326 unsigned long offset, 327 unsigned long in_data, 328 unsigned long *out_data) 329 { 330 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 331 long rc; 332 333 pr_devel("H_INT_ESB flags=%lx lisn=%lx offset=%lx in=%lx\n", 334 flags, lisn, offset, in_data); 335 336 do { 337 rc = plpar_hcall(H_INT_ESB, retbuf, flags, lisn, offset, 338 in_data); 339 } while (plpar_busy_delay(rc)); 340 341 if (rc) { 342 pr_err("H_INT_ESB lisn=%ld offset=%ld returned %ld\n", 343 lisn, offset, rc); 344 return rc; 345 } 346 347 *out_data = retbuf[0]; 348 349 return 0; 350 } 351 352 static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64 data, bool write) 353 { 354 unsigned long read_data; 355 long rc; 356 357 rc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0, 358 lisn, offset, data, &read_data); 359 if (rc) 360 return -1; 361 362 return write ? 0 : read_data; 363 } 364 365 #define XIVE_SRC_H_INT_ESB (1ull << (63 - 60)) 366 #define XIVE_SRC_LSI (1ull << (63 - 61)) 367 #define XIVE_SRC_TRIGGER (1ull << (63 - 62)) 368 #define XIVE_SRC_STORE_EOI (1ull << (63 - 63)) 369 370 static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data) 371 { 372 long rc; 373 unsigned long flags; 374 unsigned long eoi_page; 375 unsigned long trig_page; 376 unsigned long esb_shift; 377 378 memset(data, 0, sizeof(*data)); 379 380 rc = plpar_int_get_source_info(0, hw_irq, &flags, &eoi_page, &trig_page, 381 &esb_shift); 382 if (rc) 383 return -EINVAL; 384 385 if (flags & XIVE_SRC_H_INT_ESB) 386 data->flags |= XIVE_IRQ_FLAG_H_INT_ESB; 387 if (flags & XIVE_SRC_STORE_EOI) 388 data->flags |= XIVE_IRQ_FLAG_STORE_EOI; 389 if (flags & XIVE_SRC_LSI) 390 data->flags |= XIVE_IRQ_FLAG_LSI; 391 data->eoi_page = eoi_page; 392 data->esb_shift = esb_shift; 393 data->trig_page = trig_page; 394 395 /* 396 * No chip-id for the sPAPR backend. This has an impact how we 397 * pick a target. See xive_pick_irq_target(). 398 */ 399 data->src_chip = XIVE_INVALID_CHIP_ID; 400 401 data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift); 402 if (!data->eoi_mmio) { 403 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq); 404 return -ENOMEM; 405 } 406 407 data->hw_irq = hw_irq; 408 409 /* Full function page supports trigger */ 410 if (flags & XIVE_SRC_TRIGGER) { 411 data->trig_mmio = data->eoi_mmio; 412 return 0; 413 } 414 415 data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift); 416 if (!data->trig_mmio) { 417 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq); 418 return -ENOMEM; 419 } 420 return 0; 421 } 422 423 static int xive_spapr_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) 424 { 425 long rc; 426 427 rc = plpar_int_set_source_config(XIVE_SRC_SET_EISN, hw_irq, target, 428 prio, sw_irq); 429 430 return rc == 0 ? 0 : -ENXIO; 431 } 432 433 static int xive_spapr_get_irq_config(u32 hw_irq, u32 *target, u8 *prio, 434 u32 *sw_irq) 435 { 436 long rc; 437 unsigned long h_target; 438 unsigned long h_prio; 439 unsigned long h_sw_irq; 440 441 rc = plpar_int_get_source_config(0, hw_irq, &h_target, &h_prio, 442 &h_sw_irq); 443 444 *target = h_target; 445 *prio = h_prio; 446 *sw_irq = h_sw_irq; 447 448 return rc == 0 ? 0 : -ENXIO; 449 } 450 451 /* This can be called multiple time to change a queue configuration */ 452 static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio, 453 __be32 *qpage, u32 order) 454 { 455 s64 rc = 0; 456 unsigned long esn_page; 457 unsigned long esn_size; 458 u64 flags, qpage_phys; 459 460 /* If there's an actual queue page, clean it */ 461 if (order) { 462 if (WARN_ON(!qpage)) 463 return -EINVAL; 464 qpage_phys = __pa(qpage); 465 } else { 466 qpage_phys = 0; 467 } 468 469 /* Initialize the rest of the fields */ 470 q->msk = order ? ((1u << (order - 2)) - 1) : 0; 471 q->idx = 0; 472 q->toggle = 0; 473 474 rc = plpar_int_get_queue_info(0, target, prio, &esn_page, &esn_size); 475 if (rc) { 476 pr_err("Error %lld getting queue info CPU %d prio %d\n", rc, 477 target, prio); 478 rc = -EIO; 479 goto fail; 480 } 481 482 /* TODO: add support for the notification page */ 483 q->eoi_phys = esn_page; 484 485 /* Default is to always notify */ 486 flags = XIVE_EQ_ALWAYS_NOTIFY; 487 488 /* Configure and enable the queue in HW */ 489 rc = plpar_int_set_queue_config(flags, target, prio, qpage_phys, order); 490 if (rc) { 491 pr_err("Error %lld setting queue for CPU %d prio %d\n", rc, 492 target, prio); 493 rc = -EIO; 494 } else { 495 q->qpage = qpage; 496 } 497 fail: 498 return rc; 499 } 500 501 static int xive_spapr_setup_queue(unsigned int cpu, struct xive_cpu *xc, 502 u8 prio) 503 { 504 struct xive_q *q = &xc->queue[prio]; 505 __be32 *qpage; 506 507 qpage = xive_queue_page_alloc(cpu, xive_queue_shift); 508 if (IS_ERR(qpage)) 509 return PTR_ERR(qpage); 510 511 return xive_spapr_configure_queue(get_hard_smp_processor_id(cpu), 512 q, prio, qpage, xive_queue_shift); 513 } 514 515 static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, 516 u8 prio) 517 { 518 struct xive_q *q = &xc->queue[prio]; 519 unsigned int alloc_order; 520 long rc; 521 int hw_cpu = get_hard_smp_processor_id(cpu); 522 523 rc = plpar_int_set_queue_config(0, hw_cpu, prio, 0, 0); 524 if (rc) 525 pr_err("Error %ld setting queue for CPU %d prio %d\n", rc, 526 hw_cpu, prio); 527 528 alloc_order = xive_alloc_order(xive_queue_shift); 529 free_pages((unsigned long)q->qpage, alloc_order); 530 q->qpage = NULL; 531 } 532 533 static bool xive_spapr_match(struct device_node *node) 534 { 535 /* Ignore cascaded controllers for the moment */ 536 return 1; 537 } 538 539 #ifdef CONFIG_SMP 540 static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc) 541 { 542 int irq = xive_irq_bitmap_alloc(); 543 544 if (irq < 0) { 545 pr_err("Failed to allocate IPI on CPU %d\n", cpu); 546 return -ENXIO; 547 } 548 549 xc->hw_ipi = irq; 550 return 0; 551 } 552 553 static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc) 554 { 555 if (!xc->hw_ipi) 556 return; 557 558 xive_irq_bitmap_free(xc->hw_ipi); 559 xc->hw_ipi = 0; 560 } 561 #endif /* CONFIG_SMP */ 562 563 static void xive_spapr_shutdown(void) 564 { 565 plpar_int_reset(0); 566 } 567 568 /* 569 * Perform an "ack" cycle on the current thread. Grab the pending 570 * active priorities and update the CPPR to the most favored one. 571 */ 572 static void xive_spapr_update_pending(struct xive_cpu *xc) 573 { 574 u8 nsr, cppr; 575 u16 ack; 576 577 /* 578 * Perform the "Acknowledge O/S to Register" cycle. 579 * 580 * Let's speedup the access to the TIMA using the raw I/O 581 * accessor as we don't need the synchronisation routine of 582 * the higher level ones 583 */ 584 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_OS_REG)); 585 586 /* Synchronize subsequent queue accesses */ 587 mb(); 588 589 /* 590 * Grab the CPPR and the "NSR" field which indicates the source 591 * of the interrupt (if any) 592 */ 593 cppr = ack & 0xff; 594 nsr = ack >> 8; 595 596 if (nsr & TM_QW1_NSR_EO) { 597 if (cppr == 0xff) 598 return; 599 /* Mark the priority pending */ 600 xc->pending_prio |= 1 << cppr; 601 602 /* 603 * A new interrupt should never have a CPPR less favored 604 * than our current one. 605 */ 606 if (cppr >= xc->cppr) 607 pr_err("CPU %d odd ack CPPR, got %d at %d\n", 608 smp_processor_id(), cppr, xc->cppr); 609 610 /* Update our idea of what the CPPR is */ 611 xc->cppr = cppr; 612 } 613 } 614 615 static void xive_spapr_eoi(u32 hw_irq) 616 { 617 /* Not used */; 618 } 619 620 static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc) 621 { 622 /* Only some debug on the TIMA settings */ 623 pr_debug("(HW value: %08x %08x %08x)\n", 624 in_be32(xive_tima + TM_QW1_OS + TM_WORD0), 625 in_be32(xive_tima + TM_QW1_OS + TM_WORD1), 626 in_be32(xive_tima + TM_QW1_OS + TM_WORD2)); 627 } 628 629 static void xive_spapr_teardown_cpu(unsigned int cpu, struct xive_cpu *xc) 630 { 631 /* Nothing to do */; 632 } 633 634 static void xive_spapr_sync_source(u32 hw_irq) 635 { 636 /* Specs are unclear on what this is doing */ 637 plpar_int_sync(0, hw_irq); 638 } 639 640 static const struct xive_ops xive_spapr_ops = { 641 .populate_irq_data = xive_spapr_populate_irq_data, 642 .configure_irq = xive_spapr_configure_irq, 643 .get_irq_config = xive_spapr_get_irq_config, 644 .setup_queue = xive_spapr_setup_queue, 645 .cleanup_queue = xive_spapr_cleanup_queue, 646 .match = xive_spapr_match, 647 .shutdown = xive_spapr_shutdown, 648 .update_pending = xive_spapr_update_pending, 649 .eoi = xive_spapr_eoi, 650 .setup_cpu = xive_spapr_setup_cpu, 651 .teardown_cpu = xive_spapr_teardown_cpu, 652 .sync_source = xive_spapr_sync_source, 653 .esb_rw = xive_spapr_esb_rw, 654 #ifdef CONFIG_SMP 655 .get_ipi = xive_spapr_get_ipi, 656 .put_ipi = xive_spapr_put_ipi, 657 #endif /* CONFIG_SMP */ 658 .name = "spapr", 659 }; 660 661 /* 662 * get max priority from "/ibm,plat-res-int-priorities" 663 */ 664 static bool xive_get_max_prio(u8 *max_prio) 665 { 666 struct device_node *rootdn; 667 const __be32 *reg; 668 u32 len; 669 int prio, found; 670 671 rootdn = of_find_node_by_path("/"); 672 if (!rootdn) { 673 pr_err("not root node found !\n"); 674 return false; 675 } 676 677 reg = of_get_property(rootdn, "ibm,plat-res-int-priorities", &len); 678 if (!reg) { 679 pr_err("Failed to read 'ibm,plat-res-int-priorities' property\n"); 680 return false; 681 } 682 683 if (len % (2 * sizeof(u32)) != 0) { 684 pr_err("invalid 'ibm,plat-res-int-priorities' property\n"); 685 return false; 686 } 687 688 /* HW supports priorities in the range [0-7] and 0xFF is a 689 * wildcard priority used to mask. We scan the ranges reserved 690 * by the hypervisor to find the lowest priority we can use. 691 */ 692 found = 0xFF; 693 for (prio = 0; prio < 8; prio++) { 694 int reserved = 0; 695 int i; 696 697 for (i = 0; i < len / (2 * sizeof(u32)); i++) { 698 int base = be32_to_cpu(reg[2 * i]); 699 int range = be32_to_cpu(reg[2 * i + 1]); 700 701 if (prio >= base && prio < base + range) 702 reserved++; 703 } 704 705 if (!reserved) 706 found = prio; 707 } 708 709 if (found == 0xFF) { 710 pr_err("no valid priority found in 'ibm,plat-res-int-priorities'\n"); 711 return false; 712 } 713 714 *max_prio = found; 715 return true; 716 } 717 718 static const u8 *get_vec5_feature(unsigned int index) 719 { 720 unsigned long root, chosen; 721 int size; 722 const u8 *vec5; 723 724 root = of_get_flat_dt_root(); 725 chosen = of_get_flat_dt_subnode_by_name(root, "chosen"); 726 if (chosen == -FDT_ERR_NOTFOUND) 727 return NULL; 728 729 vec5 = of_get_flat_dt_prop(chosen, "ibm,architecture-vec-5", &size); 730 if (!vec5) 731 return NULL; 732 733 if (size <= index) 734 return NULL; 735 736 return vec5 + index; 737 } 738 739 static bool xive_spapr_disabled(void) 740 { 741 const u8 *vec5_xive; 742 743 vec5_xive = get_vec5_feature(OV5_INDX(OV5_XIVE_SUPPORT)); 744 if (vec5_xive) { 745 u8 val; 746 747 val = *vec5_xive & OV5_FEAT(OV5_XIVE_SUPPORT); 748 switch (val) { 749 case OV5_FEAT(OV5_XIVE_EITHER): 750 case OV5_FEAT(OV5_XIVE_LEGACY): 751 break; 752 case OV5_FEAT(OV5_XIVE_EXPLOIT): 753 /* Hypervisor only supports XIVE */ 754 if (xive_cmdline_disabled) 755 pr_warn("WARNING: Ignoring cmdline option xive=off\n"); 756 return false; 757 default: 758 pr_warn("%s: Unknown xive support option: 0x%x\n", 759 __func__, val); 760 break; 761 } 762 } 763 764 return xive_cmdline_disabled; 765 } 766 767 bool __init xive_spapr_init(void) 768 { 769 struct device_node *np; 770 struct resource r; 771 void __iomem *tima; 772 struct property *prop; 773 u8 max_prio; 774 u32 val; 775 u32 len; 776 const __be32 *reg; 777 int i; 778 779 if (xive_spapr_disabled()) 780 return false; 781 782 pr_devel("%s()\n", __func__); 783 np = of_find_compatible_node(NULL, NULL, "ibm,power-ivpe"); 784 if (!np) { 785 pr_devel("not found !\n"); 786 return false; 787 } 788 pr_devel("Found %s\n", np->full_name); 789 790 /* Resource 1 is the OS ring TIMA */ 791 if (of_address_to_resource(np, 1, &r)) { 792 pr_err("Failed to get thread mgmnt area resource\n"); 793 return false; 794 } 795 tima = ioremap(r.start, resource_size(&r)); 796 if (!tima) { 797 pr_err("Failed to map thread mgmnt area\n"); 798 return false; 799 } 800 801 if (!xive_get_max_prio(&max_prio)) 802 return false; 803 804 /* Feed the IRQ number allocator with the ranges given in the DT */ 805 reg = of_get_property(np, "ibm,xive-lisn-ranges", &len); 806 if (!reg) { 807 pr_err("Failed to read 'ibm,xive-lisn-ranges' property\n"); 808 return false; 809 } 810 811 if (len % (2 * sizeof(u32)) != 0) { 812 pr_err("invalid 'ibm,xive-lisn-ranges' property\n"); 813 return false; 814 } 815 816 for (i = 0; i < len / (2 * sizeof(u32)); i++, reg += 2) 817 xive_irq_bitmap_add(be32_to_cpu(reg[0]), 818 be32_to_cpu(reg[1])); 819 820 /* Iterate the EQ sizes and pick one */ 821 of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) { 822 xive_queue_shift = val; 823 if (val == PAGE_SHIFT) 824 break; 825 } 826 827 /* Initialize XIVE core with our backend */ 828 if (!xive_core_init(&xive_spapr_ops, tima, TM_QW1_OS, max_prio)) 829 return false; 830 831 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10)); 832 return true; 833 } 834