1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2016,2017 IBM Corporation. 4 */ 5 6 #define pr_fmt(fmt) "xive: " fmt 7 8 #include <linux/types.h> 9 #include <linux/irq.h> 10 #include <linux/smp.h> 11 #include <linux/interrupt.h> 12 #include <linux/init.h> 13 #include <linux/of.h> 14 #include <linux/slab.h> 15 #include <linux/spinlock.h> 16 #include <linux/cpumask.h> 17 #include <linux/mm.h> 18 #include <linux/delay.h> 19 #include <linux/libfdt.h> 20 21 #include <asm/machdep.h> 22 #include <asm/prom.h> 23 #include <asm/io.h> 24 #include <asm/smp.h> 25 #include <asm/irq.h> 26 #include <asm/errno.h> 27 #include <asm/xive.h> 28 #include <asm/xive-regs.h> 29 #include <asm/hvcall.h> 30 #include <asm/svm.h> 31 #include <asm/ultravisor.h> 32 33 #include "xive-internal.h" 34 35 static u32 xive_queue_shift; 36 37 struct xive_irq_bitmap { 38 unsigned long *bitmap; 39 unsigned int base; 40 unsigned int count; 41 spinlock_t lock; 42 struct list_head list; 43 }; 44 45 static LIST_HEAD(xive_irq_bitmaps); 46 47 static int __init xive_irq_bitmap_add(int base, int count) 48 { 49 struct xive_irq_bitmap *xibm; 50 51 xibm = kzalloc(sizeof(*xibm), GFP_KERNEL); 52 if (!xibm) 53 return -ENOMEM; 54 55 spin_lock_init(&xibm->lock); 56 xibm->base = base; 57 xibm->count = count; 58 xibm->bitmap = kzalloc(xibm->count, GFP_KERNEL); 59 if (!xibm->bitmap) { 60 kfree(xibm); 61 return -ENOMEM; 62 } 63 list_add(&xibm->list, &xive_irq_bitmaps); 64 65 pr_info("Using IRQ range [%x-%x]", xibm->base, 66 xibm->base + xibm->count - 1); 67 return 0; 68 } 69 70 static void xive_irq_bitmap_remove_all(void) 71 { 72 struct xive_irq_bitmap *xibm, *tmp; 73 74 list_for_each_entry_safe(xibm, tmp, &xive_irq_bitmaps, list) { 75 list_del(&xibm->list); 76 kfree(xibm->bitmap); 77 kfree(xibm); 78 } 79 } 80 81 static int __xive_irq_bitmap_alloc(struct xive_irq_bitmap *xibm) 82 { 83 int irq; 84 85 irq = find_first_zero_bit(xibm->bitmap, xibm->count); 86 if (irq != xibm->count) { 87 set_bit(irq, xibm->bitmap); 88 irq += xibm->base; 89 } else { 90 irq = -ENOMEM; 91 } 92 93 return irq; 94 } 95 96 static int xive_irq_bitmap_alloc(void) 97 { 98 struct xive_irq_bitmap *xibm; 99 unsigned long flags; 100 int irq = -ENOENT; 101 102 list_for_each_entry(xibm, &xive_irq_bitmaps, list) { 103 spin_lock_irqsave(&xibm->lock, flags); 104 irq = __xive_irq_bitmap_alloc(xibm); 105 spin_unlock_irqrestore(&xibm->lock, flags); 106 if (irq >= 0) 107 break; 108 } 109 return irq; 110 } 111 112 static void xive_irq_bitmap_free(int irq) 113 { 114 unsigned long flags; 115 struct xive_irq_bitmap *xibm; 116 117 list_for_each_entry(xibm, &xive_irq_bitmaps, list) { 118 if ((irq >= xibm->base) && (irq < xibm->base + xibm->count)) { 119 spin_lock_irqsave(&xibm->lock, flags); 120 clear_bit(irq - xibm->base, xibm->bitmap); 121 spin_unlock_irqrestore(&xibm->lock, flags); 122 break; 123 } 124 } 125 } 126 127 128 /* Based on the similar routines in RTAS */ 129 static unsigned int plpar_busy_delay_time(long rc) 130 { 131 unsigned int ms = 0; 132 133 if (H_IS_LONG_BUSY(rc)) { 134 ms = get_longbusy_msecs(rc); 135 } else if (rc == H_BUSY) { 136 ms = 10; /* seems appropriate for XIVE hcalls */ 137 } 138 139 return ms; 140 } 141 142 static unsigned int plpar_busy_delay(int rc) 143 { 144 unsigned int ms; 145 146 ms = plpar_busy_delay_time(rc); 147 if (ms) 148 mdelay(ms); 149 150 return ms; 151 } 152 153 /* 154 * Note: this call has a partition wide scope and can take a while to 155 * complete. If it returns H_LONG_BUSY_* it should be retried 156 * periodically. 157 */ 158 static long plpar_int_reset(unsigned long flags) 159 { 160 long rc; 161 162 do { 163 rc = plpar_hcall_norets(H_INT_RESET, flags); 164 } while (plpar_busy_delay(rc)); 165 166 if (rc) 167 pr_err("H_INT_RESET failed %ld\n", rc); 168 169 return rc; 170 } 171 172 static long plpar_int_get_source_info(unsigned long flags, 173 unsigned long lisn, 174 unsigned long *src_flags, 175 unsigned long *eoi_page, 176 unsigned long *trig_page, 177 unsigned long *esb_shift) 178 { 179 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 180 long rc; 181 182 do { 183 rc = plpar_hcall(H_INT_GET_SOURCE_INFO, retbuf, flags, lisn); 184 } while (plpar_busy_delay(rc)); 185 186 if (rc) { 187 pr_err("H_INT_GET_SOURCE_INFO lisn=0x%lx failed %ld\n", lisn, rc); 188 return rc; 189 } 190 191 *src_flags = retbuf[0]; 192 *eoi_page = retbuf[1]; 193 *trig_page = retbuf[2]; 194 *esb_shift = retbuf[3]; 195 196 pr_debug("H_INT_GET_SOURCE_INFO lisn=0x%lx flags=0x%lx eoi=0x%lx trig=0x%lx shift=0x%lx\n", 197 lisn, retbuf[0], retbuf[1], retbuf[2], retbuf[3]); 198 199 return 0; 200 } 201 202 #define XIVE_SRC_SET_EISN (1ull << (63 - 62)) 203 #define XIVE_SRC_MASK (1ull << (63 - 63)) /* unused */ 204 205 static long plpar_int_set_source_config(unsigned long flags, 206 unsigned long lisn, 207 unsigned long target, 208 unsigned long prio, 209 unsigned long sw_irq) 210 { 211 long rc; 212 213 214 pr_debug("H_INT_SET_SOURCE_CONFIG flags=0x%lx lisn=0x%lx target=%ld prio=%ld sw_irq=%ld\n", 215 flags, lisn, target, prio, sw_irq); 216 217 218 do { 219 rc = plpar_hcall_norets(H_INT_SET_SOURCE_CONFIG, flags, lisn, 220 target, prio, sw_irq); 221 } while (plpar_busy_delay(rc)); 222 223 if (rc) { 224 pr_err("H_INT_SET_SOURCE_CONFIG lisn=0x%lx target=%ld prio=%ld failed %ld\n", 225 lisn, target, prio, rc); 226 return rc; 227 } 228 229 return 0; 230 } 231 232 static long plpar_int_get_source_config(unsigned long flags, 233 unsigned long lisn, 234 unsigned long *target, 235 unsigned long *prio, 236 unsigned long *sw_irq) 237 { 238 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 239 long rc; 240 241 pr_debug("H_INT_GET_SOURCE_CONFIG flags=0x%lx lisn=0x%lx\n", flags, lisn); 242 243 do { 244 rc = plpar_hcall(H_INT_GET_SOURCE_CONFIG, retbuf, flags, lisn, 245 target, prio, sw_irq); 246 } while (plpar_busy_delay(rc)); 247 248 if (rc) { 249 pr_err("H_INT_GET_SOURCE_CONFIG lisn=0x%lx failed %ld\n", 250 lisn, rc); 251 return rc; 252 } 253 254 *target = retbuf[0]; 255 *prio = retbuf[1]; 256 *sw_irq = retbuf[2]; 257 258 pr_debug("H_INT_GET_SOURCE_CONFIG target=%ld prio=%ld sw_irq=%ld\n", 259 retbuf[0], retbuf[1], retbuf[2]); 260 261 return 0; 262 } 263 264 static long plpar_int_get_queue_info(unsigned long flags, 265 unsigned long target, 266 unsigned long priority, 267 unsigned long *esn_page, 268 unsigned long *esn_size) 269 { 270 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 271 long rc; 272 273 do { 274 rc = plpar_hcall(H_INT_GET_QUEUE_INFO, retbuf, flags, target, 275 priority); 276 } while (plpar_busy_delay(rc)); 277 278 if (rc) { 279 pr_err("H_INT_GET_QUEUE_INFO cpu=%ld prio=%ld failed %ld\n", 280 target, priority, rc); 281 return rc; 282 } 283 284 *esn_page = retbuf[0]; 285 *esn_size = retbuf[1]; 286 287 pr_debug("H_INT_GET_QUEUE_INFO cpu=%ld prio=%ld page=0x%lx size=0x%lx\n", 288 target, priority, retbuf[0], retbuf[1]); 289 290 return 0; 291 } 292 293 #define XIVE_EQ_ALWAYS_NOTIFY (1ull << (63 - 63)) 294 295 static long plpar_int_set_queue_config(unsigned long flags, 296 unsigned long target, 297 unsigned long priority, 298 unsigned long qpage, 299 unsigned long qsize) 300 { 301 long rc; 302 303 pr_debug("H_INT_SET_QUEUE_CONFIG flags=0x%lx target=%ld priority=0x%lx qpage=0x%lx qsize=0x%lx\n", 304 flags, target, priority, qpage, qsize); 305 306 do { 307 rc = plpar_hcall_norets(H_INT_SET_QUEUE_CONFIG, flags, target, 308 priority, qpage, qsize); 309 } while (plpar_busy_delay(rc)); 310 311 if (rc) { 312 pr_err("H_INT_SET_QUEUE_CONFIG cpu=%ld prio=%ld qpage=0x%lx returned %ld\n", 313 target, priority, qpage, rc); 314 return rc; 315 } 316 317 return 0; 318 } 319 320 static long plpar_int_sync(unsigned long flags, unsigned long lisn) 321 { 322 long rc; 323 324 do { 325 rc = plpar_hcall_norets(H_INT_SYNC, flags, lisn); 326 } while (plpar_busy_delay(rc)); 327 328 if (rc) { 329 pr_err("H_INT_SYNC lisn=0x%lx returned %ld\n", lisn, rc); 330 return rc; 331 } 332 333 return 0; 334 } 335 336 #define XIVE_ESB_FLAG_STORE (1ull << (63 - 63)) 337 338 static long plpar_int_esb(unsigned long flags, 339 unsigned long lisn, 340 unsigned long offset, 341 unsigned long in_data, 342 unsigned long *out_data) 343 { 344 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 345 long rc; 346 347 pr_debug("H_INT_ESB flags=0x%lx lisn=0x%lx offset=0x%lx in=0x%lx\n", 348 flags, lisn, offset, in_data); 349 350 do { 351 rc = plpar_hcall(H_INT_ESB, retbuf, flags, lisn, offset, 352 in_data); 353 } while (plpar_busy_delay(rc)); 354 355 if (rc) { 356 pr_err("H_INT_ESB lisn=0x%lx offset=0x%lx returned %ld\n", 357 lisn, offset, rc); 358 return rc; 359 } 360 361 *out_data = retbuf[0]; 362 363 return 0; 364 } 365 366 static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64 data, bool write) 367 { 368 unsigned long read_data; 369 long rc; 370 371 rc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0, 372 lisn, offset, data, &read_data); 373 if (rc) 374 return -1; 375 376 return write ? 0 : read_data; 377 } 378 379 #define XIVE_SRC_H_INT_ESB (1ull << (63 - 60)) 380 #define XIVE_SRC_LSI (1ull << (63 - 61)) 381 #define XIVE_SRC_TRIGGER (1ull << (63 - 62)) 382 #define XIVE_SRC_STORE_EOI (1ull << (63 - 63)) 383 384 static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data) 385 { 386 long rc; 387 unsigned long flags; 388 unsigned long eoi_page; 389 unsigned long trig_page; 390 unsigned long esb_shift; 391 392 memset(data, 0, sizeof(*data)); 393 394 rc = plpar_int_get_source_info(0, hw_irq, &flags, &eoi_page, &trig_page, 395 &esb_shift); 396 if (rc) 397 return -EINVAL; 398 399 if (flags & XIVE_SRC_H_INT_ESB) 400 data->flags |= XIVE_IRQ_FLAG_H_INT_ESB; 401 if (flags & XIVE_SRC_STORE_EOI) 402 data->flags |= XIVE_IRQ_FLAG_STORE_EOI; 403 if (flags & XIVE_SRC_LSI) 404 data->flags |= XIVE_IRQ_FLAG_LSI; 405 data->eoi_page = eoi_page; 406 data->esb_shift = esb_shift; 407 data->trig_page = trig_page; 408 409 data->hw_irq = hw_irq; 410 411 /* 412 * No chip-id for the sPAPR backend. This has an impact how we 413 * pick a target. See xive_pick_irq_target(). 414 */ 415 data->src_chip = XIVE_INVALID_CHIP_ID; 416 417 /* 418 * When the H_INT_ESB flag is set, the H_INT_ESB hcall should 419 * be used for interrupt management. Skip the remapping of the 420 * ESB pages which are not available. 421 */ 422 if (data->flags & XIVE_IRQ_FLAG_H_INT_ESB) 423 return 0; 424 425 data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift); 426 if (!data->eoi_mmio) { 427 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq); 428 return -ENOMEM; 429 } 430 431 /* Full function page supports trigger */ 432 if (flags & XIVE_SRC_TRIGGER) { 433 data->trig_mmio = data->eoi_mmio; 434 return 0; 435 } 436 437 data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift); 438 if (!data->trig_mmio) { 439 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq); 440 return -ENOMEM; 441 } 442 return 0; 443 } 444 445 static int xive_spapr_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) 446 { 447 long rc; 448 449 rc = plpar_int_set_source_config(XIVE_SRC_SET_EISN, hw_irq, target, 450 prio, sw_irq); 451 452 return rc == 0 ? 0 : -ENXIO; 453 } 454 455 static int xive_spapr_get_irq_config(u32 hw_irq, u32 *target, u8 *prio, 456 u32 *sw_irq) 457 { 458 long rc; 459 unsigned long h_target; 460 unsigned long h_prio; 461 unsigned long h_sw_irq; 462 463 rc = plpar_int_get_source_config(0, hw_irq, &h_target, &h_prio, 464 &h_sw_irq); 465 466 *target = h_target; 467 *prio = h_prio; 468 *sw_irq = h_sw_irq; 469 470 return rc == 0 ? 0 : -ENXIO; 471 } 472 473 /* This can be called multiple time to change a queue configuration */ 474 static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio, 475 __be32 *qpage, u32 order) 476 { 477 s64 rc = 0; 478 unsigned long esn_page; 479 unsigned long esn_size; 480 u64 flags, qpage_phys; 481 482 /* If there's an actual queue page, clean it */ 483 if (order) { 484 if (WARN_ON(!qpage)) 485 return -EINVAL; 486 qpage_phys = __pa(qpage); 487 } else { 488 qpage_phys = 0; 489 } 490 491 /* Initialize the rest of the fields */ 492 q->msk = order ? ((1u << (order - 2)) - 1) : 0; 493 q->idx = 0; 494 q->toggle = 0; 495 496 rc = plpar_int_get_queue_info(0, target, prio, &esn_page, &esn_size); 497 if (rc) { 498 pr_err("Error %lld getting queue info CPU %d prio %d\n", rc, 499 target, prio); 500 rc = -EIO; 501 goto fail; 502 } 503 504 /* TODO: add support for the notification page */ 505 q->eoi_phys = esn_page; 506 507 /* Default is to always notify */ 508 flags = XIVE_EQ_ALWAYS_NOTIFY; 509 510 /* Configure and enable the queue in HW */ 511 rc = plpar_int_set_queue_config(flags, target, prio, qpage_phys, order); 512 if (rc) { 513 pr_err("Error %lld setting queue for CPU %d prio %d\n", rc, 514 target, prio); 515 rc = -EIO; 516 } else { 517 q->qpage = qpage; 518 if (is_secure_guest()) 519 uv_share_page(PHYS_PFN(qpage_phys), 520 1 << xive_alloc_order(order)); 521 } 522 fail: 523 return rc; 524 } 525 526 static int xive_spapr_setup_queue(unsigned int cpu, struct xive_cpu *xc, 527 u8 prio) 528 { 529 struct xive_q *q = &xc->queue[prio]; 530 __be32 *qpage; 531 532 qpage = xive_queue_page_alloc(cpu, xive_queue_shift); 533 if (IS_ERR(qpage)) 534 return PTR_ERR(qpage); 535 536 return xive_spapr_configure_queue(get_hard_smp_processor_id(cpu), 537 q, prio, qpage, xive_queue_shift); 538 } 539 540 static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, 541 u8 prio) 542 { 543 struct xive_q *q = &xc->queue[prio]; 544 unsigned int alloc_order; 545 long rc; 546 int hw_cpu = get_hard_smp_processor_id(cpu); 547 548 rc = plpar_int_set_queue_config(0, hw_cpu, prio, 0, 0); 549 if (rc) 550 pr_err("Error %ld setting queue for CPU %d prio %d\n", rc, 551 hw_cpu, prio); 552 553 alloc_order = xive_alloc_order(xive_queue_shift); 554 if (is_secure_guest()) 555 uv_unshare_page(PHYS_PFN(__pa(q->qpage)), 1 << alloc_order); 556 free_pages((unsigned long)q->qpage, alloc_order); 557 q->qpage = NULL; 558 } 559 560 static bool xive_spapr_match(struct device_node *node) 561 { 562 /* Ignore cascaded controllers for the moment */ 563 return true; 564 } 565 566 #ifdef CONFIG_SMP 567 static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc) 568 { 569 int irq = xive_irq_bitmap_alloc(); 570 571 if (irq < 0) { 572 pr_err("Failed to allocate IPI on CPU %d\n", cpu); 573 return -ENXIO; 574 } 575 576 xc->hw_ipi = irq; 577 return 0; 578 } 579 580 static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc) 581 { 582 if (xc->hw_ipi == XIVE_BAD_IRQ) 583 return; 584 585 xive_irq_bitmap_free(xc->hw_ipi); 586 xc->hw_ipi = XIVE_BAD_IRQ; 587 } 588 #endif /* CONFIG_SMP */ 589 590 static void xive_spapr_shutdown(void) 591 { 592 plpar_int_reset(0); 593 } 594 595 /* 596 * Perform an "ack" cycle on the current thread. Grab the pending 597 * active priorities and update the CPPR to the most favored one. 598 */ 599 static void xive_spapr_update_pending(struct xive_cpu *xc) 600 { 601 u8 nsr, cppr; 602 u16 ack; 603 604 /* 605 * Perform the "Acknowledge O/S to Register" cycle. 606 * 607 * Let's speedup the access to the TIMA using the raw I/O 608 * accessor as we don't need the synchronisation routine of 609 * the higher level ones 610 */ 611 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_OS_REG)); 612 613 /* Synchronize subsequent queue accesses */ 614 mb(); 615 616 /* 617 * Grab the CPPR and the "NSR" field which indicates the source 618 * of the interrupt (if any) 619 */ 620 cppr = ack & 0xff; 621 nsr = ack >> 8; 622 623 if (nsr & TM_QW1_NSR_EO) { 624 if (cppr == 0xff) 625 return; 626 /* Mark the priority pending */ 627 xc->pending_prio |= 1 << cppr; 628 629 /* 630 * A new interrupt should never have a CPPR less favored 631 * than our current one. 632 */ 633 if (cppr >= xc->cppr) 634 pr_err("CPU %d odd ack CPPR, got %d at %d\n", 635 smp_processor_id(), cppr, xc->cppr); 636 637 /* Update our idea of what the CPPR is */ 638 xc->cppr = cppr; 639 } 640 } 641 642 static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc) 643 { 644 /* Only some debug on the TIMA settings */ 645 pr_debug("(HW value: %08x %08x %08x)\n", 646 in_be32(xive_tima + TM_QW1_OS + TM_WORD0), 647 in_be32(xive_tima + TM_QW1_OS + TM_WORD1), 648 in_be32(xive_tima + TM_QW1_OS + TM_WORD2)); 649 } 650 651 static void xive_spapr_teardown_cpu(unsigned int cpu, struct xive_cpu *xc) 652 { 653 /* Nothing to do */; 654 } 655 656 static void xive_spapr_sync_source(u32 hw_irq) 657 { 658 /* Specs are unclear on what this is doing */ 659 plpar_int_sync(0, hw_irq); 660 } 661 662 static int xive_spapr_debug_show(struct seq_file *m, void *private) 663 { 664 struct xive_irq_bitmap *xibm; 665 char *buf = kmalloc(PAGE_SIZE, GFP_KERNEL); 666 667 if (!buf) 668 return -ENOMEM; 669 670 list_for_each_entry(xibm, &xive_irq_bitmaps, list) { 671 memset(buf, 0, PAGE_SIZE); 672 bitmap_print_to_pagebuf(true, buf, xibm->bitmap, xibm->count); 673 seq_printf(m, "bitmap #%d: %s", xibm->count, buf); 674 } 675 kfree(buf); 676 677 return 0; 678 } 679 680 static const struct xive_ops xive_spapr_ops = { 681 .populate_irq_data = xive_spapr_populate_irq_data, 682 .configure_irq = xive_spapr_configure_irq, 683 .get_irq_config = xive_spapr_get_irq_config, 684 .setup_queue = xive_spapr_setup_queue, 685 .cleanup_queue = xive_spapr_cleanup_queue, 686 .match = xive_spapr_match, 687 .shutdown = xive_spapr_shutdown, 688 .update_pending = xive_spapr_update_pending, 689 .setup_cpu = xive_spapr_setup_cpu, 690 .teardown_cpu = xive_spapr_teardown_cpu, 691 .sync_source = xive_spapr_sync_source, 692 .esb_rw = xive_spapr_esb_rw, 693 #ifdef CONFIG_SMP 694 .get_ipi = xive_spapr_get_ipi, 695 .put_ipi = xive_spapr_put_ipi, 696 .debug_show = xive_spapr_debug_show, 697 #endif /* CONFIG_SMP */ 698 .name = "spapr", 699 }; 700 701 /* 702 * get max priority from "/ibm,plat-res-int-priorities" 703 */ 704 static bool __init xive_get_max_prio(u8 *max_prio) 705 { 706 struct device_node *rootdn; 707 const __be32 *reg; 708 u32 len; 709 int prio, found; 710 711 rootdn = of_find_node_by_path("/"); 712 if (!rootdn) { 713 pr_err("not root node found !\n"); 714 return false; 715 } 716 717 reg = of_get_property(rootdn, "ibm,plat-res-int-priorities", &len); 718 if (!reg) { 719 pr_err("Failed to read 'ibm,plat-res-int-priorities' property\n"); 720 return false; 721 } 722 723 if (len % (2 * sizeof(u32)) != 0) { 724 pr_err("invalid 'ibm,plat-res-int-priorities' property\n"); 725 return false; 726 } 727 728 /* HW supports priorities in the range [0-7] and 0xFF is a 729 * wildcard priority used to mask. We scan the ranges reserved 730 * by the hypervisor to find the lowest priority we can use. 731 */ 732 found = 0xFF; 733 for (prio = 0; prio < 8; prio++) { 734 int reserved = 0; 735 int i; 736 737 for (i = 0; i < len / (2 * sizeof(u32)); i++) { 738 int base = be32_to_cpu(reg[2 * i]); 739 int range = be32_to_cpu(reg[2 * i + 1]); 740 741 if (prio >= base && prio < base + range) 742 reserved++; 743 } 744 745 if (!reserved) 746 found = prio; 747 } 748 749 if (found == 0xFF) { 750 pr_err("no valid priority found in 'ibm,plat-res-int-priorities'\n"); 751 return false; 752 } 753 754 *max_prio = found; 755 return true; 756 } 757 758 static const u8 *__init get_vec5_feature(unsigned int index) 759 { 760 unsigned long root, chosen; 761 int size; 762 const u8 *vec5; 763 764 root = of_get_flat_dt_root(); 765 chosen = of_get_flat_dt_subnode_by_name(root, "chosen"); 766 if (chosen == -FDT_ERR_NOTFOUND) 767 return NULL; 768 769 vec5 = of_get_flat_dt_prop(chosen, "ibm,architecture-vec-5", &size); 770 if (!vec5) 771 return NULL; 772 773 if (size <= index) 774 return NULL; 775 776 return vec5 + index; 777 } 778 779 static bool __init xive_spapr_disabled(void) 780 { 781 const u8 *vec5_xive; 782 783 vec5_xive = get_vec5_feature(OV5_INDX(OV5_XIVE_SUPPORT)); 784 if (vec5_xive) { 785 u8 val; 786 787 val = *vec5_xive & OV5_FEAT(OV5_XIVE_SUPPORT); 788 switch (val) { 789 case OV5_FEAT(OV5_XIVE_EITHER): 790 case OV5_FEAT(OV5_XIVE_LEGACY): 791 break; 792 case OV5_FEAT(OV5_XIVE_EXPLOIT): 793 /* Hypervisor only supports XIVE */ 794 if (xive_cmdline_disabled) 795 pr_warn("WARNING: Ignoring cmdline option xive=off\n"); 796 return false; 797 default: 798 pr_warn("%s: Unknown xive support option: 0x%x\n", 799 __func__, val); 800 break; 801 } 802 } 803 804 return xive_cmdline_disabled; 805 } 806 807 bool __init xive_spapr_init(void) 808 { 809 struct device_node *np; 810 struct resource r; 811 void __iomem *tima; 812 struct property *prop; 813 u8 max_prio; 814 u32 val; 815 u32 len; 816 const __be32 *reg; 817 int i, err; 818 819 if (xive_spapr_disabled()) 820 return false; 821 822 pr_devel("%s()\n", __func__); 823 np = of_find_compatible_node(NULL, NULL, "ibm,power-ivpe"); 824 if (!np) { 825 pr_devel("not found !\n"); 826 return false; 827 } 828 pr_devel("Found %s\n", np->full_name); 829 830 /* Resource 1 is the OS ring TIMA */ 831 if (of_address_to_resource(np, 1, &r)) { 832 pr_err("Failed to get thread mgmnt area resource\n"); 833 return false; 834 } 835 tima = ioremap(r.start, resource_size(&r)); 836 if (!tima) { 837 pr_err("Failed to map thread mgmnt area\n"); 838 return false; 839 } 840 841 if (!xive_get_max_prio(&max_prio)) 842 goto err_unmap; 843 844 /* Feed the IRQ number allocator with the ranges given in the DT */ 845 reg = of_get_property(np, "ibm,xive-lisn-ranges", &len); 846 if (!reg) { 847 pr_err("Failed to read 'ibm,xive-lisn-ranges' property\n"); 848 goto err_unmap; 849 } 850 851 if (len % (2 * sizeof(u32)) != 0) { 852 pr_err("invalid 'ibm,xive-lisn-ranges' property\n"); 853 goto err_unmap; 854 } 855 856 for (i = 0; i < len / (2 * sizeof(u32)); i++, reg += 2) { 857 err = xive_irq_bitmap_add(be32_to_cpu(reg[0]), 858 be32_to_cpu(reg[1])); 859 if (err < 0) 860 goto err_mem_free; 861 } 862 863 /* Iterate the EQ sizes and pick one */ 864 of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) { 865 xive_queue_shift = val; 866 if (val == PAGE_SHIFT) 867 break; 868 } 869 870 /* Initialize XIVE core with our backend */ 871 if (!xive_core_init(np, &xive_spapr_ops, tima, TM_QW1_OS, max_prio)) 872 goto err_mem_free; 873 874 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10)); 875 return true; 876 877 err_mem_free: 878 xive_irq_bitmap_remove_all(); 879 err_unmap: 880 iounmap(tima); 881 return false; 882 } 883 884 machine_arch_initcall(pseries, xive_core_debug_init); 885