1 /* 2 * Copyright 2016,2017 IBM Corporation. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #define pr_fmt(fmt) "xive: " fmt 11 12 #include <linux/types.h> 13 #include <linux/irq.h> 14 #include <linux/debugfs.h> 15 #include <linux/smp.h> 16 #include <linux/interrupt.h> 17 #include <linux/seq_file.h> 18 #include <linux/init.h> 19 #include <linux/of.h> 20 #include <linux/slab.h> 21 #include <linux/spinlock.h> 22 #include <linux/delay.h> 23 #include <linux/cpumask.h> 24 #include <linux/mm.h> 25 26 #include <asm/prom.h> 27 #include <asm/io.h> 28 #include <asm/smp.h> 29 #include <asm/irq.h> 30 #include <asm/errno.h> 31 #include <asm/xive.h> 32 #include <asm/xive-regs.h> 33 #include <asm/opal.h> 34 #include <asm/kvm_ppc.h> 35 36 #include "xive-internal.h" 37 38 39 static u32 xive_provision_size; 40 static u32 *xive_provision_chips; 41 static u32 xive_provision_chip_count; 42 static u32 xive_queue_shift; 43 static u32 xive_pool_vps = XIVE_INVALID_VP; 44 static struct kmem_cache *xive_provision_cache; 45 static bool xive_has_single_esc; 46 47 int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data) 48 { 49 __be64 flags, eoi_page, trig_page; 50 __be32 esb_shift, src_chip; 51 u64 opal_flags; 52 s64 rc; 53 54 memset(data, 0, sizeof(*data)); 55 56 rc = opal_xive_get_irq_info(hw_irq, &flags, &eoi_page, &trig_page, 57 &esb_shift, &src_chip); 58 if (rc) { 59 pr_err("opal_xive_get_irq_info(0x%x) returned %lld\n", 60 hw_irq, rc); 61 return -EINVAL; 62 } 63 64 opal_flags = be64_to_cpu(flags); 65 if (opal_flags & OPAL_XIVE_IRQ_STORE_EOI) 66 data->flags |= XIVE_IRQ_FLAG_STORE_EOI; 67 if (opal_flags & OPAL_XIVE_IRQ_LSI) 68 data->flags |= XIVE_IRQ_FLAG_LSI; 69 if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG) 70 data->flags |= XIVE_IRQ_FLAG_SHIFT_BUG; 71 if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW) 72 data->flags |= XIVE_IRQ_FLAG_MASK_FW; 73 if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW) 74 data->flags |= XIVE_IRQ_FLAG_EOI_FW; 75 data->eoi_page = be64_to_cpu(eoi_page); 76 data->trig_page = be64_to_cpu(trig_page); 77 data->esb_shift = be32_to_cpu(esb_shift); 78 data->src_chip = be32_to_cpu(src_chip); 79 80 data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift); 81 if (!data->eoi_mmio) { 82 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq); 83 return -ENOMEM; 84 } 85 86 data->hw_irq = hw_irq; 87 88 if (!data->trig_page) 89 return 0; 90 if (data->trig_page == data->eoi_page) { 91 data->trig_mmio = data->eoi_mmio; 92 return 0; 93 } 94 95 data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift); 96 if (!data->trig_mmio) { 97 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq); 98 return -ENOMEM; 99 } 100 return 0; 101 } 102 EXPORT_SYMBOL_GPL(xive_native_populate_irq_data); 103 104 int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) 105 { 106 s64 rc; 107 108 for (;;) { 109 rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq); 110 if (rc != OPAL_BUSY) 111 break; 112 msleep(OPAL_BUSY_DELAY_MS); 113 } 114 return rc == 0 ? 0 : -ENXIO; 115 } 116 EXPORT_SYMBOL_GPL(xive_native_configure_irq); 117 118 119 /* This can be called multiple time to change a queue configuration */ 120 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, 121 __be32 *qpage, u32 order, bool can_escalate) 122 { 123 s64 rc = 0; 124 __be64 qeoi_page_be; 125 __be32 esc_irq_be; 126 u64 flags, qpage_phys; 127 128 /* If there's an actual queue page, clean it */ 129 if (order) { 130 if (WARN_ON(!qpage)) 131 return -EINVAL; 132 qpage_phys = __pa(qpage); 133 } else 134 qpage_phys = 0; 135 136 /* Initialize the rest of the fields */ 137 q->msk = order ? ((1u << (order - 2)) - 1) : 0; 138 q->idx = 0; 139 q->toggle = 0; 140 141 rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL, 142 &qeoi_page_be, 143 &esc_irq_be, 144 NULL); 145 if (rc) { 146 pr_err("Error %lld getting queue info prio %d\n", rc, prio); 147 rc = -EIO; 148 goto fail; 149 } 150 q->eoi_phys = be64_to_cpu(qeoi_page_be); 151 152 /* Default flags */ 153 flags = OPAL_XIVE_EQ_ALWAYS_NOTIFY | OPAL_XIVE_EQ_ENABLED; 154 155 /* Escalation needed ? */ 156 if (can_escalate) { 157 q->esc_irq = be32_to_cpu(esc_irq_be); 158 flags |= OPAL_XIVE_EQ_ESCALATE; 159 } 160 161 /* Configure and enable the queue in HW */ 162 for (;;) { 163 rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags); 164 if (rc != OPAL_BUSY) 165 break; 166 msleep(OPAL_BUSY_DELAY_MS); 167 } 168 if (rc) { 169 pr_err("Error %lld setting queue for prio %d\n", rc, prio); 170 rc = -EIO; 171 } else { 172 /* 173 * KVM code requires all of the above to be visible before 174 * q->qpage is set due to how it manages IPI EOIs 175 */ 176 wmb(); 177 q->qpage = qpage; 178 } 179 fail: 180 return rc; 181 } 182 EXPORT_SYMBOL_GPL(xive_native_configure_queue); 183 184 static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) 185 { 186 s64 rc; 187 188 /* Disable the queue in HW */ 189 for (;;) { 190 rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0); 191 if (rc != OPAL_BUSY) 192 break; 193 msleep(OPAL_BUSY_DELAY_MS); 194 } 195 if (rc) 196 pr_err("Error %lld disabling queue for prio %d\n", rc, prio); 197 } 198 199 void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) 200 { 201 __xive_native_disable_queue(vp_id, q, prio); 202 } 203 EXPORT_SYMBOL_GPL(xive_native_disable_queue); 204 205 static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio) 206 { 207 struct xive_q *q = &xc->queue[prio]; 208 __be32 *qpage; 209 210 qpage = xive_queue_page_alloc(cpu, xive_queue_shift); 211 if (IS_ERR(qpage)) 212 return PTR_ERR(qpage); 213 214 return xive_native_configure_queue(get_hard_smp_processor_id(cpu), 215 q, prio, qpage, xive_queue_shift, false); 216 } 217 218 static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio) 219 { 220 struct xive_q *q = &xc->queue[prio]; 221 unsigned int alloc_order; 222 223 /* 224 * We use the variant with no iounmap as this is called on exec 225 * from an IPI and iounmap isn't safe 226 */ 227 __xive_native_disable_queue(get_hard_smp_processor_id(cpu), q, prio); 228 alloc_order = xive_alloc_order(xive_queue_shift); 229 free_pages((unsigned long)q->qpage, alloc_order); 230 q->qpage = NULL; 231 } 232 233 static bool xive_native_match(struct device_node *node) 234 { 235 return of_device_is_compatible(node, "ibm,opal-xive-vc"); 236 } 237 238 #ifdef CONFIG_SMP 239 static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc) 240 { 241 struct device_node *np; 242 unsigned int chip_id; 243 s64 irq; 244 245 /* Find the chip ID */ 246 np = of_get_cpu_node(cpu, NULL); 247 if (np) { 248 if (of_property_read_u32(np, "ibm,chip-id", &chip_id) < 0) 249 chip_id = 0; 250 } 251 252 /* Allocate an IPI and populate info about it */ 253 for (;;) { 254 irq = opal_xive_allocate_irq(chip_id); 255 if (irq == OPAL_BUSY) { 256 msleep(OPAL_BUSY_DELAY_MS); 257 continue; 258 } 259 if (irq < 0) { 260 pr_err("Failed to allocate IPI on CPU %d\n", cpu); 261 return -ENXIO; 262 } 263 xc->hw_ipi = irq; 264 break; 265 } 266 return 0; 267 } 268 #endif /* CONFIG_SMP */ 269 270 u32 xive_native_alloc_irq(void) 271 { 272 s64 rc; 273 274 for (;;) { 275 rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP); 276 if (rc != OPAL_BUSY) 277 break; 278 msleep(OPAL_BUSY_DELAY_MS); 279 } 280 if (rc < 0) 281 return 0; 282 return rc; 283 } 284 EXPORT_SYMBOL_GPL(xive_native_alloc_irq); 285 286 void xive_native_free_irq(u32 irq) 287 { 288 for (;;) { 289 s64 rc = opal_xive_free_irq(irq); 290 if (rc != OPAL_BUSY) 291 break; 292 msleep(OPAL_BUSY_DELAY_MS); 293 } 294 } 295 EXPORT_SYMBOL_GPL(xive_native_free_irq); 296 297 #ifdef CONFIG_SMP 298 static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc) 299 { 300 s64 rc; 301 302 /* Free the IPI */ 303 if (!xc->hw_ipi) 304 return; 305 for (;;) { 306 rc = opal_xive_free_irq(xc->hw_ipi); 307 if (rc == OPAL_BUSY) { 308 msleep(OPAL_BUSY_DELAY_MS); 309 continue; 310 } 311 xc->hw_ipi = 0; 312 break; 313 } 314 } 315 #endif /* CONFIG_SMP */ 316 317 static void xive_native_shutdown(void) 318 { 319 /* Switch the XIVE to emulation mode */ 320 opal_xive_reset(OPAL_XIVE_MODE_EMU); 321 } 322 323 /* 324 * Perform an "ack" cycle on the current thread, thus 325 * grabbing the pending active priorities and updating 326 * the CPPR to the most favored one. 327 */ 328 static void xive_native_update_pending(struct xive_cpu *xc) 329 { 330 u8 he, cppr; 331 u16 ack; 332 333 /* Perform the acknowledge hypervisor to register cycle */ 334 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_HV_REG)); 335 336 /* Synchronize subsequent queue accesses */ 337 mb(); 338 339 /* 340 * Grab the CPPR and the "HE" field which indicates the source 341 * of the hypervisor interrupt (if any) 342 */ 343 cppr = ack & 0xff; 344 he = (ack >> 8) >> 6; 345 switch(he) { 346 case TM_QW3_NSR_HE_NONE: /* Nothing to see here */ 347 break; 348 case TM_QW3_NSR_HE_PHYS: /* Physical thread interrupt */ 349 if (cppr == 0xff) 350 return; 351 /* Mark the priority pending */ 352 xc->pending_prio |= 1 << cppr; 353 354 /* 355 * A new interrupt should never have a CPPR less favored 356 * than our current one. 357 */ 358 if (cppr >= xc->cppr) 359 pr_err("CPU %d odd ack CPPR, got %d at %d\n", 360 smp_processor_id(), cppr, xc->cppr); 361 362 /* Update our idea of what the CPPR is */ 363 xc->cppr = cppr; 364 break; 365 case TM_QW3_NSR_HE_POOL: /* HV Pool interrupt (unused) */ 366 case TM_QW3_NSR_HE_LSI: /* Legacy FW LSI (unused) */ 367 pr_err("CPU %d got unexpected interrupt type HE=%d\n", 368 smp_processor_id(), he); 369 return; 370 } 371 } 372 373 static void xive_native_eoi(u32 hw_irq) 374 { 375 /* 376 * Not normally used except if specific interrupts need 377 * a workaround on EOI. 378 */ 379 opal_int_eoi(hw_irq); 380 } 381 382 static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc) 383 { 384 s64 rc; 385 u32 vp; 386 __be64 vp_cam_be; 387 u64 vp_cam; 388 389 if (xive_pool_vps == XIVE_INVALID_VP) 390 return; 391 392 /* Check if pool VP already active, if it is, pull it */ 393 if (in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2) & TM_QW2W2_VP) 394 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX); 395 396 /* Enable the pool VP */ 397 vp = xive_pool_vps + cpu; 398 for (;;) { 399 rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0); 400 if (rc != OPAL_BUSY) 401 break; 402 msleep(OPAL_BUSY_DELAY_MS); 403 } 404 if (rc) { 405 pr_err("Failed to enable pool VP on CPU %d\n", cpu); 406 return; 407 } 408 409 /* Grab it's CAM value */ 410 rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL); 411 if (rc) { 412 pr_err("Failed to get pool VP info CPU %d\n", cpu); 413 return; 414 } 415 vp_cam = be64_to_cpu(vp_cam_be); 416 417 /* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */ 418 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff); 419 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2, TM_QW2W2_VP | vp_cam); 420 } 421 422 static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc) 423 { 424 s64 rc; 425 u32 vp; 426 427 if (xive_pool_vps == XIVE_INVALID_VP) 428 return; 429 430 /* Pull the pool VP from the CPU */ 431 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX); 432 433 /* Disable it */ 434 vp = xive_pool_vps + cpu; 435 for (;;) { 436 rc = opal_xive_set_vp_info(vp, 0, 0); 437 if (rc != OPAL_BUSY) 438 break; 439 msleep(OPAL_BUSY_DELAY_MS); 440 } 441 } 442 443 void xive_native_sync_source(u32 hw_irq) 444 { 445 opal_xive_sync(XIVE_SYNC_EAS, hw_irq); 446 } 447 EXPORT_SYMBOL_GPL(xive_native_sync_source); 448 449 static const struct xive_ops xive_native_ops = { 450 .populate_irq_data = xive_native_populate_irq_data, 451 .configure_irq = xive_native_configure_irq, 452 .setup_queue = xive_native_setup_queue, 453 .cleanup_queue = xive_native_cleanup_queue, 454 .match = xive_native_match, 455 .shutdown = xive_native_shutdown, 456 .update_pending = xive_native_update_pending, 457 .eoi = xive_native_eoi, 458 .setup_cpu = xive_native_setup_cpu, 459 .teardown_cpu = xive_native_teardown_cpu, 460 .sync_source = xive_native_sync_source, 461 #ifdef CONFIG_SMP 462 .get_ipi = xive_native_get_ipi, 463 .put_ipi = xive_native_put_ipi, 464 #endif /* CONFIG_SMP */ 465 .name = "native", 466 }; 467 468 static bool xive_parse_provisioning(struct device_node *np) 469 { 470 int rc; 471 472 if (of_property_read_u32(np, "ibm,xive-provision-page-size", 473 &xive_provision_size) < 0) 474 return true; 475 rc = of_property_count_elems_of_size(np, "ibm,xive-provision-chips", 4); 476 if (rc < 0) { 477 pr_err("Error %d getting provision chips array\n", rc); 478 return false; 479 } 480 xive_provision_chip_count = rc; 481 if (rc == 0) 482 return true; 483 484 xive_provision_chips = kcalloc(4, xive_provision_chip_count, 485 GFP_KERNEL); 486 if (WARN_ON(!xive_provision_chips)) 487 return false; 488 489 rc = of_property_read_u32_array(np, "ibm,xive-provision-chips", 490 xive_provision_chips, 491 xive_provision_chip_count); 492 if (rc < 0) { 493 pr_err("Error %d reading provision chips array\n", rc); 494 return false; 495 } 496 497 xive_provision_cache = kmem_cache_create("xive-provision", 498 xive_provision_size, 499 xive_provision_size, 500 0, NULL); 501 if (!xive_provision_cache) { 502 pr_err("Failed to allocate provision cache\n"); 503 return false; 504 } 505 return true; 506 } 507 508 static void xive_native_setup_pools(void) 509 { 510 /* Allocate a pool big enough */ 511 pr_debug("XIVE: Allocating VP block for pool size %u\n", nr_cpu_ids); 512 513 xive_pool_vps = xive_native_alloc_vp_block(nr_cpu_ids); 514 if (WARN_ON(xive_pool_vps == XIVE_INVALID_VP)) 515 pr_err("XIVE: Failed to allocate pool VP, KVM might not function\n"); 516 517 pr_debug("XIVE: Pool VPs allocated at 0x%x for %u max CPUs\n", 518 xive_pool_vps, nr_cpu_ids); 519 } 520 521 u32 xive_native_default_eq_shift(void) 522 { 523 return xive_queue_shift; 524 } 525 EXPORT_SYMBOL_GPL(xive_native_default_eq_shift); 526 527 bool __init xive_native_init(void) 528 { 529 struct device_node *np; 530 struct resource r; 531 void __iomem *tima; 532 struct property *prop; 533 u8 max_prio = 7; 534 const __be32 *p; 535 u32 val, cpu; 536 s64 rc; 537 538 if (xive_cmdline_disabled) 539 return false; 540 541 pr_devel("xive_native_init()\n"); 542 np = of_find_compatible_node(NULL, NULL, "ibm,opal-xive-pe"); 543 if (!np) { 544 pr_devel("not found !\n"); 545 return false; 546 } 547 pr_devel("Found %pOF\n", np); 548 549 /* Resource 1 is HV window */ 550 if (of_address_to_resource(np, 1, &r)) { 551 pr_err("Failed to get thread mgmnt area resource\n"); 552 return false; 553 } 554 tima = ioremap(r.start, resource_size(&r)); 555 if (!tima) { 556 pr_err("Failed to map thread mgmnt area\n"); 557 return false; 558 } 559 560 /* Read number of priorities */ 561 if (of_property_read_u32(np, "ibm,xive-#priorities", &val) == 0) 562 max_prio = val - 1; 563 564 /* Iterate the EQ sizes and pick one */ 565 of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) { 566 xive_queue_shift = val; 567 if (val == PAGE_SHIFT) 568 break; 569 } 570 571 /* Do we support single escalation */ 572 if (of_get_property(np, "single-escalation-support", NULL) != NULL) 573 xive_has_single_esc = true; 574 575 /* Configure Thread Management areas for KVM */ 576 for_each_possible_cpu(cpu) 577 kvmppc_set_xive_tima(cpu, r.start, tima); 578 579 /* Grab size of provisionning pages */ 580 xive_parse_provisioning(np); 581 582 /* Switch the XIVE to exploitation mode */ 583 rc = opal_xive_reset(OPAL_XIVE_MODE_EXPL); 584 if (rc) { 585 pr_err("Switch to exploitation mode failed with error %lld\n", rc); 586 return false; 587 } 588 589 /* Setup some dummy HV pool VPs */ 590 xive_native_setup_pools(); 591 592 /* Initialize XIVE core with our backend */ 593 if (!xive_core_init(&xive_native_ops, tima, TM_QW3_HV_PHYS, 594 max_prio)) { 595 opal_xive_reset(OPAL_XIVE_MODE_EMU); 596 return false; 597 } 598 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10)); 599 return true; 600 } 601 602 static bool xive_native_provision_pages(void) 603 { 604 u32 i; 605 void *p; 606 607 for (i = 0; i < xive_provision_chip_count; i++) { 608 u32 chip = xive_provision_chips[i]; 609 610 /* 611 * XXX TODO: Try to make the allocation local to the node where 612 * the chip resides. 613 */ 614 p = kmem_cache_alloc(xive_provision_cache, GFP_KERNEL); 615 if (!p) { 616 pr_err("Failed to allocate provisioning page\n"); 617 return false; 618 } 619 opal_xive_donate_page(chip, __pa(p)); 620 } 621 return true; 622 } 623 624 u32 xive_native_alloc_vp_block(u32 max_vcpus) 625 { 626 s64 rc; 627 u32 order; 628 629 order = fls(max_vcpus) - 1; 630 if (max_vcpus > (1 << order)) 631 order++; 632 633 pr_debug("VP block alloc, for max VCPUs %d use order %d\n", 634 max_vcpus, order); 635 636 for (;;) { 637 rc = opal_xive_alloc_vp_block(order); 638 switch (rc) { 639 case OPAL_BUSY: 640 msleep(OPAL_BUSY_DELAY_MS); 641 break; 642 case OPAL_XIVE_PROVISIONING: 643 if (!xive_native_provision_pages()) 644 return XIVE_INVALID_VP; 645 break; 646 default: 647 if (rc < 0) { 648 pr_err("OPAL failed to allocate VCPUs order %d, err %lld\n", 649 order, rc); 650 return XIVE_INVALID_VP; 651 } 652 return rc; 653 } 654 } 655 } 656 EXPORT_SYMBOL_GPL(xive_native_alloc_vp_block); 657 658 void xive_native_free_vp_block(u32 vp_base) 659 { 660 s64 rc; 661 662 if (vp_base == XIVE_INVALID_VP) 663 return; 664 665 rc = opal_xive_free_vp_block(vp_base); 666 if (rc < 0) 667 pr_warn("OPAL error %lld freeing VP block\n", rc); 668 } 669 EXPORT_SYMBOL_GPL(xive_native_free_vp_block); 670 671 int xive_native_enable_vp(u32 vp_id, bool single_escalation) 672 { 673 s64 rc; 674 u64 flags = OPAL_XIVE_VP_ENABLED; 675 676 if (single_escalation) 677 flags |= OPAL_XIVE_VP_SINGLE_ESCALATION; 678 for (;;) { 679 rc = opal_xive_set_vp_info(vp_id, flags, 0); 680 if (rc != OPAL_BUSY) 681 break; 682 msleep(OPAL_BUSY_DELAY_MS); 683 } 684 return rc ? -EIO : 0; 685 } 686 EXPORT_SYMBOL_GPL(xive_native_enable_vp); 687 688 int xive_native_disable_vp(u32 vp_id) 689 { 690 s64 rc; 691 692 for (;;) { 693 rc = opal_xive_set_vp_info(vp_id, 0, 0); 694 if (rc != OPAL_BUSY) 695 break; 696 msleep(OPAL_BUSY_DELAY_MS); 697 } 698 return rc ? -EIO : 0; 699 } 700 EXPORT_SYMBOL_GPL(xive_native_disable_vp); 701 702 int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id) 703 { 704 __be64 vp_cam_be; 705 __be32 vp_chip_id_be; 706 s64 rc; 707 708 rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be); 709 if (rc) 710 return -EIO; 711 *out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu; 712 *out_chip_id = be32_to_cpu(vp_chip_id_be); 713 714 return 0; 715 } 716 EXPORT_SYMBOL_GPL(xive_native_get_vp_info); 717 718 bool xive_native_has_single_escalation(void) 719 { 720 return xive_has_single_esc; 721 } 722 EXPORT_SYMBOL_GPL(xive_native_has_single_escalation); 723