1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2016,2017 IBM Corporation. 4 */ 5 6 #define pr_fmt(fmt) "xive: " fmt 7 8 #include <linux/types.h> 9 #include <linux/irq.h> 10 #include <linux/debugfs.h> 11 #include <linux/smp.h> 12 #include <linux/interrupt.h> 13 #include <linux/seq_file.h> 14 #include <linux/init.h> 15 #include <linux/of.h> 16 #include <linux/slab.h> 17 #include <linux/spinlock.h> 18 #include <linux/delay.h> 19 #include <linux/cpumask.h> 20 #include <linux/mm.h> 21 22 #include <asm/prom.h> 23 #include <asm/io.h> 24 #include <asm/smp.h> 25 #include <asm/irq.h> 26 #include <asm/errno.h> 27 #include <asm/xive.h> 28 #include <asm/xive-regs.h> 29 #include <asm/opal.h> 30 #include <asm/kvm_ppc.h> 31 32 #include "xive-internal.h" 33 34 35 static u32 xive_provision_size; 36 static u32 *xive_provision_chips; 37 static u32 xive_provision_chip_count; 38 static u32 xive_queue_shift; 39 static u32 xive_pool_vps = XIVE_INVALID_VP; 40 static struct kmem_cache *xive_provision_cache; 41 static bool xive_has_single_esc; 42 43 int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data) 44 { 45 __be64 flags, eoi_page, trig_page; 46 __be32 esb_shift, src_chip; 47 u64 opal_flags; 48 s64 rc; 49 50 memset(data, 0, sizeof(*data)); 51 52 rc = opal_xive_get_irq_info(hw_irq, &flags, &eoi_page, &trig_page, 53 &esb_shift, &src_chip); 54 if (rc) { 55 pr_err("opal_xive_get_irq_info(0x%x) returned %lld\n", 56 hw_irq, rc); 57 return -EINVAL; 58 } 59 60 opal_flags = be64_to_cpu(flags); 61 if (opal_flags & OPAL_XIVE_IRQ_STORE_EOI) 62 data->flags |= XIVE_IRQ_FLAG_STORE_EOI; 63 if (opal_flags & OPAL_XIVE_IRQ_LSI) 64 data->flags |= XIVE_IRQ_FLAG_LSI; 65 if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG) 66 data->flags |= XIVE_IRQ_FLAG_SHIFT_BUG; 67 if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW) 68 data->flags |= XIVE_IRQ_FLAG_MASK_FW; 69 if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW) 70 data->flags |= XIVE_IRQ_FLAG_EOI_FW; 71 data->eoi_page = be64_to_cpu(eoi_page); 72 data->trig_page = be64_to_cpu(trig_page); 73 data->esb_shift = be32_to_cpu(esb_shift); 74 data->src_chip = be32_to_cpu(src_chip); 75 76 data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift); 77 if (!data->eoi_mmio) { 78 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq); 79 return -ENOMEM; 80 } 81 82 data->hw_irq = hw_irq; 83 84 if (!data->trig_page) 85 return 0; 86 if (data->trig_page == data->eoi_page) { 87 data->trig_mmio = data->eoi_mmio; 88 return 0; 89 } 90 91 data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift); 92 if (!data->trig_mmio) { 93 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq); 94 return -ENOMEM; 95 } 96 return 0; 97 } 98 EXPORT_SYMBOL_GPL(xive_native_populate_irq_data); 99 100 int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) 101 { 102 s64 rc; 103 104 for (;;) { 105 rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq); 106 if (rc != OPAL_BUSY) 107 break; 108 msleep(OPAL_BUSY_DELAY_MS); 109 } 110 return rc == 0 ? 0 : -ENXIO; 111 } 112 EXPORT_SYMBOL_GPL(xive_native_configure_irq); 113 114 static int xive_native_get_irq_config(u32 hw_irq, u32 *target, u8 *prio, 115 u32 *sw_irq) 116 { 117 s64 rc; 118 __be64 vp; 119 __be32 lirq; 120 121 rc = opal_xive_get_irq_config(hw_irq, &vp, prio, &lirq); 122 123 *target = be64_to_cpu(vp); 124 *sw_irq = be32_to_cpu(lirq); 125 126 return rc == 0 ? 0 : -ENXIO; 127 } 128 129 /* This can be called multiple time to change a queue configuration */ 130 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, 131 __be32 *qpage, u32 order, bool can_escalate) 132 { 133 s64 rc = 0; 134 __be64 qeoi_page_be; 135 __be32 esc_irq_be; 136 u64 flags, qpage_phys; 137 138 /* If there's an actual queue page, clean it */ 139 if (order) { 140 if (WARN_ON(!qpage)) 141 return -EINVAL; 142 qpage_phys = __pa(qpage); 143 } else 144 qpage_phys = 0; 145 146 /* Initialize the rest of the fields */ 147 q->msk = order ? ((1u << (order - 2)) - 1) : 0; 148 q->idx = 0; 149 q->toggle = 0; 150 151 rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL, 152 &qeoi_page_be, 153 &esc_irq_be, 154 NULL); 155 if (rc) { 156 pr_err("Error %lld getting queue info prio %d\n", rc, prio); 157 rc = -EIO; 158 goto fail; 159 } 160 q->eoi_phys = be64_to_cpu(qeoi_page_be); 161 162 /* Default flags */ 163 flags = OPAL_XIVE_EQ_ALWAYS_NOTIFY | OPAL_XIVE_EQ_ENABLED; 164 165 /* Escalation needed ? */ 166 if (can_escalate) { 167 q->esc_irq = be32_to_cpu(esc_irq_be); 168 flags |= OPAL_XIVE_EQ_ESCALATE; 169 } 170 171 /* Configure and enable the queue in HW */ 172 for (;;) { 173 rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags); 174 if (rc != OPAL_BUSY) 175 break; 176 msleep(OPAL_BUSY_DELAY_MS); 177 } 178 if (rc) { 179 pr_err("Error %lld setting queue for prio %d\n", rc, prio); 180 rc = -EIO; 181 } else { 182 /* 183 * KVM code requires all of the above to be visible before 184 * q->qpage is set due to how it manages IPI EOIs 185 */ 186 wmb(); 187 q->qpage = qpage; 188 } 189 fail: 190 return rc; 191 } 192 EXPORT_SYMBOL_GPL(xive_native_configure_queue); 193 194 static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) 195 { 196 s64 rc; 197 198 /* Disable the queue in HW */ 199 for (;;) { 200 rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0); 201 if (rc != OPAL_BUSY) 202 break; 203 msleep(OPAL_BUSY_DELAY_MS); 204 } 205 if (rc) 206 pr_err("Error %lld disabling queue for prio %d\n", rc, prio); 207 } 208 209 void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) 210 { 211 __xive_native_disable_queue(vp_id, q, prio); 212 } 213 EXPORT_SYMBOL_GPL(xive_native_disable_queue); 214 215 static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio) 216 { 217 struct xive_q *q = &xc->queue[prio]; 218 __be32 *qpage; 219 220 qpage = xive_queue_page_alloc(cpu, xive_queue_shift); 221 if (IS_ERR(qpage)) 222 return PTR_ERR(qpage); 223 224 return xive_native_configure_queue(get_hard_smp_processor_id(cpu), 225 q, prio, qpage, xive_queue_shift, false); 226 } 227 228 static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio) 229 { 230 struct xive_q *q = &xc->queue[prio]; 231 unsigned int alloc_order; 232 233 /* 234 * We use the variant with no iounmap as this is called on exec 235 * from an IPI and iounmap isn't safe 236 */ 237 __xive_native_disable_queue(get_hard_smp_processor_id(cpu), q, prio); 238 alloc_order = xive_alloc_order(xive_queue_shift); 239 free_pages((unsigned long)q->qpage, alloc_order); 240 q->qpage = NULL; 241 } 242 243 static bool xive_native_match(struct device_node *node) 244 { 245 return of_device_is_compatible(node, "ibm,opal-xive-vc"); 246 } 247 248 static s64 opal_xive_allocate_irq(u32 chip_id) 249 { 250 s64 irq = opal_xive_allocate_irq_raw(chip_id); 251 252 /* 253 * Old versions of skiboot can incorrectly return 0xffffffff to 254 * indicate no space, fix it up here. 255 */ 256 return irq == 0xffffffff ? OPAL_RESOURCE : irq; 257 } 258 259 #ifdef CONFIG_SMP 260 static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc) 261 { 262 s64 irq; 263 264 /* Allocate an IPI and populate info about it */ 265 for (;;) { 266 irq = opal_xive_allocate_irq(xc->chip_id); 267 if (irq == OPAL_BUSY) { 268 msleep(OPAL_BUSY_DELAY_MS); 269 continue; 270 } 271 if (irq < 0) { 272 pr_err("Failed to allocate IPI on CPU %d\n", cpu); 273 return -ENXIO; 274 } 275 xc->hw_ipi = irq; 276 break; 277 } 278 return 0; 279 } 280 #endif /* CONFIG_SMP */ 281 282 u32 xive_native_alloc_irq(void) 283 { 284 s64 rc; 285 286 for (;;) { 287 rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP); 288 if (rc != OPAL_BUSY) 289 break; 290 msleep(OPAL_BUSY_DELAY_MS); 291 } 292 if (rc < 0) 293 return 0; 294 return rc; 295 } 296 EXPORT_SYMBOL_GPL(xive_native_alloc_irq); 297 298 void xive_native_free_irq(u32 irq) 299 { 300 for (;;) { 301 s64 rc = opal_xive_free_irq(irq); 302 if (rc != OPAL_BUSY) 303 break; 304 msleep(OPAL_BUSY_DELAY_MS); 305 } 306 } 307 EXPORT_SYMBOL_GPL(xive_native_free_irq); 308 309 #ifdef CONFIG_SMP 310 static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc) 311 { 312 s64 rc; 313 314 /* Free the IPI */ 315 if (!xc->hw_ipi) 316 return; 317 for (;;) { 318 rc = opal_xive_free_irq(xc->hw_ipi); 319 if (rc == OPAL_BUSY) { 320 msleep(OPAL_BUSY_DELAY_MS); 321 continue; 322 } 323 xc->hw_ipi = 0; 324 break; 325 } 326 } 327 #endif /* CONFIG_SMP */ 328 329 static void xive_native_shutdown(void) 330 { 331 /* Switch the XIVE to emulation mode */ 332 opal_xive_reset(OPAL_XIVE_MODE_EMU); 333 } 334 335 /* 336 * Perform an "ack" cycle on the current thread, thus 337 * grabbing the pending active priorities and updating 338 * the CPPR to the most favored one. 339 */ 340 static void xive_native_update_pending(struct xive_cpu *xc) 341 { 342 u8 he, cppr; 343 u16 ack; 344 345 /* Perform the acknowledge hypervisor to register cycle */ 346 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_HV_REG)); 347 348 /* Synchronize subsequent queue accesses */ 349 mb(); 350 351 /* 352 * Grab the CPPR and the "HE" field which indicates the source 353 * of the hypervisor interrupt (if any) 354 */ 355 cppr = ack & 0xff; 356 he = (ack >> 8) >> 6; 357 switch(he) { 358 case TM_QW3_NSR_HE_NONE: /* Nothing to see here */ 359 break; 360 case TM_QW3_NSR_HE_PHYS: /* Physical thread interrupt */ 361 if (cppr == 0xff) 362 return; 363 /* Mark the priority pending */ 364 xc->pending_prio |= 1 << cppr; 365 366 /* 367 * A new interrupt should never have a CPPR less favored 368 * than our current one. 369 */ 370 if (cppr >= xc->cppr) 371 pr_err("CPU %d odd ack CPPR, got %d at %d\n", 372 smp_processor_id(), cppr, xc->cppr); 373 374 /* Update our idea of what the CPPR is */ 375 xc->cppr = cppr; 376 break; 377 case TM_QW3_NSR_HE_POOL: /* HV Pool interrupt (unused) */ 378 case TM_QW3_NSR_HE_LSI: /* Legacy FW LSI (unused) */ 379 pr_err("CPU %d got unexpected interrupt type HE=%d\n", 380 smp_processor_id(), he); 381 return; 382 } 383 } 384 385 static void xive_native_eoi(u32 hw_irq) 386 { 387 /* 388 * Not normally used except if specific interrupts need 389 * a workaround on EOI. 390 */ 391 opal_int_eoi(hw_irq); 392 } 393 394 static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc) 395 { 396 s64 rc; 397 u32 vp; 398 __be64 vp_cam_be; 399 u64 vp_cam; 400 401 if (xive_pool_vps == XIVE_INVALID_VP) 402 return; 403 404 /* Check if pool VP already active, if it is, pull it */ 405 if (in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2) & TM_QW2W2_VP) 406 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX); 407 408 /* Enable the pool VP */ 409 vp = xive_pool_vps + cpu; 410 for (;;) { 411 rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0); 412 if (rc != OPAL_BUSY) 413 break; 414 msleep(OPAL_BUSY_DELAY_MS); 415 } 416 if (rc) { 417 pr_err("Failed to enable pool VP on CPU %d\n", cpu); 418 return; 419 } 420 421 /* Grab it's CAM value */ 422 rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL); 423 if (rc) { 424 pr_err("Failed to get pool VP info CPU %d\n", cpu); 425 return; 426 } 427 vp_cam = be64_to_cpu(vp_cam_be); 428 429 /* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */ 430 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff); 431 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2, TM_QW2W2_VP | vp_cam); 432 } 433 434 static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc) 435 { 436 s64 rc; 437 u32 vp; 438 439 if (xive_pool_vps == XIVE_INVALID_VP) 440 return; 441 442 /* Pull the pool VP from the CPU */ 443 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX); 444 445 /* Disable it */ 446 vp = xive_pool_vps + cpu; 447 for (;;) { 448 rc = opal_xive_set_vp_info(vp, 0, 0); 449 if (rc != OPAL_BUSY) 450 break; 451 msleep(OPAL_BUSY_DELAY_MS); 452 } 453 } 454 455 void xive_native_sync_source(u32 hw_irq) 456 { 457 opal_xive_sync(XIVE_SYNC_EAS, hw_irq); 458 } 459 EXPORT_SYMBOL_GPL(xive_native_sync_source); 460 461 void xive_native_sync_queue(u32 hw_irq) 462 { 463 opal_xive_sync(XIVE_SYNC_QUEUE, hw_irq); 464 } 465 EXPORT_SYMBOL_GPL(xive_native_sync_queue); 466 467 static const struct xive_ops xive_native_ops = { 468 .populate_irq_data = xive_native_populate_irq_data, 469 .configure_irq = xive_native_configure_irq, 470 .get_irq_config = xive_native_get_irq_config, 471 .setup_queue = xive_native_setup_queue, 472 .cleanup_queue = xive_native_cleanup_queue, 473 .match = xive_native_match, 474 .shutdown = xive_native_shutdown, 475 .update_pending = xive_native_update_pending, 476 .eoi = xive_native_eoi, 477 .setup_cpu = xive_native_setup_cpu, 478 .teardown_cpu = xive_native_teardown_cpu, 479 .sync_source = xive_native_sync_source, 480 #ifdef CONFIG_SMP 481 .get_ipi = xive_native_get_ipi, 482 .put_ipi = xive_native_put_ipi, 483 #endif /* CONFIG_SMP */ 484 .name = "native", 485 }; 486 487 static bool xive_parse_provisioning(struct device_node *np) 488 { 489 int rc; 490 491 if (of_property_read_u32(np, "ibm,xive-provision-page-size", 492 &xive_provision_size) < 0) 493 return true; 494 rc = of_property_count_elems_of_size(np, "ibm,xive-provision-chips", 4); 495 if (rc < 0) { 496 pr_err("Error %d getting provision chips array\n", rc); 497 return false; 498 } 499 xive_provision_chip_count = rc; 500 if (rc == 0) 501 return true; 502 503 xive_provision_chips = kcalloc(4, xive_provision_chip_count, 504 GFP_KERNEL); 505 if (WARN_ON(!xive_provision_chips)) 506 return false; 507 508 rc = of_property_read_u32_array(np, "ibm,xive-provision-chips", 509 xive_provision_chips, 510 xive_provision_chip_count); 511 if (rc < 0) { 512 pr_err("Error %d reading provision chips array\n", rc); 513 return false; 514 } 515 516 xive_provision_cache = kmem_cache_create("xive-provision", 517 xive_provision_size, 518 xive_provision_size, 519 0, NULL); 520 if (!xive_provision_cache) { 521 pr_err("Failed to allocate provision cache\n"); 522 return false; 523 } 524 return true; 525 } 526 527 static void xive_native_setup_pools(void) 528 { 529 /* Allocate a pool big enough */ 530 pr_debug("XIVE: Allocating VP block for pool size %u\n", nr_cpu_ids); 531 532 xive_pool_vps = xive_native_alloc_vp_block(nr_cpu_ids); 533 if (WARN_ON(xive_pool_vps == XIVE_INVALID_VP)) 534 pr_err("XIVE: Failed to allocate pool VP, KVM might not function\n"); 535 536 pr_debug("XIVE: Pool VPs allocated at 0x%x for %u max CPUs\n", 537 xive_pool_vps, nr_cpu_ids); 538 } 539 540 u32 xive_native_default_eq_shift(void) 541 { 542 return xive_queue_shift; 543 } 544 EXPORT_SYMBOL_GPL(xive_native_default_eq_shift); 545 546 unsigned long xive_tima_os; 547 EXPORT_SYMBOL_GPL(xive_tima_os); 548 549 bool __init xive_native_init(void) 550 { 551 struct device_node *np; 552 struct resource r; 553 void __iomem *tima; 554 struct property *prop; 555 u8 max_prio = 7; 556 const __be32 *p; 557 u32 val, cpu; 558 s64 rc; 559 560 if (xive_cmdline_disabled) 561 return false; 562 563 pr_devel("xive_native_init()\n"); 564 np = of_find_compatible_node(NULL, NULL, "ibm,opal-xive-pe"); 565 if (!np) { 566 pr_devel("not found !\n"); 567 return false; 568 } 569 pr_devel("Found %pOF\n", np); 570 571 /* Resource 1 is HV window */ 572 if (of_address_to_resource(np, 1, &r)) { 573 pr_err("Failed to get thread mgmnt area resource\n"); 574 return false; 575 } 576 tima = ioremap(r.start, resource_size(&r)); 577 if (!tima) { 578 pr_err("Failed to map thread mgmnt area\n"); 579 return false; 580 } 581 582 /* Read number of priorities */ 583 if (of_property_read_u32(np, "ibm,xive-#priorities", &val) == 0) 584 max_prio = val - 1; 585 586 /* Iterate the EQ sizes and pick one */ 587 of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) { 588 xive_queue_shift = val; 589 if (val == PAGE_SHIFT) 590 break; 591 } 592 593 /* Do we support single escalation */ 594 if (of_get_property(np, "single-escalation-support", NULL) != NULL) 595 xive_has_single_esc = true; 596 597 /* Configure Thread Management areas for KVM */ 598 for_each_possible_cpu(cpu) 599 kvmppc_set_xive_tima(cpu, r.start, tima); 600 601 /* Resource 2 is OS window */ 602 if (of_address_to_resource(np, 2, &r)) { 603 pr_err("Failed to get thread mgmnt area resource\n"); 604 return false; 605 } 606 607 xive_tima_os = r.start; 608 609 /* Grab size of provisionning pages */ 610 xive_parse_provisioning(np); 611 612 /* Switch the XIVE to exploitation mode */ 613 rc = opal_xive_reset(OPAL_XIVE_MODE_EXPL); 614 if (rc) { 615 pr_err("Switch to exploitation mode failed with error %lld\n", rc); 616 return false; 617 } 618 619 /* Setup some dummy HV pool VPs */ 620 xive_native_setup_pools(); 621 622 /* Initialize XIVE core with our backend */ 623 if (!xive_core_init(&xive_native_ops, tima, TM_QW3_HV_PHYS, 624 max_prio)) { 625 opal_xive_reset(OPAL_XIVE_MODE_EMU); 626 return false; 627 } 628 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10)); 629 return true; 630 } 631 632 static bool xive_native_provision_pages(void) 633 { 634 u32 i; 635 void *p; 636 637 for (i = 0; i < xive_provision_chip_count; i++) { 638 u32 chip = xive_provision_chips[i]; 639 640 /* 641 * XXX TODO: Try to make the allocation local to the node where 642 * the chip resides. 643 */ 644 p = kmem_cache_alloc(xive_provision_cache, GFP_KERNEL); 645 if (!p) { 646 pr_err("Failed to allocate provisioning page\n"); 647 return false; 648 } 649 opal_xive_donate_page(chip, __pa(p)); 650 } 651 return true; 652 } 653 654 u32 xive_native_alloc_vp_block(u32 max_vcpus) 655 { 656 s64 rc; 657 u32 order; 658 659 order = fls(max_vcpus) - 1; 660 if (max_vcpus > (1 << order)) 661 order++; 662 663 pr_debug("VP block alloc, for max VCPUs %d use order %d\n", 664 max_vcpus, order); 665 666 for (;;) { 667 rc = opal_xive_alloc_vp_block(order); 668 switch (rc) { 669 case OPAL_BUSY: 670 msleep(OPAL_BUSY_DELAY_MS); 671 break; 672 case OPAL_XIVE_PROVISIONING: 673 if (!xive_native_provision_pages()) 674 return XIVE_INVALID_VP; 675 break; 676 default: 677 if (rc < 0) { 678 pr_err("OPAL failed to allocate VCPUs order %d, err %lld\n", 679 order, rc); 680 return XIVE_INVALID_VP; 681 } 682 return rc; 683 } 684 } 685 } 686 EXPORT_SYMBOL_GPL(xive_native_alloc_vp_block); 687 688 void xive_native_free_vp_block(u32 vp_base) 689 { 690 s64 rc; 691 692 if (vp_base == XIVE_INVALID_VP) 693 return; 694 695 rc = opal_xive_free_vp_block(vp_base); 696 if (rc < 0) 697 pr_warn("OPAL error %lld freeing VP block\n", rc); 698 } 699 EXPORT_SYMBOL_GPL(xive_native_free_vp_block); 700 701 int xive_native_enable_vp(u32 vp_id, bool single_escalation) 702 { 703 s64 rc; 704 u64 flags = OPAL_XIVE_VP_ENABLED; 705 706 if (single_escalation) 707 flags |= OPAL_XIVE_VP_SINGLE_ESCALATION; 708 for (;;) { 709 rc = opal_xive_set_vp_info(vp_id, flags, 0); 710 if (rc != OPAL_BUSY) 711 break; 712 msleep(OPAL_BUSY_DELAY_MS); 713 } 714 return rc ? -EIO : 0; 715 } 716 EXPORT_SYMBOL_GPL(xive_native_enable_vp); 717 718 int xive_native_disable_vp(u32 vp_id) 719 { 720 s64 rc; 721 722 for (;;) { 723 rc = opal_xive_set_vp_info(vp_id, 0, 0); 724 if (rc != OPAL_BUSY) 725 break; 726 msleep(OPAL_BUSY_DELAY_MS); 727 } 728 return rc ? -EIO : 0; 729 } 730 EXPORT_SYMBOL_GPL(xive_native_disable_vp); 731 732 int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id) 733 { 734 __be64 vp_cam_be; 735 __be32 vp_chip_id_be; 736 s64 rc; 737 738 rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be); 739 if (rc) 740 return -EIO; 741 *out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu; 742 *out_chip_id = be32_to_cpu(vp_chip_id_be); 743 744 return 0; 745 } 746 EXPORT_SYMBOL_GPL(xive_native_get_vp_info); 747 748 bool xive_native_has_single_escalation(void) 749 { 750 return xive_has_single_esc; 751 } 752 EXPORT_SYMBOL_GPL(xive_native_has_single_escalation); 753 754 int xive_native_get_queue_info(u32 vp_id, u32 prio, 755 u64 *out_qpage, 756 u64 *out_qsize, 757 u64 *out_qeoi_page, 758 u32 *out_escalate_irq, 759 u64 *out_qflags) 760 { 761 __be64 qpage; 762 __be64 qsize; 763 __be64 qeoi_page; 764 __be32 escalate_irq; 765 __be64 qflags; 766 s64 rc; 767 768 rc = opal_xive_get_queue_info(vp_id, prio, &qpage, &qsize, 769 &qeoi_page, &escalate_irq, &qflags); 770 if (rc) { 771 pr_err("OPAL failed to get queue info for VCPU %d/%d : %lld\n", 772 vp_id, prio, rc); 773 return -EIO; 774 } 775 776 if (out_qpage) 777 *out_qpage = be64_to_cpu(qpage); 778 if (out_qsize) 779 *out_qsize = be32_to_cpu(qsize); 780 if (out_qeoi_page) 781 *out_qeoi_page = be64_to_cpu(qeoi_page); 782 if (out_escalate_irq) 783 *out_escalate_irq = be32_to_cpu(escalate_irq); 784 if (out_qflags) 785 *out_qflags = be64_to_cpu(qflags); 786 787 return 0; 788 } 789 EXPORT_SYMBOL_GPL(xive_native_get_queue_info); 790 791 int xive_native_get_queue_state(u32 vp_id, u32 prio, u32 *qtoggle, u32 *qindex) 792 { 793 __be32 opal_qtoggle; 794 __be32 opal_qindex; 795 s64 rc; 796 797 rc = opal_xive_get_queue_state(vp_id, prio, &opal_qtoggle, 798 &opal_qindex); 799 if (rc) { 800 pr_err("OPAL failed to get queue state for VCPU %d/%d : %lld\n", 801 vp_id, prio, rc); 802 return -EIO; 803 } 804 805 if (qtoggle) 806 *qtoggle = be32_to_cpu(opal_qtoggle); 807 if (qindex) 808 *qindex = be32_to_cpu(opal_qindex); 809 810 return 0; 811 } 812 EXPORT_SYMBOL_GPL(xive_native_get_queue_state); 813 814 int xive_native_set_queue_state(u32 vp_id, u32 prio, u32 qtoggle, u32 qindex) 815 { 816 s64 rc; 817 818 rc = opal_xive_set_queue_state(vp_id, prio, qtoggle, qindex); 819 if (rc) { 820 pr_err("OPAL failed to set queue state for VCPU %d/%d : %lld\n", 821 vp_id, prio, rc); 822 return -EIO; 823 } 824 825 return 0; 826 } 827 EXPORT_SYMBOL_GPL(xive_native_set_queue_state); 828 829 bool xive_native_has_queue_state_support(void) 830 { 831 return opal_check_token(OPAL_XIVE_GET_QUEUE_STATE) && 832 opal_check_token(OPAL_XIVE_SET_QUEUE_STATE); 833 } 834 EXPORT_SYMBOL_GPL(xive_native_has_queue_state_support); 835 836 int xive_native_get_vp_state(u32 vp_id, u64 *out_state) 837 { 838 __be64 state; 839 s64 rc; 840 841 rc = opal_xive_get_vp_state(vp_id, &state); 842 if (rc) { 843 pr_err("OPAL failed to get vp state for VCPU %d : %lld\n", 844 vp_id, rc); 845 return -EIO; 846 } 847 848 if (out_state) 849 *out_state = be64_to_cpu(state); 850 return 0; 851 } 852 EXPORT_SYMBOL_GPL(xive_native_get_vp_state); 853