1 /* 2 * Copyright 2016,2017 IBM Corporation. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #define pr_fmt(fmt) "xive: " fmt 11 12 #include <linux/types.h> 13 #include <linux/irq.h> 14 #include <linux/debugfs.h> 15 #include <linux/smp.h> 16 #include <linux/interrupt.h> 17 #include <linux/seq_file.h> 18 #include <linux/init.h> 19 #include <linux/of.h> 20 #include <linux/slab.h> 21 #include <linux/spinlock.h> 22 #include <linux/delay.h> 23 #include <linux/cpumask.h> 24 #include <linux/mm.h> 25 26 #include <asm/prom.h> 27 #include <asm/io.h> 28 #include <asm/smp.h> 29 #include <asm/irq.h> 30 #include <asm/errno.h> 31 #include <asm/xive.h> 32 #include <asm/xive-regs.h> 33 #include <asm/opal.h> 34 #include <asm/kvm_ppc.h> 35 36 #include "xive-internal.h" 37 38 39 static u32 xive_provision_size; 40 static u32 *xive_provision_chips; 41 static u32 xive_provision_chip_count; 42 static u32 xive_queue_shift; 43 static u32 xive_pool_vps = XIVE_INVALID_VP; 44 static struct kmem_cache *xive_provision_cache; 45 static bool xive_has_single_esc; 46 47 int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data) 48 { 49 __be64 flags, eoi_page, trig_page; 50 __be32 esb_shift, src_chip; 51 u64 opal_flags; 52 s64 rc; 53 54 memset(data, 0, sizeof(*data)); 55 56 rc = opal_xive_get_irq_info(hw_irq, &flags, &eoi_page, &trig_page, 57 &esb_shift, &src_chip); 58 if (rc) { 59 pr_err("opal_xive_get_irq_info(0x%x) returned %lld\n", 60 hw_irq, rc); 61 return -EINVAL; 62 } 63 64 opal_flags = be64_to_cpu(flags); 65 if (opal_flags & OPAL_XIVE_IRQ_STORE_EOI) 66 data->flags |= XIVE_IRQ_FLAG_STORE_EOI; 67 if (opal_flags & OPAL_XIVE_IRQ_LSI) 68 data->flags |= XIVE_IRQ_FLAG_LSI; 69 if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG) 70 data->flags |= XIVE_IRQ_FLAG_SHIFT_BUG; 71 if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW) 72 data->flags |= XIVE_IRQ_FLAG_MASK_FW; 73 if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW) 74 data->flags |= XIVE_IRQ_FLAG_EOI_FW; 75 data->eoi_page = be64_to_cpu(eoi_page); 76 data->trig_page = be64_to_cpu(trig_page); 77 data->esb_shift = be32_to_cpu(esb_shift); 78 data->src_chip = be32_to_cpu(src_chip); 79 80 data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift); 81 if (!data->eoi_mmio) { 82 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq); 83 return -ENOMEM; 84 } 85 86 data->hw_irq = hw_irq; 87 88 if (!data->trig_page) 89 return 0; 90 if (data->trig_page == data->eoi_page) { 91 data->trig_mmio = data->eoi_mmio; 92 return 0; 93 } 94 95 data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift); 96 if (!data->trig_mmio) { 97 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq); 98 return -ENOMEM; 99 } 100 return 0; 101 } 102 EXPORT_SYMBOL_GPL(xive_native_populate_irq_data); 103 104 int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) 105 { 106 s64 rc; 107 108 for (;;) { 109 rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq); 110 if (rc != OPAL_BUSY) 111 break; 112 msleep(OPAL_BUSY_DELAY_MS); 113 } 114 return rc == 0 ? 0 : -ENXIO; 115 } 116 EXPORT_SYMBOL_GPL(xive_native_configure_irq); 117 118 119 /* This can be called multiple time to change a queue configuration */ 120 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, 121 __be32 *qpage, u32 order, bool can_escalate) 122 { 123 s64 rc = 0; 124 __be64 qeoi_page_be; 125 __be32 esc_irq_be; 126 u64 flags, qpage_phys; 127 128 /* If there's an actual queue page, clean it */ 129 if (order) { 130 if (WARN_ON(!qpage)) 131 return -EINVAL; 132 qpage_phys = __pa(qpage); 133 } else 134 qpage_phys = 0; 135 136 /* Initialize the rest of the fields */ 137 q->msk = order ? ((1u << (order - 2)) - 1) : 0; 138 q->idx = 0; 139 q->toggle = 0; 140 141 rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL, 142 &qeoi_page_be, 143 &esc_irq_be, 144 NULL); 145 if (rc) { 146 pr_err("Error %lld getting queue info prio %d\n", rc, prio); 147 rc = -EIO; 148 goto fail; 149 } 150 q->eoi_phys = be64_to_cpu(qeoi_page_be); 151 152 /* Default flags */ 153 flags = OPAL_XIVE_EQ_ALWAYS_NOTIFY | OPAL_XIVE_EQ_ENABLED; 154 155 /* Escalation needed ? */ 156 if (can_escalate) { 157 q->esc_irq = be32_to_cpu(esc_irq_be); 158 flags |= OPAL_XIVE_EQ_ESCALATE; 159 } 160 161 /* Configure and enable the queue in HW */ 162 for (;;) { 163 rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags); 164 if (rc != OPAL_BUSY) 165 break; 166 msleep(OPAL_BUSY_DELAY_MS); 167 } 168 if (rc) { 169 pr_err("Error %lld setting queue for prio %d\n", rc, prio); 170 rc = -EIO; 171 } else { 172 /* 173 * KVM code requires all of the above to be visible before 174 * q->qpage is set due to how it manages IPI EOIs 175 */ 176 wmb(); 177 q->qpage = qpage; 178 } 179 fail: 180 return rc; 181 } 182 EXPORT_SYMBOL_GPL(xive_native_configure_queue); 183 184 static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) 185 { 186 s64 rc; 187 188 /* Disable the queue in HW */ 189 for (;;) { 190 rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0); 191 if (rc != OPAL_BUSY) 192 break; 193 msleep(OPAL_BUSY_DELAY_MS); 194 } 195 if (rc) 196 pr_err("Error %lld disabling queue for prio %d\n", rc, prio); 197 } 198 199 void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) 200 { 201 __xive_native_disable_queue(vp_id, q, prio); 202 } 203 EXPORT_SYMBOL_GPL(xive_native_disable_queue); 204 205 static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio) 206 { 207 struct xive_q *q = &xc->queue[prio]; 208 __be32 *qpage; 209 210 qpage = xive_queue_page_alloc(cpu, xive_queue_shift); 211 if (IS_ERR(qpage)) 212 return PTR_ERR(qpage); 213 214 return xive_native_configure_queue(get_hard_smp_processor_id(cpu), 215 q, prio, qpage, xive_queue_shift, false); 216 } 217 218 static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio) 219 { 220 struct xive_q *q = &xc->queue[prio]; 221 unsigned int alloc_order; 222 223 /* 224 * We use the variant with no iounmap as this is called on exec 225 * from an IPI and iounmap isn't safe 226 */ 227 __xive_native_disable_queue(get_hard_smp_processor_id(cpu), q, prio); 228 alloc_order = xive_alloc_order(xive_queue_shift); 229 free_pages((unsigned long)q->qpage, alloc_order); 230 q->qpage = NULL; 231 } 232 233 static bool xive_native_match(struct device_node *node) 234 { 235 return of_device_is_compatible(node, "ibm,opal-xive-vc"); 236 } 237 238 #ifdef CONFIG_SMP 239 static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc) 240 { 241 s64 irq; 242 243 /* Allocate an IPI and populate info about it */ 244 for (;;) { 245 irq = opal_xive_allocate_irq(xc->chip_id); 246 if (irq == OPAL_BUSY) { 247 msleep(OPAL_BUSY_DELAY_MS); 248 continue; 249 } 250 if (irq < 0) { 251 pr_err("Failed to allocate IPI on CPU %d\n", cpu); 252 return -ENXIO; 253 } 254 xc->hw_ipi = irq; 255 break; 256 } 257 return 0; 258 } 259 #endif /* CONFIG_SMP */ 260 261 u32 xive_native_alloc_irq(void) 262 { 263 s64 rc; 264 265 for (;;) { 266 rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP); 267 if (rc != OPAL_BUSY) 268 break; 269 msleep(OPAL_BUSY_DELAY_MS); 270 } 271 if (rc < 0) 272 return 0; 273 return rc; 274 } 275 EXPORT_SYMBOL_GPL(xive_native_alloc_irq); 276 277 void xive_native_free_irq(u32 irq) 278 { 279 for (;;) { 280 s64 rc = opal_xive_free_irq(irq); 281 if (rc != OPAL_BUSY) 282 break; 283 msleep(OPAL_BUSY_DELAY_MS); 284 } 285 } 286 EXPORT_SYMBOL_GPL(xive_native_free_irq); 287 288 #ifdef CONFIG_SMP 289 static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc) 290 { 291 s64 rc; 292 293 /* Free the IPI */ 294 if (!xc->hw_ipi) 295 return; 296 for (;;) { 297 rc = opal_xive_free_irq(xc->hw_ipi); 298 if (rc == OPAL_BUSY) { 299 msleep(OPAL_BUSY_DELAY_MS); 300 continue; 301 } 302 xc->hw_ipi = 0; 303 break; 304 } 305 } 306 #endif /* CONFIG_SMP */ 307 308 static void xive_native_shutdown(void) 309 { 310 /* Switch the XIVE to emulation mode */ 311 opal_xive_reset(OPAL_XIVE_MODE_EMU); 312 } 313 314 /* 315 * Perform an "ack" cycle on the current thread, thus 316 * grabbing the pending active priorities and updating 317 * the CPPR to the most favored one. 318 */ 319 static void xive_native_update_pending(struct xive_cpu *xc) 320 { 321 u8 he, cppr; 322 u16 ack; 323 324 /* Perform the acknowledge hypervisor to register cycle */ 325 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_HV_REG)); 326 327 /* Synchronize subsequent queue accesses */ 328 mb(); 329 330 /* 331 * Grab the CPPR and the "HE" field which indicates the source 332 * of the hypervisor interrupt (if any) 333 */ 334 cppr = ack & 0xff; 335 he = (ack >> 8) >> 6; 336 switch(he) { 337 case TM_QW3_NSR_HE_NONE: /* Nothing to see here */ 338 break; 339 case TM_QW3_NSR_HE_PHYS: /* Physical thread interrupt */ 340 if (cppr == 0xff) 341 return; 342 /* Mark the priority pending */ 343 xc->pending_prio |= 1 << cppr; 344 345 /* 346 * A new interrupt should never have a CPPR less favored 347 * than our current one. 348 */ 349 if (cppr >= xc->cppr) 350 pr_err("CPU %d odd ack CPPR, got %d at %d\n", 351 smp_processor_id(), cppr, xc->cppr); 352 353 /* Update our idea of what the CPPR is */ 354 xc->cppr = cppr; 355 break; 356 case TM_QW3_NSR_HE_POOL: /* HV Pool interrupt (unused) */ 357 case TM_QW3_NSR_HE_LSI: /* Legacy FW LSI (unused) */ 358 pr_err("CPU %d got unexpected interrupt type HE=%d\n", 359 smp_processor_id(), he); 360 return; 361 } 362 } 363 364 static void xive_native_eoi(u32 hw_irq) 365 { 366 /* 367 * Not normally used except if specific interrupts need 368 * a workaround on EOI. 369 */ 370 opal_int_eoi(hw_irq); 371 } 372 373 static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc) 374 { 375 s64 rc; 376 u32 vp; 377 __be64 vp_cam_be; 378 u64 vp_cam; 379 380 if (xive_pool_vps == XIVE_INVALID_VP) 381 return; 382 383 /* Check if pool VP already active, if it is, pull it */ 384 if (in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2) & TM_QW2W2_VP) 385 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX); 386 387 /* Enable the pool VP */ 388 vp = xive_pool_vps + cpu; 389 for (;;) { 390 rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0); 391 if (rc != OPAL_BUSY) 392 break; 393 msleep(OPAL_BUSY_DELAY_MS); 394 } 395 if (rc) { 396 pr_err("Failed to enable pool VP on CPU %d\n", cpu); 397 return; 398 } 399 400 /* Grab it's CAM value */ 401 rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL); 402 if (rc) { 403 pr_err("Failed to get pool VP info CPU %d\n", cpu); 404 return; 405 } 406 vp_cam = be64_to_cpu(vp_cam_be); 407 408 /* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */ 409 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff); 410 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2, TM_QW2W2_VP | vp_cam); 411 } 412 413 static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc) 414 { 415 s64 rc; 416 u32 vp; 417 418 if (xive_pool_vps == XIVE_INVALID_VP) 419 return; 420 421 /* Pull the pool VP from the CPU */ 422 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX); 423 424 /* Disable it */ 425 vp = xive_pool_vps + cpu; 426 for (;;) { 427 rc = opal_xive_set_vp_info(vp, 0, 0); 428 if (rc != OPAL_BUSY) 429 break; 430 msleep(OPAL_BUSY_DELAY_MS); 431 } 432 } 433 434 void xive_native_sync_source(u32 hw_irq) 435 { 436 opal_xive_sync(XIVE_SYNC_EAS, hw_irq); 437 } 438 EXPORT_SYMBOL_GPL(xive_native_sync_source); 439 440 static const struct xive_ops xive_native_ops = { 441 .populate_irq_data = xive_native_populate_irq_data, 442 .configure_irq = xive_native_configure_irq, 443 .setup_queue = xive_native_setup_queue, 444 .cleanup_queue = xive_native_cleanup_queue, 445 .match = xive_native_match, 446 .shutdown = xive_native_shutdown, 447 .update_pending = xive_native_update_pending, 448 .eoi = xive_native_eoi, 449 .setup_cpu = xive_native_setup_cpu, 450 .teardown_cpu = xive_native_teardown_cpu, 451 .sync_source = xive_native_sync_source, 452 #ifdef CONFIG_SMP 453 .get_ipi = xive_native_get_ipi, 454 .put_ipi = xive_native_put_ipi, 455 #endif /* CONFIG_SMP */ 456 .name = "native", 457 }; 458 459 static bool xive_parse_provisioning(struct device_node *np) 460 { 461 int rc; 462 463 if (of_property_read_u32(np, "ibm,xive-provision-page-size", 464 &xive_provision_size) < 0) 465 return true; 466 rc = of_property_count_elems_of_size(np, "ibm,xive-provision-chips", 4); 467 if (rc < 0) { 468 pr_err("Error %d getting provision chips array\n", rc); 469 return false; 470 } 471 xive_provision_chip_count = rc; 472 if (rc == 0) 473 return true; 474 475 xive_provision_chips = kcalloc(4, xive_provision_chip_count, 476 GFP_KERNEL); 477 if (WARN_ON(!xive_provision_chips)) 478 return false; 479 480 rc = of_property_read_u32_array(np, "ibm,xive-provision-chips", 481 xive_provision_chips, 482 xive_provision_chip_count); 483 if (rc < 0) { 484 pr_err("Error %d reading provision chips array\n", rc); 485 return false; 486 } 487 488 xive_provision_cache = kmem_cache_create("xive-provision", 489 xive_provision_size, 490 xive_provision_size, 491 0, NULL); 492 if (!xive_provision_cache) { 493 pr_err("Failed to allocate provision cache\n"); 494 return false; 495 } 496 return true; 497 } 498 499 static void xive_native_setup_pools(void) 500 { 501 /* Allocate a pool big enough */ 502 pr_debug("XIVE: Allocating VP block for pool size %u\n", nr_cpu_ids); 503 504 xive_pool_vps = xive_native_alloc_vp_block(nr_cpu_ids); 505 if (WARN_ON(xive_pool_vps == XIVE_INVALID_VP)) 506 pr_err("XIVE: Failed to allocate pool VP, KVM might not function\n"); 507 508 pr_debug("XIVE: Pool VPs allocated at 0x%x for %u max CPUs\n", 509 xive_pool_vps, nr_cpu_ids); 510 } 511 512 u32 xive_native_default_eq_shift(void) 513 { 514 return xive_queue_shift; 515 } 516 EXPORT_SYMBOL_GPL(xive_native_default_eq_shift); 517 518 bool __init xive_native_init(void) 519 { 520 struct device_node *np; 521 struct resource r; 522 void __iomem *tima; 523 struct property *prop; 524 u8 max_prio = 7; 525 const __be32 *p; 526 u32 val, cpu; 527 s64 rc; 528 529 if (xive_cmdline_disabled) 530 return false; 531 532 pr_devel("xive_native_init()\n"); 533 np = of_find_compatible_node(NULL, NULL, "ibm,opal-xive-pe"); 534 if (!np) { 535 pr_devel("not found !\n"); 536 return false; 537 } 538 pr_devel("Found %pOF\n", np); 539 540 /* Resource 1 is HV window */ 541 if (of_address_to_resource(np, 1, &r)) { 542 pr_err("Failed to get thread mgmnt area resource\n"); 543 return false; 544 } 545 tima = ioremap(r.start, resource_size(&r)); 546 if (!tima) { 547 pr_err("Failed to map thread mgmnt area\n"); 548 return false; 549 } 550 551 /* Read number of priorities */ 552 if (of_property_read_u32(np, "ibm,xive-#priorities", &val) == 0) 553 max_prio = val - 1; 554 555 /* Iterate the EQ sizes and pick one */ 556 of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) { 557 xive_queue_shift = val; 558 if (val == PAGE_SHIFT) 559 break; 560 } 561 562 /* Do we support single escalation */ 563 if (of_get_property(np, "single-escalation-support", NULL) != NULL) 564 xive_has_single_esc = true; 565 566 /* Configure Thread Management areas for KVM */ 567 for_each_possible_cpu(cpu) 568 kvmppc_set_xive_tima(cpu, r.start, tima); 569 570 /* Grab size of provisionning pages */ 571 xive_parse_provisioning(np); 572 573 /* Switch the XIVE to exploitation mode */ 574 rc = opal_xive_reset(OPAL_XIVE_MODE_EXPL); 575 if (rc) { 576 pr_err("Switch to exploitation mode failed with error %lld\n", rc); 577 return false; 578 } 579 580 /* Setup some dummy HV pool VPs */ 581 xive_native_setup_pools(); 582 583 /* Initialize XIVE core with our backend */ 584 if (!xive_core_init(&xive_native_ops, tima, TM_QW3_HV_PHYS, 585 max_prio)) { 586 opal_xive_reset(OPAL_XIVE_MODE_EMU); 587 return false; 588 } 589 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10)); 590 return true; 591 } 592 593 static bool xive_native_provision_pages(void) 594 { 595 u32 i; 596 void *p; 597 598 for (i = 0; i < xive_provision_chip_count; i++) { 599 u32 chip = xive_provision_chips[i]; 600 601 /* 602 * XXX TODO: Try to make the allocation local to the node where 603 * the chip resides. 604 */ 605 p = kmem_cache_alloc(xive_provision_cache, GFP_KERNEL); 606 if (!p) { 607 pr_err("Failed to allocate provisioning page\n"); 608 return false; 609 } 610 opal_xive_donate_page(chip, __pa(p)); 611 } 612 return true; 613 } 614 615 u32 xive_native_alloc_vp_block(u32 max_vcpus) 616 { 617 s64 rc; 618 u32 order; 619 620 order = fls(max_vcpus) - 1; 621 if (max_vcpus > (1 << order)) 622 order++; 623 624 pr_debug("VP block alloc, for max VCPUs %d use order %d\n", 625 max_vcpus, order); 626 627 for (;;) { 628 rc = opal_xive_alloc_vp_block(order); 629 switch (rc) { 630 case OPAL_BUSY: 631 msleep(OPAL_BUSY_DELAY_MS); 632 break; 633 case OPAL_XIVE_PROVISIONING: 634 if (!xive_native_provision_pages()) 635 return XIVE_INVALID_VP; 636 break; 637 default: 638 if (rc < 0) { 639 pr_err("OPAL failed to allocate VCPUs order %d, err %lld\n", 640 order, rc); 641 return XIVE_INVALID_VP; 642 } 643 return rc; 644 } 645 } 646 } 647 EXPORT_SYMBOL_GPL(xive_native_alloc_vp_block); 648 649 void xive_native_free_vp_block(u32 vp_base) 650 { 651 s64 rc; 652 653 if (vp_base == XIVE_INVALID_VP) 654 return; 655 656 rc = opal_xive_free_vp_block(vp_base); 657 if (rc < 0) 658 pr_warn("OPAL error %lld freeing VP block\n", rc); 659 } 660 EXPORT_SYMBOL_GPL(xive_native_free_vp_block); 661 662 int xive_native_enable_vp(u32 vp_id, bool single_escalation) 663 { 664 s64 rc; 665 u64 flags = OPAL_XIVE_VP_ENABLED; 666 667 if (single_escalation) 668 flags |= OPAL_XIVE_VP_SINGLE_ESCALATION; 669 for (;;) { 670 rc = opal_xive_set_vp_info(vp_id, flags, 0); 671 if (rc != OPAL_BUSY) 672 break; 673 msleep(OPAL_BUSY_DELAY_MS); 674 } 675 return rc ? -EIO : 0; 676 } 677 EXPORT_SYMBOL_GPL(xive_native_enable_vp); 678 679 int xive_native_disable_vp(u32 vp_id) 680 { 681 s64 rc; 682 683 for (;;) { 684 rc = opal_xive_set_vp_info(vp_id, 0, 0); 685 if (rc != OPAL_BUSY) 686 break; 687 msleep(OPAL_BUSY_DELAY_MS); 688 } 689 return rc ? -EIO : 0; 690 } 691 EXPORT_SYMBOL_GPL(xive_native_disable_vp); 692 693 int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id) 694 { 695 __be64 vp_cam_be; 696 __be32 vp_chip_id_be; 697 s64 rc; 698 699 rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be); 700 if (rc) 701 return -EIO; 702 *out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu; 703 *out_chip_id = be32_to_cpu(vp_chip_id_be); 704 705 return 0; 706 } 707 EXPORT_SYMBOL_GPL(xive_native_get_vp_info); 708 709 bool xive_native_has_single_escalation(void) 710 { 711 return xive_has_single_esc; 712 } 713 EXPORT_SYMBOL_GPL(xive_native_has_single_escalation); 714