1 /* 2 * Copyright 2016,2017 IBM Corporation. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #define pr_fmt(fmt) "xive: " fmt 11 12 #include <linux/types.h> 13 #include <linux/irq.h> 14 #include <linux/debugfs.h> 15 #include <linux/smp.h> 16 #include <linux/interrupt.h> 17 #include <linux/seq_file.h> 18 #include <linux/init.h> 19 #include <linux/of.h> 20 #include <linux/slab.h> 21 #include <linux/spinlock.h> 22 #include <linux/delay.h> 23 #include <linux/cpumask.h> 24 #include <linux/mm.h> 25 26 #include <asm/prom.h> 27 #include <asm/io.h> 28 #include <asm/smp.h> 29 #include <asm/irq.h> 30 #include <asm/errno.h> 31 #include <asm/xive.h> 32 #include <asm/xive-regs.h> 33 #include <asm/opal.h> 34 #include <asm/kvm_ppc.h> 35 36 #include "xive-internal.h" 37 38 39 static u32 xive_provision_size; 40 static u32 *xive_provision_chips; 41 static u32 xive_provision_chip_count; 42 static u32 xive_queue_shift; 43 static u32 xive_pool_vps = XIVE_INVALID_VP; 44 static struct kmem_cache *xive_provision_cache; 45 46 int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data) 47 { 48 __be64 flags, eoi_page, trig_page; 49 __be32 esb_shift, src_chip; 50 u64 opal_flags; 51 s64 rc; 52 53 memset(data, 0, sizeof(*data)); 54 55 rc = opal_xive_get_irq_info(hw_irq, &flags, &eoi_page, &trig_page, 56 &esb_shift, &src_chip); 57 if (rc) { 58 pr_err("opal_xive_get_irq_info(0x%x) returned %lld\n", 59 hw_irq, rc); 60 return -EINVAL; 61 } 62 63 opal_flags = be64_to_cpu(flags); 64 if (opal_flags & OPAL_XIVE_IRQ_STORE_EOI) 65 data->flags |= XIVE_IRQ_FLAG_STORE_EOI; 66 if (opal_flags & OPAL_XIVE_IRQ_LSI) 67 data->flags |= XIVE_IRQ_FLAG_LSI; 68 if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG) 69 data->flags |= XIVE_IRQ_FLAG_SHIFT_BUG; 70 if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW) 71 data->flags |= XIVE_IRQ_FLAG_MASK_FW; 72 if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW) 73 data->flags |= XIVE_IRQ_FLAG_EOI_FW; 74 data->eoi_page = be64_to_cpu(eoi_page); 75 data->trig_page = be64_to_cpu(trig_page); 76 data->esb_shift = be32_to_cpu(esb_shift); 77 data->src_chip = be32_to_cpu(src_chip); 78 79 data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift); 80 if (!data->eoi_mmio) { 81 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq); 82 return -ENOMEM; 83 } 84 85 if (!data->trig_page) 86 return 0; 87 if (data->trig_page == data->eoi_page) { 88 data->trig_mmio = data->eoi_mmio; 89 return 0; 90 } 91 92 data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift); 93 if (!data->trig_mmio) { 94 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq); 95 return -ENOMEM; 96 } 97 return 0; 98 } 99 EXPORT_SYMBOL_GPL(xive_native_populate_irq_data); 100 101 int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) 102 { 103 s64 rc; 104 105 for (;;) { 106 rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq); 107 if (rc != OPAL_BUSY) 108 break; 109 msleep(1); 110 } 111 return rc == 0 ? 0 : -ENXIO; 112 } 113 EXPORT_SYMBOL_GPL(xive_native_configure_irq); 114 115 116 /* This can be called multiple time to change a queue configuration */ 117 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, 118 __be32 *qpage, u32 order, bool can_escalate) 119 { 120 s64 rc = 0; 121 __be64 qeoi_page_be; 122 __be32 esc_irq_be; 123 u64 flags, qpage_phys; 124 125 /* If there's an actual queue page, clean it */ 126 if (order) { 127 if (WARN_ON(!qpage)) 128 return -EINVAL; 129 qpage_phys = __pa(qpage); 130 } else 131 qpage_phys = 0; 132 133 /* Initialize the rest of the fields */ 134 q->msk = order ? ((1u << (order - 2)) - 1) : 0; 135 q->idx = 0; 136 q->toggle = 0; 137 138 rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL, 139 &qeoi_page_be, 140 &esc_irq_be, 141 NULL); 142 if (rc) { 143 pr_err("Error %lld getting queue info prio %d\n", rc, prio); 144 rc = -EIO; 145 goto fail; 146 } 147 q->eoi_phys = be64_to_cpu(qeoi_page_be); 148 149 /* Default flags */ 150 flags = OPAL_XIVE_EQ_ALWAYS_NOTIFY | OPAL_XIVE_EQ_ENABLED; 151 152 /* Escalation needed ? */ 153 if (can_escalate) { 154 q->esc_irq = be32_to_cpu(esc_irq_be); 155 flags |= OPAL_XIVE_EQ_ESCALATE; 156 } 157 158 /* Configure and enable the queue in HW */ 159 for (;;) { 160 rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags); 161 if (rc != OPAL_BUSY) 162 break; 163 msleep(1); 164 } 165 if (rc) { 166 pr_err("Error %lld setting queue for prio %d\n", rc, prio); 167 rc = -EIO; 168 } else { 169 /* 170 * KVM code requires all of the above to be visible before 171 * q->qpage is set due to how it manages IPI EOIs 172 */ 173 wmb(); 174 q->qpage = qpage; 175 } 176 fail: 177 return rc; 178 } 179 EXPORT_SYMBOL_GPL(xive_native_configure_queue); 180 181 static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) 182 { 183 s64 rc; 184 185 /* Disable the queue in HW */ 186 for (;;) { 187 rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0); 188 if (rc != OPAL_BUSY) 189 break; 190 msleep(1); 191 } 192 if (rc) 193 pr_err("Error %lld disabling queue for prio %d\n", rc, prio); 194 } 195 196 void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) 197 { 198 __xive_native_disable_queue(vp_id, q, prio); 199 } 200 EXPORT_SYMBOL_GPL(xive_native_disable_queue); 201 202 static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio) 203 { 204 struct xive_q *q = &xc->queue[prio]; 205 unsigned int alloc_order; 206 struct page *pages; 207 __be32 *qpage; 208 209 alloc_order = (xive_queue_shift > PAGE_SHIFT) ? 210 (xive_queue_shift - PAGE_SHIFT) : 0; 211 pages = alloc_pages_node(cpu_to_node(cpu), GFP_KERNEL, alloc_order); 212 if (!pages) 213 return -ENOMEM; 214 qpage = (__be32 *)page_address(pages); 215 memset(qpage, 0, 1 << xive_queue_shift); 216 return xive_native_configure_queue(get_hard_smp_processor_id(cpu), 217 q, prio, qpage, xive_queue_shift, false); 218 } 219 220 static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio) 221 { 222 struct xive_q *q = &xc->queue[prio]; 223 unsigned int alloc_order; 224 225 /* 226 * We use the variant with no iounmap as this is called on exec 227 * from an IPI and iounmap isn't safe 228 */ 229 __xive_native_disable_queue(get_hard_smp_processor_id(cpu), q, prio); 230 alloc_order = (xive_queue_shift > PAGE_SHIFT) ? 231 (xive_queue_shift - PAGE_SHIFT) : 0; 232 free_pages((unsigned long)q->qpage, alloc_order); 233 q->qpage = NULL; 234 } 235 236 static bool xive_native_match(struct device_node *node) 237 { 238 return of_device_is_compatible(node, "ibm,opal-xive-vc"); 239 } 240 241 #ifdef CONFIG_SMP 242 static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc) 243 { 244 struct device_node *np; 245 unsigned int chip_id; 246 s64 irq; 247 248 /* Find the chip ID */ 249 np = of_get_cpu_node(cpu, NULL); 250 if (np) { 251 if (of_property_read_u32(np, "ibm,chip-id", &chip_id) < 0) 252 chip_id = 0; 253 } 254 255 /* Allocate an IPI and populate info about it */ 256 for (;;) { 257 irq = opal_xive_allocate_irq(chip_id); 258 if (irq == OPAL_BUSY) { 259 msleep(1); 260 continue; 261 } 262 if (irq < 0) { 263 pr_err("Failed to allocate IPI on CPU %d\n", cpu); 264 return -ENXIO; 265 } 266 xc->hw_ipi = irq; 267 break; 268 } 269 return 0; 270 } 271 #endif /* CONFIG_SMP */ 272 273 u32 xive_native_alloc_irq(void) 274 { 275 s64 rc; 276 277 for (;;) { 278 rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP); 279 if (rc != OPAL_BUSY) 280 break; 281 msleep(1); 282 } 283 if (rc < 0) 284 return 0; 285 return rc; 286 } 287 EXPORT_SYMBOL_GPL(xive_native_alloc_irq); 288 289 void xive_native_free_irq(u32 irq) 290 { 291 for (;;) { 292 s64 rc = opal_xive_free_irq(irq); 293 if (rc != OPAL_BUSY) 294 break; 295 msleep(1); 296 } 297 } 298 EXPORT_SYMBOL_GPL(xive_native_free_irq); 299 300 #ifdef CONFIG_SMP 301 static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc) 302 { 303 s64 rc; 304 305 /* Free the IPI */ 306 if (!xc->hw_ipi) 307 return; 308 for (;;) { 309 rc = opal_xive_free_irq(xc->hw_ipi); 310 if (rc == OPAL_BUSY) { 311 msleep(1); 312 continue; 313 } 314 xc->hw_ipi = 0; 315 break; 316 } 317 } 318 #endif /* CONFIG_SMP */ 319 320 static void xive_native_shutdown(void) 321 { 322 /* Switch the XIVE to emulation mode */ 323 opal_xive_reset(OPAL_XIVE_MODE_EMU); 324 } 325 326 /* 327 * Perform an "ack" cycle on the current thread, thus 328 * grabbing the pending active priorities and updating 329 * the CPPR to the most favored one. 330 */ 331 static void xive_native_update_pending(struct xive_cpu *xc) 332 { 333 u8 he, cppr; 334 u16 ack; 335 336 /* Perform the acknowledge hypervisor to register cycle */ 337 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_HV_REG)); 338 339 /* Synchronize subsequent queue accesses */ 340 mb(); 341 342 /* 343 * Grab the CPPR and the "HE" field which indicates the source 344 * of the hypervisor interrupt (if any) 345 */ 346 cppr = ack & 0xff; 347 he = GETFIELD(TM_QW3_NSR_HE, (ack >> 8)); 348 switch(he) { 349 case TM_QW3_NSR_HE_NONE: /* Nothing to see here */ 350 break; 351 case TM_QW3_NSR_HE_PHYS: /* Physical thread interrupt */ 352 if (cppr == 0xff) 353 return; 354 /* Mark the priority pending */ 355 xc->pending_prio |= 1 << cppr; 356 357 /* 358 * A new interrupt should never have a CPPR less favored 359 * than our current one. 360 */ 361 if (cppr >= xc->cppr) 362 pr_err("CPU %d odd ack CPPR, got %d at %d\n", 363 smp_processor_id(), cppr, xc->cppr); 364 365 /* Update our idea of what the CPPR is */ 366 xc->cppr = cppr; 367 break; 368 case TM_QW3_NSR_HE_POOL: /* HV Pool interrupt (unused) */ 369 case TM_QW3_NSR_HE_LSI: /* Legacy FW LSI (unused) */ 370 pr_err("CPU %d got unexpected interrupt type HE=%d\n", 371 smp_processor_id(), he); 372 return; 373 } 374 } 375 376 static void xive_native_eoi(u32 hw_irq) 377 { 378 /* 379 * Not normally used except if specific interrupts need 380 * a workaround on EOI. 381 */ 382 opal_int_eoi(hw_irq); 383 } 384 385 static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc) 386 { 387 s64 rc; 388 u32 vp; 389 __be64 vp_cam_be; 390 u64 vp_cam; 391 392 if (xive_pool_vps == XIVE_INVALID_VP) 393 return; 394 395 /* Enable the pool VP */ 396 vp = xive_pool_vps + cpu; 397 pr_debug("CPU %d setting up pool VP 0x%x\n", cpu, vp); 398 for (;;) { 399 rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0); 400 if (rc != OPAL_BUSY) 401 break; 402 msleep(1); 403 } 404 if (rc) { 405 pr_err("Failed to enable pool VP on CPU %d\n", cpu); 406 return; 407 } 408 409 /* Grab it's CAM value */ 410 rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL); 411 if (rc) { 412 pr_err("Failed to get pool VP info CPU %d\n", cpu); 413 return; 414 } 415 vp_cam = be64_to_cpu(vp_cam_be); 416 417 pr_debug("VP CAM = %llx\n", vp_cam); 418 419 /* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */ 420 pr_debug("(Old HW value: %08x)\n", 421 in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2)); 422 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff); 423 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2, 424 TM_QW2W2_VP | vp_cam); 425 pr_debug("(New HW value: %08x)\n", 426 in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2)); 427 } 428 429 static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc) 430 { 431 s64 rc; 432 u32 vp; 433 434 if (xive_pool_vps == XIVE_INVALID_VP) 435 return; 436 437 /* Pull the pool VP from the CPU */ 438 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX); 439 440 /* Disable it */ 441 vp = xive_pool_vps + cpu; 442 for (;;) { 443 rc = opal_xive_set_vp_info(vp, 0, 0); 444 if (rc != OPAL_BUSY) 445 break; 446 msleep(1); 447 } 448 } 449 450 void xive_native_sync_source(u32 hw_irq) 451 { 452 opal_xive_sync(XIVE_SYNC_EAS, hw_irq); 453 } 454 EXPORT_SYMBOL_GPL(xive_native_sync_source); 455 456 static const struct xive_ops xive_native_ops = { 457 .populate_irq_data = xive_native_populate_irq_data, 458 .configure_irq = xive_native_configure_irq, 459 .setup_queue = xive_native_setup_queue, 460 .cleanup_queue = xive_native_cleanup_queue, 461 .match = xive_native_match, 462 .shutdown = xive_native_shutdown, 463 .update_pending = xive_native_update_pending, 464 .eoi = xive_native_eoi, 465 .setup_cpu = xive_native_setup_cpu, 466 .teardown_cpu = xive_native_teardown_cpu, 467 .sync_source = xive_native_sync_source, 468 #ifdef CONFIG_SMP 469 .get_ipi = xive_native_get_ipi, 470 .put_ipi = xive_native_put_ipi, 471 #endif /* CONFIG_SMP */ 472 .name = "native", 473 }; 474 475 static bool xive_parse_provisioning(struct device_node *np) 476 { 477 int rc; 478 479 if (of_property_read_u32(np, "ibm,xive-provision-page-size", 480 &xive_provision_size) < 0) 481 return true; 482 rc = of_property_count_elems_of_size(np, "ibm,xive-provision-chips", 4); 483 if (rc < 0) { 484 pr_err("Error %d getting provision chips array\n", rc); 485 return false; 486 } 487 xive_provision_chip_count = rc; 488 if (rc == 0) 489 return true; 490 491 xive_provision_chips = kzalloc(4 * xive_provision_chip_count, 492 GFP_KERNEL); 493 if (WARN_ON(!xive_provision_chips)) 494 return false; 495 496 rc = of_property_read_u32_array(np, "ibm,xive-provision-chips", 497 xive_provision_chips, 498 xive_provision_chip_count); 499 if (rc < 0) { 500 pr_err("Error %d reading provision chips array\n", rc); 501 return false; 502 } 503 504 xive_provision_cache = kmem_cache_create("xive-provision", 505 xive_provision_size, 506 xive_provision_size, 507 0, NULL); 508 if (!xive_provision_cache) { 509 pr_err("Failed to allocate provision cache\n"); 510 return false; 511 } 512 return true; 513 } 514 515 static void xive_native_setup_pools(void) 516 { 517 /* Allocate a pool big enough */ 518 pr_debug("XIVE: Allocating VP block for pool size %d\n", nr_cpu_ids); 519 520 xive_pool_vps = xive_native_alloc_vp_block(nr_cpu_ids); 521 if (WARN_ON(xive_pool_vps == XIVE_INVALID_VP)) 522 pr_err("XIVE: Failed to allocate pool VP, KVM might not function\n"); 523 524 pr_debug("XIVE: Pool VPs allocated at 0x%x for %d max CPUs\n", 525 xive_pool_vps, nr_cpu_ids); 526 } 527 528 u32 xive_native_default_eq_shift(void) 529 { 530 return xive_queue_shift; 531 } 532 EXPORT_SYMBOL_GPL(xive_native_default_eq_shift); 533 534 bool xive_native_init(void) 535 { 536 struct device_node *np; 537 struct resource r; 538 void __iomem *tima; 539 struct property *prop; 540 u8 max_prio = 7; 541 const __be32 *p; 542 u32 val, cpu; 543 s64 rc; 544 545 if (xive_cmdline_disabled) 546 return false; 547 548 pr_devel("xive_native_init()\n"); 549 np = of_find_compatible_node(NULL, NULL, "ibm,opal-xive-pe"); 550 if (!np) { 551 pr_devel("not found !\n"); 552 return false; 553 } 554 pr_devel("Found %s\n", np->full_name); 555 556 /* Resource 1 is HV window */ 557 if (of_address_to_resource(np, 1, &r)) { 558 pr_err("Failed to get thread mgmnt area resource\n"); 559 return false; 560 } 561 tima = ioremap(r.start, resource_size(&r)); 562 if (!tima) { 563 pr_err("Failed to map thread mgmnt area\n"); 564 return false; 565 } 566 567 /* Read number of priorities */ 568 if (of_property_read_u32(np, "ibm,xive-#priorities", &val) == 0) 569 max_prio = val - 1; 570 571 /* Iterate the EQ sizes and pick one */ 572 of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) { 573 xive_queue_shift = val; 574 if (val == PAGE_SHIFT) 575 break; 576 } 577 578 /* Configure Thread Management areas for KVM */ 579 for_each_possible_cpu(cpu) 580 kvmppc_set_xive_tima(cpu, r.start, tima); 581 582 /* Grab size of provisionning pages */ 583 xive_parse_provisioning(np); 584 585 /* Switch the XIVE to exploitation mode */ 586 rc = opal_xive_reset(OPAL_XIVE_MODE_EXPL); 587 if (rc) { 588 pr_err("Switch to exploitation mode failed with error %lld\n", rc); 589 return false; 590 } 591 592 /* Setup some dummy HV pool VPs */ 593 xive_native_setup_pools(); 594 595 /* Initialize XIVE core with our backend */ 596 if (!xive_core_init(&xive_native_ops, tima, TM_QW3_HV_PHYS, 597 max_prio)) { 598 opal_xive_reset(OPAL_XIVE_MODE_EMU); 599 return false; 600 } 601 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10)); 602 return true; 603 } 604 605 static bool xive_native_provision_pages(void) 606 { 607 u32 i; 608 void *p; 609 610 for (i = 0; i < xive_provision_chip_count; i++) { 611 u32 chip = xive_provision_chips[i]; 612 613 /* 614 * XXX TODO: Try to make the allocation local to the node where 615 * the chip resides. 616 */ 617 p = kmem_cache_alloc(xive_provision_cache, GFP_KERNEL); 618 if (!p) { 619 pr_err("Failed to allocate provisioning page\n"); 620 return false; 621 } 622 opal_xive_donate_page(chip, __pa(p)); 623 } 624 return true; 625 } 626 627 u32 xive_native_alloc_vp_block(u32 max_vcpus) 628 { 629 s64 rc; 630 u32 order; 631 632 order = fls(max_vcpus) - 1; 633 if (max_vcpus > (1 << order)) 634 order++; 635 636 pr_debug("VP block alloc, for max VCPUs %d use order %d\n", 637 max_vcpus, order); 638 639 for (;;) { 640 rc = opal_xive_alloc_vp_block(order); 641 switch (rc) { 642 case OPAL_BUSY: 643 msleep(1); 644 break; 645 case OPAL_XIVE_PROVISIONING: 646 if (!xive_native_provision_pages()) 647 return XIVE_INVALID_VP; 648 break; 649 default: 650 if (rc < 0) { 651 pr_err("OPAL failed to allocate VCPUs order %d, err %lld\n", 652 order, rc); 653 return XIVE_INVALID_VP; 654 } 655 return rc; 656 } 657 } 658 } 659 EXPORT_SYMBOL_GPL(xive_native_alloc_vp_block); 660 661 void xive_native_free_vp_block(u32 vp_base) 662 { 663 s64 rc; 664 665 if (vp_base == XIVE_INVALID_VP) 666 return; 667 668 rc = opal_xive_free_vp_block(vp_base); 669 if (rc < 0) 670 pr_warn("OPAL error %lld freeing VP block\n", rc); 671 } 672 EXPORT_SYMBOL_GPL(xive_native_free_vp_block); 673 674 int xive_native_enable_vp(u32 vp_id) 675 { 676 s64 rc; 677 678 for (;;) { 679 rc = opal_xive_set_vp_info(vp_id, OPAL_XIVE_VP_ENABLED, 0); 680 if (rc != OPAL_BUSY) 681 break; 682 msleep(1); 683 } 684 return rc ? -EIO : 0; 685 } 686 EXPORT_SYMBOL_GPL(xive_native_enable_vp); 687 688 int xive_native_disable_vp(u32 vp_id) 689 { 690 s64 rc; 691 692 for (;;) { 693 rc = opal_xive_set_vp_info(vp_id, 0, 0); 694 if (rc != OPAL_BUSY) 695 break; 696 msleep(1); 697 } 698 return rc ? -EIO : 0; 699 } 700 EXPORT_SYMBOL_GPL(xive_native_disable_vp); 701 702 int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id) 703 { 704 __be64 vp_cam_be; 705 __be32 vp_chip_id_be; 706 s64 rc; 707 708 rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be); 709 if (rc) 710 return -EIO; 711 *out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu; 712 *out_chip_id = be32_to_cpu(vp_chip_id_be); 713 714 return 0; 715 } 716 EXPORT_SYMBOL_GPL(xive_native_get_vp_info); 717