1 /* 2 * Copyright 2016,2017 IBM Corporation. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #define pr_fmt(fmt) "xive: " fmt 11 12 #include <linux/types.h> 13 #include <linux/irq.h> 14 #include <linux/debugfs.h> 15 #include <linux/smp.h> 16 #include <linux/interrupt.h> 17 #include <linux/seq_file.h> 18 #include <linux/init.h> 19 #include <linux/of.h> 20 #include <linux/slab.h> 21 #include <linux/spinlock.h> 22 #include <linux/delay.h> 23 #include <linux/cpumask.h> 24 #include <linux/mm.h> 25 26 #include <asm/prom.h> 27 #include <asm/io.h> 28 #include <asm/smp.h> 29 #include <asm/irq.h> 30 #include <asm/errno.h> 31 #include <asm/xive.h> 32 #include <asm/xive-regs.h> 33 #include <asm/opal.h> 34 #include <asm/kvm_ppc.h> 35 36 #include "xive-internal.h" 37 38 39 static u32 xive_provision_size; 40 static u32 *xive_provision_chips; 41 static u32 xive_provision_chip_count; 42 static u32 xive_queue_shift; 43 static u32 xive_pool_vps = XIVE_INVALID_VP; 44 static struct kmem_cache *xive_provision_cache; 45 46 int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data) 47 { 48 __be64 flags, eoi_page, trig_page; 49 __be32 esb_shift, src_chip; 50 u64 opal_flags; 51 s64 rc; 52 53 memset(data, 0, sizeof(*data)); 54 55 rc = opal_xive_get_irq_info(hw_irq, &flags, &eoi_page, &trig_page, 56 &esb_shift, &src_chip); 57 if (rc) { 58 pr_err("opal_xive_get_irq_info(0x%x) returned %lld\n", 59 hw_irq, rc); 60 return -EINVAL; 61 } 62 63 opal_flags = be64_to_cpu(flags); 64 if (opal_flags & OPAL_XIVE_IRQ_STORE_EOI) 65 data->flags |= XIVE_IRQ_FLAG_STORE_EOI; 66 if (opal_flags & OPAL_XIVE_IRQ_LSI) 67 data->flags |= XIVE_IRQ_FLAG_LSI; 68 if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG) 69 data->flags |= XIVE_IRQ_FLAG_SHIFT_BUG; 70 if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW) 71 data->flags |= XIVE_IRQ_FLAG_MASK_FW; 72 if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW) 73 data->flags |= XIVE_IRQ_FLAG_EOI_FW; 74 data->eoi_page = be64_to_cpu(eoi_page); 75 data->trig_page = be64_to_cpu(trig_page); 76 data->esb_shift = be32_to_cpu(esb_shift); 77 data->src_chip = be32_to_cpu(src_chip); 78 79 data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift); 80 if (!data->eoi_mmio) { 81 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq); 82 return -ENOMEM; 83 } 84 85 data->hw_irq = hw_irq; 86 87 if (!data->trig_page) 88 return 0; 89 if (data->trig_page == data->eoi_page) { 90 data->trig_mmio = data->eoi_mmio; 91 return 0; 92 } 93 94 data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift); 95 if (!data->trig_mmio) { 96 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq); 97 return -ENOMEM; 98 } 99 return 0; 100 } 101 EXPORT_SYMBOL_GPL(xive_native_populate_irq_data); 102 103 int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) 104 { 105 s64 rc; 106 107 for (;;) { 108 rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq); 109 if (rc != OPAL_BUSY) 110 break; 111 msleep(1); 112 } 113 return rc == 0 ? 0 : -ENXIO; 114 } 115 EXPORT_SYMBOL_GPL(xive_native_configure_irq); 116 117 118 /* This can be called multiple time to change a queue configuration */ 119 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, 120 __be32 *qpage, u32 order, bool can_escalate) 121 { 122 s64 rc = 0; 123 __be64 qeoi_page_be; 124 __be32 esc_irq_be; 125 u64 flags, qpage_phys; 126 127 /* If there's an actual queue page, clean it */ 128 if (order) { 129 if (WARN_ON(!qpage)) 130 return -EINVAL; 131 qpage_phys = __pa(qpage); 132 } else 133 qpage_phys = 0; 134 135 /* Initialize the rest of the fields */ 136 q->msk = order ? ((1u << (order - 2)) - 1) : 0; 137 q->idx = 0; 138 q->toggle = 0; 139 140 rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL, 141 &qeoi_page_be, 142 &esc_irq_be, 143 NULL); 144 if (rc) { 145 pr_err("Error %lld getting queue info prio %d\n", rc, prio); 146 rc = -EIO; 147 goto fail; 148 } 149 q->eoi_phys = be64_to_cpu(qeoi_page_be); 150 151 /* Default flags */ 152 flags = OPAL_XIVE_EQ_ALWAYS_NOTIFY | OPAL_XIVE_EQ_ENABLED; 153 154 /* Escalation needed ? */ 155 if (can_escalate) { 156 q->esc_irq = be32_to_cpu(esc_irq_be); 157 flags |= OPAL_XIVE_EQ_ESCALATE; 158 } 159 160 /* Configure and enable the queue in HW */ 161 for (;;) { 162 rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags); 163 if (rc != OPAL_BUSY) 164 break; 165 msleep(1); 166 } 167 if (rc) { 168 pr_err("Error %lld setting queue for prio %d\n", rc, prio); 169 rc = -EIO; 170 } else { 171 /* 172 * KVM code requires all of the above to be visible before 173 * q->qpage is set due to how it manages IPI EOIs 174 */ 175 wmb(); 176 q->qpage = qpage; 177 } 178 fail: 179 return rc; 180 } 181 EXPORT_SYMBOL_GPL(xive_native_configure_queue); 182 183 static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) 184 { 185 s64 rc; 186 187 /* Disable the queue in HW */ 188 for (;;) { 189 rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0); 190 if (rc != OPAL_BUSY) 191 break; 192 msleep(1); 193 } 194 if (rc) 195 pr_err("Error %lld disabling queue for prio %d\n", rc, prio); 196 } 197 198 void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) 199 { 200 __xive_native_disable_queue(vp_id, q, prio); 201 } 202 EXPORT_SYMBOL_GPL(xive_native_disable_queue); 203 204 static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio) 205 { 206 struct xive_q *q = &xc->queue[prio]; 207 __be32 *qpage; 208 209 qpage = xive_queue_page_alloc(cpu, xive_queue_shift); 210 if (IS_ERR(qpage)) 211 return PTR_ERR(qpage); 212 213 return xive_native_configure_queue(get_hard_smp_processor_id(cpu), 214 q, prio, qpage, xive_queue_shift, false); 215 } 216 217 static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio) 218 { 219 struct xive_q *q = &xc->queue[prio]; 220 unsigned int alloc_order; 221 222 /* 223 * We use the variant with no iounmap as this is called on exec 224 * from an IPI and iounmap isn't safe 225 */ 226 __xive_native_disable_queue(get_hard_smp_processor_id(cpu), q, prio); 227 alloc_order = xive_alloc_order(xive_queue_shift); 228 free_pages((unsigned long)q->qpage, alloc_order); 229 q->qpage = NULL; 230 } 231 232 static bool xive_native_match(struct device_node *node) 233 { 234 return of_device_is_compatible(node, "ibm,opal-xive-vc"); 235 } 236 237 #ifdef CONFIG_SMP 238 static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc) 239 { 240 struct device_node *np; 241 unsigned int chip_id; 242 s64 irq; 243 244 /* Find the chip ID */ 245 np = of_get_cpu_node(cpu, NULL); 246 if (np) { 247 if (of_property_read_u32(np, "ibm,chip-id", &chip_id) < 0) 248 chip_id = 0; 249 } 250 251 /* Allocate an IPI and populate info about it */ 252 for (;;) { 253 irq = opal_xive_allocate_irq(chip_id); 254 if (irq == OPAL_BUSY) { 255 msleep(1); 256 continue; 257 } 258 if (irq < 0) { 259 pr_err("Failed to allocate IPI on CPU %d\n", cpu); 260 return -ENXIO; 261 } 262 xc->hw_ipi = irq; 263 break; 264 } 265 return 0; 266 } 267 #endif /* CONFIG_SMP */ 268 269 u32 xive_native_alloc_irq(void) 270 { 271 s64 rc; 272 273 for (;;) { 274 rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP); 275 if (rc != OPAL_BUSY) 276 break; 277 msleep(1); 278 } 279 if (rc < 0) 280 return 0; 281 return rc; 282 } 283 EXPORT_SYMBOL_GPL(xive_native_alloc_irq); 284 285 void xive_native_free_irq(u32 irq) 286 { 287 for (;;) { 288 s64 rc = opal_xive_free_irq(irq); 289 if (rc != OPAL_BUSY) 290 break; 291 msleep(1); 292 } 293 } 294 EXPORT_SYMBOL_GPL(xive_native_free_irq); 295 296 #ifdef CONFIG_SMP 297 static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc) 298 { 299 s64 rc; 300 301 /* Free the IPI */ 302 if (!xc->hw_ipi) 303 return; 304 for (;;) { 305 rc = opal_xive_free_irq(xc->hw_ipi); 306 if (rc == OPAL_BUSY) { 307 msleep(1); 308 continue; 309 } 310 xc->hw_ipi = 0; 311 break; 312 } 313 } 314 #endif /* CONFIG_SMP */ 315 316 static void xive_native_shutdown(void) 317 { 318 /* Switch the XIVE to emulation mode */ 319 opal_xive_reset(OPAL_XIVE_MODE_EMU); 320 } 321 322 /* 323 * Perform an "ack" cycle on the current thread, thus 324 * grabbing the pending active priorities and updating 325 * the CPPR to the most favored one. 326 */ 327 static void xive_native_update_pending(struct xive_cpu *xc) 328 { 329 u8 he, cppr; 330 u16 ack; 331 332 /* Perform the acknowledge hypervisor to register cycle */ 333 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_HV_REG)); 334 335 /* Synchronize subsequent queue accesses */ 336 mb(); 337 338 /* 339 * Grab the CPPR and the "HE" field which indicates the source 340 * of the hypervisor interrupt (if any) 341 */ 342 cppr = ack & 0xff; 343 he = GETFIELD(TM_QW3_NSR_HE, (ack >> 8)); 344 switch(he) { 345 case TM_QW3_NSR_HE_NONE: /* Nothing to see here */ 346 break; 347 case TM_QW3_NSR_HE_PHYS: /* Physical thread interrupt */ 348 if (cppr == 0xff) 349 return; 350 /* Mark the priority pending */ 351 xc->pending_prio |= 1 << cppr; 352 353 /* 354 * A new interrupt should never have a CPPR less favored 355 * than our current one. 356 */ 357 if (cppr >= xc->cppr) 358 pr_err("CPU %d odd ack CPPR, got %d at %d\n", 359 smp_processor_id(), cppr, xc->cppr); 360 361 /* Update our idea of what the CPPR is */ 362 xc->cppr = cppr; 363 break; 364 case TM_QW3_NSR_HE_POOL: /* HV Pool interrupt (unused) */ 365 case TM_QW3_NSR_HE_LSI: /* Legacy FW LSI (unused) */ 366 pr_err("CPU %d got unexpected interrupt type HE=%d\n", 367 smp_processor_id(), he); 368 return; 369 } 370 } 371 372 static void xive_native_eoi(u32 hw_irq) 373 { 374 /* 375 * Not normally used except if specific interrupts need 376 * a workaround on EOI. 377 */ 378 opal_int_eoi(hw_irq); 379 } 380 381 static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc) 382 { 383 s64 rc; 384 u32 vp; 385 __be64 vp_cam_be; 386 u64 vp_cam; 387 388 if (xive_pool_vps == XIVE_INVALID_VP) 389 return; 390 391 /* Enable the pool VP */ 392 vp = xive_pool_vps + cpu; 393 pr_debug("CPU %d setting up pool VP 0x%x\n", cpu, vp); 394 for (;;) { 395 rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0); 396 if (rc != OPAL_BUSY) 397 break; 398 msleep(1); 399 } 400 if (rc) { 401 pr_err("Failed to enable pool VP on CPU %d\n", cpu); 402 return; 403 } 404 405 /* Grab it's CAM value */ 406 rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL); 407 if (rc) { 408 pr_err("Failed to get pool VP info CPU %d\n", cpu); 409 return; 410 } 411 vp_cam = be64_to_cpu(vp_cam_be); 412 413 pr_debug("VP CAM = %llx\n", vp_cam); 414 415 /* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */ 416 pr_debug("(Old HW value: %08x)\n", 417 in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2)); 418 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff); 419 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2, 420 TM_QW2W2_VP | vp_cam); 421 pr_debug("(New HW value: %08x)\n", 422 in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2)); 423 } 424 425 static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc) 426 { 427 s64 rc; 428 u32 vp; 429 430 if (xive_pool_vps == XIVE_INVALID_VP) 431 return; 432 433 /* Pull the pool VP from the CPU */ 434 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX); 435 436 /* Disable it */ 437 vp = xive_pool_vps + cpu; 438 for (;;) { 439 rc = opal_xive_set_vp_info(vp, 0, 0); 440 if (rc != OPAL_BUSY) 441 break; 442 msleep(1); 443 } 444 } 445 446 void xive_native_sync_source(u32 hw_irq) 447 { 448 opal_xive_sync(XIVE_SYNC_EAS, hw_irq); 449 } 450 EXPORT_SYMBOL_GPL(xive_native_sync_source); 451 452 static const struct xive_ops xive_native_ops = { 453 .populate_irq_data = xive_native_populate_irq_data, 454 .configure_irq = xive_native_configure_irq, 455 .setup_queue = xive_native_setup_queue, 456 .cleanup_queue = xive_native_cleanup_queue, 457 .match = xive_native_match, 458 .shutdown = xive_native_shutdown, 459 .update_pending = xive_native_update_pending, 460 .eoi = xive_native_eoi, 461 .setup_cpu = xive_native_setup_cpu, 462 .teardown_cpu = xive_native_teardown_cpu, 463 .sync_source = xive_native_sync_source, 464 #ifdef CONFIG_SMP 465 .get_ipi = xive_native_get_ipi, 466 .put_ipi = xive_native_put_ipi, 467 #endif /* CONFIG_SMP */ 468 .name = "native", 469 }; 470 471 static bool xive_parse_provisioning(struct device_node *np) 472 { 473 int rc; 474 475 if (of_property_read_u32(np, "ibm,xive-provision-page-size", 476 &xive_provision_size) < 0) 477 return true; 478 rc = of_property_count_elems_of_size(np, "ibm,xive-provision-chips", 4); 479 if (rc < 0) { 480 pr_err("Error %d getting provision chips array\n", rc); 481 return false; 482 } 483 xive_provision_chip_count = rc; 484 if (rc == 0) 485 return true; 486 487 xive_provision_chips = kzalloc(4 * xive_provision_chip_count, 488 GFP_KERNEL); 489 if (WARN_ON(!xive_provision_chips)) 490 return false; 491 492 rc = of_property_read_u32_array(np, "ibm,xive-provision-chips", 493 xive_provision_chips, 494 xive_provision_chip_count); 495 if (rc < 0) { 496 pr_err("Error %d reading provision chips array\n", rc); 497 return false; 498 } 499 500 xive_provision_cache = kmem_cache_create("xive-provision", 501 xive_provision_size, 502 xive_provision_size, 503 0, NULL); 504 if (!xive_provision_cache) { 505 pr_err("Failed to allocate provision cache\n"); 506 return false; 507 } 508 return true; 509 } 510 511 static void xive_native_setup_pools(void) 512 { 513 /* Allocate a pool big enough */ 514 pr_debug("XIVE: Allocating VP block for pool size %u\n", nr_cpu_ids); 515 516 xive_pool_vps = xive_native_alloc_vp_block(nr_cpu_ids); 517 if (WARN_ON(xive_pool_vps == XIVE_INVALID_VP)) 518 pr_err("XIVE: Failed to allocate pool VP, KVM might not function\n"); 519 520 pr_debug("XIVE: Pool VPs allocated at 0x%x for %u max CPUs\n", 521 xive_pool_vps, nr_cpu_ids); 522 } 523 524 u32 xive_native_default_eq_shift(void) 525 { 526 return xive_queue_shift; 527 } 528 EXPORT_SYMBOL_GPL(xive_native_default_eq_shift); 529 530 bool __init xive_native_init(void) 531 { 532 struct device_node *np; 533 struct resource r; 534 void __iomem *tima; 535 struct property *prop; 536 u8 max_prio = 7; 537 const __be32 *p; 538 u32 val, cpu; 539 s64 rc; 540 541 if (xive_cmdline_disabled) 542 return false; 543 544 pr_devel("xive_native_init()\n"); 545 np = of_find_compatible_node(NULL, NULL, "ibm,opal-xive-pe"); 546 if (!np) { 547 pr_devel("not found !\n"); 548 return false; 549 } 550 pr_devel("Found %pOF\n", np); 551 552 /* Resource 1 is HV window */ 553 if (of_address_to_resource(np, 1, &r)) { 554 pr_err("Failed to get thread mgmnt area resource\n"); 555 return false; 556 } 557 tima = ioremap(r.start, resource_size(&r)); 558 if (!tima) { 559 pr_err("Failed to map thread mgmnt area\n"); 560 return false; 561 } 562 563 /* Read number of priorities */ 564 if (of_property_read_u32(np, "ibm,xive-#priorities", &val) == 0) 565 max_prio = val - 1; 566 567 /* Iterate the EQ sizes and pick one */ 568 of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) { 569 xive_queue_shift = val; 570 if (val == PAGE_SHIFT) 571 break; 572 } 573 574 /* Configure Thread Management areas for KVM */ 575 for_each_possible_cpu(cpu) 576 kvmppc_set_xive_tima(cpu, r.start, tima); 577 578 /* Grab size of provisionning pages */ 579 xive_parse_provisioning(np); 580 581 /* Switch the XIVE to exploitation mode */ 582 rc = opal_xive_reset(OPAL_XIVE_MODE_EXPL); 583 if (rc) { 584 pr_err("Switch to exploitation mode failed with error %lld\n", rc); 585 return false; 586 } 587 588 /* Setup some dummy HV pool VPs */ 589 xive_native_setup_pools(); 590 591 /* Initialize XIVE core with our backend */ 592 if (!xive_core_init(&xive_native_ops, tima, TM_QW3_HV_PHYS, 593 max_prio)) { 594 opal_xive_reset(OPAL_XIVE_MODE_EMU); 595 return false; 596 } 597 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10)); 598 return true; 599 } 600 601 static bool xive_native_provision_pages(void) 602 { 603 u32 i; 604 void *p; 605 606 for (i = 0; i < xive_provision_chip_count; i++) { 607 u32 chip = xive_provision_chips[i]; 608 609 /* 610 * XXX TODO: Try to make the allocation local to the node where 611 * the chip resides. 612 */ 613 p = kmem_cache_alloc(xive_provision_cache, GFP_KERNEL); 614 if (!p) { 615 pr_err("Failed to allocate provisioning page\n"); 616 return false; 617 } 618 opal_xive_donate_page(chip, __pa(p)); 619 } 620 return true; 621 } 622 623 u32 xive_native_alloc_vp_block(u32 max_vcpus) 624 { 625 s64 rc; 626 u32 order; 627 628 order = fls(max_vcpus) - 1; 629 if (max_vcpus > (1 << order)) 630 order++; 631 632 pr_debug("VP block alloc, for max VCPUs %d use order %d\n", 633 max_vcpus, order); 634 635 for (;;) { 636 rc = opal_xive_alloc_vp_block(order); 637 switch (rc) { 638 case OPAL_BUSY: 639 msleep(1); 640 break; 641 case OPAL_XIVE_PROVISIONING: 642 if (!xive_native_provision_pages()) 643 return XIVE_INVALID_VP; 644 break; 645 default: 646 if (rc < 0) { 647 pr_err("OPAL failed to allocate VCPUs order %d, err %lld\n", 648 order, rc); 649 return XIVE_INVALID_VP; 650 } 651 return rc; 652 } 653 } 654 } 655 EXPORT_SYMBOL_GPL(xive_native_alloc_vp_block); 656 657 void xive_native_free_vp_block(u32 vp_base) 658 { 659 s64 rc; 660 661 if (vp_base == XIVE_INVALID_VP) 662 return; 663 664 rc = opal_xive_free_vp_block(vp_base); 665 if (rc < 0) 666 pr_warn("OPAL error %lld freeing VP block\n", rc); 667 } 668 EXPORT_SYMBOL_GPL(xive_native_free_vp_block); 669 670 int xive_native_enable_vp(u32 vp_id) 671 { 672 s64 rc; 673 674 for (;;) { 675 rc = opal_xive_set_vp_info(vp_id, OPAL_XIVE_VP_ENABLED, 0); 676 if (rc != OPAL_BUSY) 677 break; 678 msleep(1); 679 } 680 return rc ? -EIO : 0; 681 } 682 EXPORT_SYMBOL_GPL(xive_native_enable_vp); 683 684 int xive_native_disable_vp(u32 vp_id) 685 { 686 s64 rc; 687 688 for (;;) { 689 rc = opal_xive_set_vp_info(vp_id, 0, 0); 690 if (rc != OPAL_BUSY) 691 break; 692 msleep(1); 693 } 694 return rc ? -EIO : 0; 695 } 696 EXPORT_SYMBOL_GPL(xive_native_disable_vp); 697 698 int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id) 699 { 700 __be64 vp_cam_be; 701 __be32 vp_chip_id_be; 702 s64 rc; 703 704 rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be); 705 if (rc) 706 return -EIO; 707 *out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu; 708 *out_chip_id = be32_to_cpu(vp_chip_id_be); 709 710 return 0; 711 } 712 EXPORT_SYMBOL_GPL(xive_native_get_vp_info); 713