xref: /openbmc/linux/arch/powerpc/sysdev/xive/common.c (revision 8ffdff6a)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright 2016,2017 IBM Corporation.
4  */
5 
6 #define pr_fmt(fmt) "xive: " fmt
7 
8 #include <linux/types.h>
9 #include <linux/threads.h>
10 #include <linux/kernel.h>
11 #include <linux/irq.h>
12 #include <linux/debugfs.h>
13 #include <linux/smp.h>
14 #include <linux/interrupt.h>
15 #include <linux/seq_file.h>
16 #include <linux/init.h>
17 #include <linux/cpu.h>
18 #include <linux/of.h>
19 #include <linux/slab.h>
20 #include <linux/spinlock.h>
21 #include <linux/msi.h>
22 #include <linux/vmalloc.h>
23 
24 #include <asm/debugfs.h>
25 #include <asm/prom.h>
26 #include <asm/io.h>
27 #include <asm/smp.h>
28 #include <asm/machdep.h>
29 #include <asm/irq.h>
30 #include <asm/errno.h>
31 #include <asm/xive.h>
32 #include <asm/xive-regs.h>
33 #include <asm/xmon.h>
34 
35 #include "xive-internal.h"
36 
37 #undef DEBUG_FLUSH
38 #undef DEBUG_ALL
39 
40 #ifdef DEBUG_ALL
41 #define DBG_VERBOSE(fmt, ...)	pr_devel("cpu %d - " fmt, \
42 					 smp_processor_id(), ## __VA_ARGS__)
43 #else
44 #define DBG_VERBOSE(fmt...)	do { } while(0)
45 #endif
46 
47 bool __xive_enabled;
48 EXPORT_SYMBOL_GPL(__xive_enabled);
49 bool xive_cmdline_disabled;
50 
51 /* We use only one priority for now */
52 static u8 xive_irq_priority;
53 
54 /* TIMA exported to KVM */
55 void __iomem *xive_tima;
56 EXPORT_SYMBOL_GPL(xive_tima);
57 u32 xive_tima_offset;
58 
59 /* Backend ops */
60 static const struct xive_ops *xive_ops;
61 
62 /* Our global interrupt domain */
63 static struct irq_domain *xive_irq_domain;
64 
65 #ifdef CONFIG_SMP
66 /* The IPIs all use the same logical irq number */
67 static u32 xive_ipi_irq;
68 #endif
69 
70 /* Xive state for each CPU */
71 static DEFINE_PER_CPU(struct xive_cpu *, xive_cpu);
72 
73 /* An invalid CPU target */
74 #define XIVE_INVALID_TARGET	(-1)
75 
76 /*
77  * Read the next entry in a queue, return its content if it's valid
78  * or 0 if there is no new entry.
79  *
80  * The queue pointer is moved forward unless "just_peek" is set
81  */
82 static u32 xive_read_eq(struct xive_q *q, bool just_peek)
83 {
84 	u32 cur;
85 
86 	if (!q->qpage)
87 		return 0;
88 	cur = be32_to_cpup(q->qpage + q->idx);
89 
90 	/* Check valid bit (31) vs current toggle polarity */
91 	if ((cur >> 31) == q->toggle)
92 		return 0;
93 
94 	/* If consuming from the queue ... */
95 	if (!just_peek) {
96 		/* Next entry */
97 		q->idx = (q->idx + 1) & q->msk;
98 
99 		/* Wrap around: flip valid toggle */
100 		if (q->idx == 0)
101 			q->toggle ^= 1;
102 	}
103 	/* Mask out the valid bit (31) */
104 	return cur & 0x7fffffff;
105 }
106 
107 /*
108  * Scans all the queue that may have interrupts in them
109  * (based on "pending_prio") in priority order until an
110  * interrupt is found or all the queues are empty.
111  *
112  * Then updates the CPPR (Current Processor Priority
113  * Register) based on the most favored interrupt found
114  * (0xff if none) and return what was found (0 if none).
115  *
116  * If just_peek is set, return the most favored pending
117  * interrupt if any but don't update the queue pointers.
118  *
119  * Note: This function can operate generically on any number
120  * of queues (up to 8). The current implementation of the XIVE
121  * driver only uses a single queue however.
122  *
123  * Note2: This will also "flush" "the pending_count" of a queue
124  * into the "count" when that queue is observed to be empty.
125  * This is used to keep track of the amount of interrupts
126  * targetting a queue. When an interrupt is moved away from
127  * a queue, we only decrement that queue count once the queue
128  * has been observed empty to avoid races.
129  */
130 static u32 xive_scan_interrupts(struct xive_cpu *xc, bool just_peek)
131 {
132 	u32 irq = 0;
133 	u8 prio = 0;
134 
135 	/* Find highest pending priority */
136 	while (xc->pending_prio != 0) {
137 		struct xive_q *q;
138 
139 		prio = ffs(xc->pending_prio) - 1;
140 		DBG_VERBOSE("scan_irq: trying prio %d\n", prio);
141 
142 		/* Try to fetch */
143 		irq = xive_read_eq(&xc->queue[prio], just_peek);
144 
145 		/* Found something ? That's it */
146 		if (irq) {
147 			if (just_peek || irq_to_desc(irq))
148 				break;
149 			/*
150 			 * We should never get here; if we do then we must
151 			 * have failed to synchronize the interrupt properly
152 			 * when shutting it down.
153 			 */
154 			pr_crit("xive: got interrupt %d without descriptor, dropping\n",
155 				irq);
156 			WARN_ON(1);
157 			continue;
158 		}
159 
160 		/* Clear pending bits */
161 		xc->pending_prio &= ~(1 << prio);
162 
163 		/*
164 		 * Check if the queue count needs adjusting due to
165 		 * interrupts being moved away. See description of
166 		 * xive_dec_target_count()
167 		 */
168 		q = &xc->queue[prio];
169 		if (atomic_read(&q->pending_count)) {
170 			int p = atomic_xchg(&q->pending_count, 0);
171 			if (p) {
172 				WARN_ON(p > atomic_read(&q->count));
173 				atomic_sub(p, &q->count);
174 			}
175 		}
176 	}
177 
178 	/* If nothing was found, set CPPR to 0xff */
179 	if (irq == 0)
180 		prio = 0xff;
181 
182 	/* Update HW CPPR to match if necessary */
183 	if (prio != xc->cppr) {
184 		DBG_VERBOSE("scan_irq: adjusting CPPR to %d\n", prio);
185 		xc->cppr = prio;
186 		out_8(xive_tima + xive_tima_offset + TM_CPPR, prio);
187 	}
188 
189 	return irq;
190 }
191 
192 /*
193  * This is used to perform the magic loads from an ESB
194  * described in xive-regs.h
195  */
196 static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
197 {
198 	u64 val;
199 
200 	if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
201 		offset |= XIVE_ESB_LD_ST_MO;
202 
203 	if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
204 		val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);
205 	else
206 		val = in_be64(xd->eoi_mmio + offset);
207 
208 	return (u8)val;
209 }
210 
211 static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data)
212 {
213 	if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
214 		xive_ops->esb_rw(xd->hw_irq, offset, data, 1);
215 	else
216 		out_be64(xd->eoi_mmio + offset, data);
217 }
218 
219 #ifdef CONFIG_XMON
220 static notrace void xive_dump_eq(const char *name, struct xive_q *q)
221 {
222 	u32 i0, i1, idx;
223 
224 	if (!q->qpage)
225 		return;
226 	idx = q->idx;
227 	i0 = be32_to_cpup(q->qpage + idx);
228 	idx = (idx + 1) & q->msk;
229 	i1 = be32_to_cpup(q->qpage + idx);
230 	xmon_printf("%s idx=%d T=%d %08x %08x ...", name,
231 		     q->idx, q->toggle, i0, i1);
232 }
233 
234 notrace void xmon_xive_do_dump(int cpu)
235 {
236 	struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
237 
238 	xmon_printf("CPU %d:", cpu);
239 	if (xc) {
240 		xmon_printf("pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr);
241 
242 #ifdef CONFIG_SMP
243 		{
244 			u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET);
245 
246 			xmon_printf("IPI=0x%08x PQ=%c%c ", xc->hw_ipi,
247 				    val & XIVE_ESB_VAL_P ? 'P' : '-',
248 				    val & XIVE_ESB_VAL_Q ? 'Q' : '-');
249 		}
250 #endif
251 		xive_dump_eq("EQ", &xc->queue[xive_irq_priority]);
252 	}
253 	xmon_printf("\n");
254 }
255 
256 int xmon_xive_get_irq_config(u32 hw_irq, struct irq_data *d)
257 {
258 	struct irq_chip *chip = irq_data_get_irq_chip(d);
259 	int rc;
260 	u32 target;
261 	u8 prio;
262 	u32 lirq;
263 
264 	if (!is_xive_irq(chip))
265 		return -EINVAL;
266 
267 	rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq);
268 	if (rc) {
269 		xmon_printf("IRQ 0x%08x : no config rc=%d\n", hw_irq, rc);
270 		return rc;
271 	}
272 
273 	xmon_printf("IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ",
274 		    hw_irq, target, prio, lirq);
275 
276 	if (d) {
277 		struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
278 		u64 val = xive_esb_read(xd, XIVE_ESB_GET);
279 
280 		xmon_printf("flags=%c%c%c PQ=%c%c",
281 			    xd->flags & XIVE_IRQ_FLAG_STORE_EOI ? 'S' : ' ',
282 			    xd->flags & XIVE_IRQ_FLAG_LSI ? 'L' : ' ',
283 			    xd->flags & XIVE_IRQ_FLAG_H_INT_ESB ? 'H' : ' ',
284 			    val & XIVE_ESB_VAL_P ? 'P' : '-',
285 			    val & XIVE_ESB_VAL_Q ? 'Q' : '-');
286 	}
287 
288 	xmon_printf("\n");
289 	return 0;
290 }
291 
292 #endif /* CONFIG_XMON */
293 
294 static unsigned int xive_get_irq(void)
295 {
296 	struct xive_cpu *xc = __this_cpu_read(xive_cpu);
297 	u32 irq;
298 
299 	/*
300 	 * This can be called either as a result of a HW interrupt or
301 	 * as a "replay" because EOI decided there was still something
302 	 * in one of the queues.
303 	 *
304 	 * First we perform an ACK cycle in order to update our mask
305 	 * of pending priorities. This will also have the effect of
306 	 * updating the CPPR to the most favored pending interrupts.
307 	 *
308 	 * In the future, if we have a way to differentiate a first
309 	 * entry (on HW interrupt) from a replay triggered by EOI,
310 	 * we could skip this on replays unless we soft-mask tells us
311 	 * that a new HW interrupt occurred.
312 	 */
313 	xive_ops->update_pending(xc);
314 
315 	DBG_VERBOSE("get_irq: pending=%02x\n", xc->pending_prio);
316 
317 	/* Scan our queue(s) for interrupts */
318 	irq = xive_scan_interrupts(xc, false);
319 
320 	DBG_VERBOSE("get_irq: got irq 0x%x, new pending=0x%02x\n",
321 	    irq, xc->pending_prio);
322 
323 	/* Return pending interrupt if any */
324 	if (irq == XIVE_BAD_IRQ)
325 		return 0;
326 	return irq;
327 }
328 
329 /*
330  * After EOI'ing an interrupt, we need to re-check the queue
331  * to see if another interrupt is pending since multiple
332  * interrupts can coalesce into a single notification to the
333  * CPU.
334  *
335  * If we find that there is indeed more in there, we call
336  * force_external_irq_replay() to make Linux synthetize an
337  * external interrupt on the next call to local_irq_restore().
338  */
339 static void xive_do_queue_eoi(struct xive_cpu *xc)
340 {
341 	if (xive_scan_interrupts(xc, true) != 0) {
342 		DBG_VERBOSE("eoi: pending=0x%02x\n", xc->pending_prio);
343 		force_external_irq_replay();
344 	}
345 }
346 
347 /*
348  * EOI an interrupt at the source. There are several methods
349  * to do this depending on the HW version and source type
350  */
351 static void xive_do_source_eoi(struct xive_irq_data *xd)
352 {
353 	u8 eoi_val;
354 
355 	xd->stale_p = false;
356 
357 	/* If the XIVE supports the new "store EOI facility, use it */
358 	if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI) {
359 		xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0);
360 		return;
361 	}
362 
363 	/*
364 	 * For LSIs, we use the "EOI cycle" special load rather than
365 	 * PQ bits, as they are automatically re-triggered in HW when
366 	 * still pending.
367 	 */
368 	if (xd->flags & XIVE_IRQ_FLAG_LSI) {
369 		xive_esb_read(xd, XIVE_ESB_LOAD_EOI);
370 		return;
371 	}
372 
373 	/*
374 	 * Otherwise, we use the special MMIO that does a clear of
375 	 * both P and Q and returns the old Q. This allows us to then
376 	 * do a re-trigger if Q was set rather than synthesizing an
377 	 * interrupt in software
378 	 */
379 	eoi_val = xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
380 	DBG_VERBOSE("eoi_val=%x\n", eoi_val);
381 
382 	/* Re-trigger if needed */
383 	if ((eoi_val & XIVE_ESB_VAL_Q) && xd->trig_mmio)
384 		out_be64(xd->trig_mmio, 0);
385 }
386 
387 /* irq_chip eoi callback, called with irq descriptor lock held */
388 static void xive_irq_eoi(struct irq_data *d)
389 {
390 	struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
391 	struct xive_cpu *xc = __this_cpu_read(xive_cpu);
392 
393 	DBG_VERBOSE("eoi_irq: irq=%d [0x%lx] pending=%02x\n",
394 		    d->irq, irqd_to_hwirq(d), xc->pending_prio);
395 
396 	/*
397 	 * EOI the source if it hasn't been disabled and hasn't
398 	 * been passed-through to a KVM guest
399 	 */
400 	if (!irqd_irq_disabled(d) && !irqd_is_forwarded_to_vcpu(d) &&
401 	    !(xd->flags & XIVE_IRQ_FLAG_NO_EOI))
402 		xive_do_source_eoi(xd);
403 	else
404 		xd->stale_p = true;
405 
406 	/*
407 	 * Clear saved_p to indicate that it's no longer occupying
408 	 * a queue slot on the target queue
409 	 */
410 	xd->saved_p = false;
411 
412 	/* Check for more work in the queue */
413 	xive_do_queue_eoi(xc);
414 }
415 
416 /*
417  * Helper used to mask and unmask an interrupt source.
418  */
419 static void xive_do_source_set_mask(struct xive_irq_data *xd,
420 				    bool mask)
421 {
422 	u64 val;
423 
424 	/*
425 	 * If the interrupt had P set, it may be in a queue.
426 	 *
427 	 * We need to make sure we don't re-enable it until it
428 	 * has been fetched from that queue and EOId. We keep
429 	 * a copy of that P state and use it to restore the
430 	 * ESB accordingly on unmask.
431 	 */
432 	if (mask) {
433 		val = xive_esb_read(xd, XIVE_ESB_SET_PQ_01);
434 		if (!xd->stale_p && !!(val & XIVE_ESB_VAL_P))
435 			xd->saved_p = true;
436 		xd->stale_p = false;
437 	} else if (xd->saved_p) {
438 		xive_esb_read(xd, XIVE_ESB_SET_PQ_10);
439 		xd->saved_p = false;
440 	} else {
441 		xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
442 		xd->stale_p = false;
443 	}
444 }
445 
446 /*
447  * Try to chose "cpu" as a new interrupt target. Increments
448  * the queue accounting for that target if it's not already
449  * full.
450  */
451 static bool xive_try_pick_target(int cpu)
452 {
453 	struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
454 	struct xive_q *q = &xc->queue[xive_irq_priority];
455 	int max;
456 
457 	/*
458 	 * Calculate max number of interrupts in that queue.
459 	 *
460 	 * We leave a gap of 1 just in case...
461 	 */
462 	max = (q->msk + 1) - 1;
463 	return !!atomic_add_unless(&q->count, 1, max);
464 }
465 
466 /*
467  * Un-account an interrupt for a target CPU. We don't directly
468  * decrement q->count since the interrupt might still be present
469  * in the queue.
470  *
471  * Instead increment a separate counter "pending_count" which
472  * will be substracted from "count" later when that CPU observes
473  * the queue to be empty.
474  */
475 static void xive_dec_target_count(int cpu)
476 {
477 	struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
478 	struct xive_q *q = &xc->queue[xive_irq_priority];
479 
480 	if (WARN_ON(cpu < 0 || !xc)) {
481 		pr_err("%s: cpu=%d xc=%p\n", __func__, cpu, xc);
482 		return;
483 	}
484 
485 	/*
486 	 * We increment the "pending count" which will be used
487 	 * to decrement the target queue count whenever it's next
488 	 * processed and found empty. This ensure that we don't
489 	 * decrement while we still have the interrupt there
490 	 * occupying a slot.
491 	 */
492 	atomic_inc(&q->pending_count);
493 }
494 
495 /* Find a tentative CPU target in a CPU mask */
496 static int xive_find_target_in_mask(const struct cpumask *mask,
497 				    unsigned int fuzz)
498 {
499 	int cpu, first, num, i;
500 
501 	/* Pick up a starting point CPU in the mask based on  fuzz */
502 	num = min_t(int, cpumask_weight(mask), nr_cpu_ids);
503 	first = fuzz % num;
504 
505 	/* Locate it */
506 	cpu = cpumask_first(mask);
507 	for (i = 0; i < first && cpu < nr_cpu_ids; i++)
508 		cpu = cpumask_next(cpu, mask);
509 
510 	/* Sanity check */
511 	if (WARN_ON(cpu >= nr_cpu_ids))
512 		cpu = cpumask_first(cpu_online_mask);
513 
514 	/* Remember first one to handle wrap-around */
515 	first = cpu;
516 
517 	/*
518 	 * Now go through the entire mask until we find a valid
519 	 * target.
520 	 */
521 	do {
522 		/*
523 		 * We re-check online as the fallback case passes us
524 		 * an untested affinity mask
525 		 */
526 		if (cpu_online(cpu) && xive_try_pick_target(cpu))
527 			return cpu;
528 		cpu = cpumask_next(cpu, mask);
529 		/* Wrap around */
530 		if (cpu >= nr_cpu_ids)
531 			cpu = cpumask_first(mask);
532 	} while (cpu != first);
533 
534 	return -1;
535 }
536 
537 /*
538  * Pick a target CPU for an interrupt. This is done at
539  * startup or if the affinity is changed in a way that
540  * invalidates the current target.
541  */
542 static int xive_pick_irq_target(struct irq_data *d,
543 				const struct cpumask *affinity)
544 {
545 	static unsigned int fuzz;
546 	struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
547 	cpumask_var_t mask;
548 	int cpu = -1;
549 
550 	/*
551 	 * If we have chip IDs, first we try to build a mask of
552 	 * CPUs matching the CPU and find a target in there
553 	 */
554 	if (xd->src_chip != XIVE_INVALID_CHIP_ID &&
555 		zalloc_cpumask_var(&mask, GFP_ATOMIC)) {
556 		/* Build a mask of matching chip IDs */
557 		for_each_cpu_and(cpu, affinity, cpu_online_mask) {
558 			struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
559 			if (xc->chip_id == xd->src_chip)
560 				cpumask_set_cpu(cpu, mask);
561 		}
562 		/* Try to find a target */
563 		if (cpumask_empty(mask))
564 			cpu = -1;
565 		else
566 			cpu = xive_find_target_in_mask(mask, fuzz++);
567 		free_cpumask_var(mask);
568 		if (cpu >= 0)
569 			return cpu;
570 		fuzz--;
571 	}
572 
573 	/* No chip IDs, fallback to using the affinity mask */
574 	return xive_find_target_in_mask(affinity, fuzz++);
575 }
576 
577 static unsigned int xive_irq_startup(struct irq_data *d)
578 {
579 	struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
580 	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
581 	int target, rc;
582 
583 	xd->saved_p = false;
584 	xd->stale_p = false;
585 	pr_devel("xive_irq_startup: irq %d [0x%x] data @%p\n",
586 		 d->irq, hw_irq, d);
587 
588 #ifdef CONFIG_PCI_MSI
589 	/*
590 	 * The generic MSI code returns with the interrupt disabled on the
591 	 * card, using the MSI mask bits. Firmware doesn't appear to unmask
592 	 * at that level, so we do it here by hand.
593 	 */
594 	if (irq_data_get_msi_desc(d))
595 		pci_msi_unmask_irq(d);
596 #endif
597 
598 	/* Pick a target */
599 	target = xive_pick_irq_target(d, irq_data_get_affinity_mask(d));
600 	if (target == XIVE_INVALID_TARGET) {
601 		/* Try again breaking affinity */
602 		target = xive_pick_irq_target(d, cpu_online_mask);
603 		if (target == XIVE_INVALID_TARGET)
604 			return -ENXIO;
605 		pr_warn("irq %d started with broken affinity\n", d->irq);
606 	}
607 
608 	/* Sanity check */
609 	if (WARN_ON(target == XIVE_INVALID_TARGET ||
610 		    target >= nr_cpu_ids))
611 		target = smp_processor_id();
612 
613 	xd->target = target;
614 
615 	/*
616 	 * Configure the logical number to be the Linux IRQ number
617 	 * and set the target queue
618 	 */
619 	rc = xive_ops->configure_irq(hw_irq,
620 				     get_hard_smp_processor_id(target),
621 				     xive_irq_priority, d->irq);
622 	if (rc)
623 		return rc;
624 
625 	/* Unmask the ESB */
626 	xive_do_source_set_mask(xd, false);
627 
628 	return 0;
629 }
630 
631 /* called with irq descriptor lock held */
632 static void xive_irq_shutdown(struct irq_data *d)
633 {
634 	struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
635 	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
636 
637 	pr_devel("xive_irq_shutdown: irq %d [0x%x] data @%p\n",
638 		 d->irq, hw_irq, d);
639 
640 	if (WARN_ON(xd->target == XIVE_INVALID_TARGET))
641 		return;
642 
643 	/* Mask the interrupt at the source */
644 	xive_do_source_set_mask(xd, true);
645 
646 	/*
647 	 * Mask the interrupt in HW in the IVT/EAS and set the number
648 	 * to be the "bad" IRQ number
649 	 */
650 	xive_ops->configure_irq(hw_irq,
651 				get_hard_smp_processor_id(xd->target),
652 				0xff, XIVE_BAD_IRQ);
653 
654 	xive_dec_target_count(xd->target);
655 	xd->target = XIVE_INVALID_TARGET;
656 }
657 
658 static void xive_irq_unmask(struct irq_data *d)
659 {
660 	struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
661 
662 	pr_devel("xive_irq_unmask: irq %d data @%p\n", d->irq, xd);
663 
664 	xive_do_source_set_mask(xd, false);
665 }
666 
667 static void xive_irq_mask(struct irq_data *d)
668 {
669 	struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
670 
671 	pr_devel("xive_irq_mask: irq %d data @%p\n", d->irq, xd);
672 
673 	xive_do_source_set_mask(xd, true);
674 }
675 
676 static int xive_irq_set_affinity(struct irq_data *d,
677 				 const struct cpumask *cpumask,
678 				 bool force)
679 {
680 	struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
681 	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
682 	u32 target, old_target;
683 	int rc = 0;
684 
685 	pr_devel("xive_irq_set_affinity: irq %d\n", d->irq);
686 
687 	/* Is this valid ? */
688 	if (cpumask_any_and(cpumask, cpu_online_mask) >= nr_cpu_ids)
689 		return -EINVAL;
690 
691 	/* Don't do anything if the interrupt isn't started */
692 	if (!irqd_is_started(d))
693 		return IRQ_SET_MASK_OK;
694 
695 	/*
696 	 * If existing target is already in the new mask, and is
697 	 * online then do nothing.
698 	 */
699 	if (xd->target != XIVE_INVALID_TARGET &&
700 	    cpu_online(xd->target) &&
701 	    cpumask_test_cpu(xd->target, cpumask))
702 		return IRQ_SET_MASK_OK;
703 
704 	/* Pick a new target */
705 	target = xive_pick_irq_target(d, cpumask);
706 
707 	/* No target found */
708 	if (target == XIVE_INVALID_TARGET)
709 		return -ENXIO;
710 
711 	/* Sanity check */
712 	if (WARN_ON(target >= nr_cpu_ids))
713 		target = smp_processor_id();
714 
715 	old_target = xd->target;
716 
717 	/*
718 	 * Only configure the irq if it's not currently passed-through to
719 	 * a KVM guest
720 	 */
721 	if (!irqd_is_forwarded_to_vcpu(d))
722 		rc = xive_ops->configure_irq(hw_irq,
723 					     get_hard_smp_processor_id(target),
724 					     xive_irq_priority, d->irq);
725 	if (rc < 0) {
726 		pr_err("Error %d reconfiguring irq %d\n", rc, d->irq);
727 		return rc;
728 	}
729 
730 	pr_devel("  target: 0x%x\n", target);
731 	xd->target = target;
732 
733 	/* Give up previous target */
734 	if (old_target != XIVE_INVALID_TARGET)
735 	    xive_dec_target_count(old_target);
736 
737 	return IRQ_SET_MASK_OK;
738 }
739 
740 static int xive_irq_set_type(struct irq_data *d, unsigned int flow_type)
741 {
742 	struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
743 
744 	/*
745 	 * We only support these. This has really no effect other than setting
746 	 * the corresponding descriptor bits mind you but those will in turn
747 	 * affect the resend function when re-enabling an edge interrupt.
748 	 *
749 	 * Set set the default to edge as explained in map().
750 	 */
751 	if (flow_type == IRQ_TYPE_DEFAULT || flow_type == IRQ_TYPE_NONE)
752 		flow_type = IRQ_TYPE_EDGE_RISING;
753 
754 	if (flow_type != IRQ_TYPE_EDGE_RISING &&
755 	    flow_type != IRQ_TYPE_LEVEL_LOW)
756 		return -EINVAL;
757 
758 	irqd_set_trigger_type(d, flow_type);
759 
760 	/*
761 	 * Double check it matches what the FW thinks
762 	 *
763 	 * NOTE: We don't know yet if the PAPR interface will provide
764 	 * the LSI vs MSI information apart from the device-tree so
765 	 * this check might have to move into an optional backend call
766 	 * that is specific to the native backend
767 	 */
768 	if ((flow_type == IRQ_TYPE_LEVEL_LOW) !=
769 	    !!(xd->flags & XIVE_IRQ_FLAG_LSI)) {
770 		pr_warn("Interrupt %d (HW 0x%x) type mismatch, Linux says %s, FW says %s\n",
771 			d->irq, (u32)irqd_to_hwirq(d),
772 			(flow_type == IRQ_TYPE_LEVEL_LOW) ? "Level" : "Edge",
773 			(xd->flags & XIVE_IRQ_FLAG_LSI) ? "Level" : "Edge");
774 	}
775 
776 	return IRQ_SET_MASK_OK_NOCOPY;
777 }
778 
779 static int xive_irq_retrigger(struct irq_data *d)
780 {
781 	struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
782 
783 	/* This should be only for MSIs */
784 	if (WARN_ON(xd->flags & XIVE_IRQ_FLAG_LSI))
785 		return 0;
786 
787 	/*
788 	 * To perform a retrigger, we first set the PQ bits to
789 	 * 11, then perform an EOI.
790 	 */
791 	xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
792 	xive_do_source_eoi(xd);
793 
794 	return 1;
795 }
796 
797 /*
798  * Caller holds the irq descriptor lock, so this won't be called
799  * concurrently with xive_get_irqchip_state on the same interrupt.
800  */
801 static int xive_irq_set_vcpu_affinity(struct irq_data *d, void *state)
802 {
803 	struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
804 	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
805 	int rc;
806 	u8 pq;
807 
808 	/*
809 	 * This is called by KVM with state non-NULL for enabling
810 	 * pass-through or NULL for disabling it
811 	 */
812 	if (state) {
813 		irqd_set_forwarded_to_vcpu(d);
814 
815 		/* Set it to PQ=10 state to prevent further sends */
816 		pq = xive_esb_read(xd, XIVE_ESB_SET_PQ_10);
817 		if (!xd->stale_p) {
818 			xd->saved_p = !!(pq & XIVE_ESB_VAL_P);
819 			xd->stale_p = !xd->saved_p;
820 		}
821 
822 		/* No target ? nothing to do */
823 		if (xd->target == XIVE_INVALID_TARGET) {
824 			/*
825 			 * An untargetted interrupt should have been
826 			 * also masked at the source
827 			 */
828 			WARN_ON(xd->saved_p);
829 
830 			return 0;
831 		}
832 
833 		/*
834 		 * If P was set, adjust state to PQ=11 to indicate
835 		 * that a resend is needed for the interrupt to reach
836 		 * the guest. Also remember the value of P.
837 		 *
838 		 * This also tells us that it's in flight to a host queue
839 		 * or has already been fetched but hasn't been EOIed yet
840 		 * by the host. This it's potentially using up a host
841 		 * queue slot. This is important to know because as long
842 		 * as this is the case, we must not hard-unmask it when
843 		 * "returning" that interrupt to the host.
844 		 *
845 		 * This saved_p is cleared by the host EOI, when we know
846 		 * for sure the queue slot is no longer in use.
847 		 */
848 		if (xd->saved_p) {
849 			xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
850 
851 			/*
852 			 * Sync the XIVE source HW to ensure the interrupt
853 			 * has gone through the EAS before we change its
854 			 * target to the guest. That should guarantee us
855 			 * that we *will* eventually get an EOI for it on
856 			 * the host. Otherwise there would be a small window
857 			 * for P to be seen here but the interrupt going
858 			 * to the guest queue.
859 			 */
860 			if (xive_ops->sync_source)
861 				xive_ops->sync_source(hw_irq);
862 		}
863 	} else {
864 		irqd_clr_forwarded_to_vcpu(d);
865 
866 		/* No host target ? hard mask and return */
867 		if (xd->target == XIVE_INVALID_TARGET) {
868 			xive_do_source_set_mask(xd, true);
869 			return 0;
870 		}
871 
872 		/*
873 		 * Sync the XIVE source HW to ensure the interrupt
874 		 * has gone through the EAS before we change its
875 		 * target to the host.
876 		 */
877 		if (xive_ops->sync_source)
878 			xive_ops->sync_source(hw_irq);
879 
880 		/*
881 		 * By convention we are called with the interrupt in
882 		 * a PQ=10 or PQ=11 state, ie, it won't fire and will
883 		 * have latched in Q whether there's a pending HW
884 		 * interrupt or not.
885 		 *
886 		 * First reconfigure the target.
887 		 */
888 		rc = xive_ops->configure_irq(hw_irq,
889 					     get_hard_smp_processor_id(xd->target),
890 					     xive_irq_priority, d->irq);
891 		if (rc)
892 			return rc;
893 
894 		/*
895 		 * Then if saved_p is not set, effectively re-enable the
896 		 * interrupt with an EOI. If it is set, we know there is
897 		 * still a message in a host queue somewhere that will be
898 		 * EOId eventually.
899 		 *
900 		 * Note: We don't check irqd_irq_disabled(). Effectively,
901 		 * we *will* let the irq get through even if masked if the
902 		 * HW is still firing it in order to deal with the whole
903 		 * saved_p business properly. If the interrupt triggers
904 		 * while masked, the generic code will re-mask it anyway.
905 		 */
906 		if (!xd->saved_p)
907 			xive_do_source_eoi(xd);
908 
909 	}
910 	return 0;
911 }
912 
913 /* Called with irq descriptor lock held. */
914 static int xive_get_irqchip_state(struct irq_data *data,
915 				  enum irqchip_irq_state which, bool *state)
916 {
917 	struct xive_irq_data *xd = irq_data_get_irq_handler_data(data);
918 	u8 pq;
919 
920 	switch (which) {
921 	case IRQCHIP_STATE_ACTIVE:
922 		pq = xive_esb_read(xd, XIVE_ESB_GET);
923 
924 		/*
925 		 * The esb value being all 1's means we couldn't get
926 		 * the PQ state of the interrupt through mmio. It may
927 		 * happen, for example when querying a PHB interrupt
928 		 * while the PHB is in an error state. We consider the
929 		 * interrupt to be inactive in that case.
930 		 */
931 		*state = (pq != XIVE_ESB_INVALID) && !xd->stale_p &&
932 			(xd->saved_p || !!(pq & XIVE_ESB_VAL_P));
933 		return 0;
934 	default:
935 		return -EINVAL;
936 	}
937 }
938 
939 static struct irq_chip xive_irq_chip = {
940 	.name = "XIVE-IRQ",
941 	.irq_startup = xive_irq_startup,
942 	.irq_shutdown = xive_irq_shutdown,
943 	.irq_eoi = xive_irq_eoi,
944 	.irq_mask = xive_irq_mask,
945 	.irq_unmask = xive_irq_unmask,
946 	.irq_set_affinity = xive_irq_set_affinity,
947 	.irq_set_type = xive_irq_set_type,
948 	.irq_retrigger = xive_irq_retrigger,
949 	.irq_set_vcpu_affinity = xive_irq_set_vcpu_affinity,
950 	.irq_get_irqchip_state = xive_get_irqchip_state,
951 };
952 
953 bool is_xive_irq(struct irq_chip *chip)
954 {
955 	return chip == &xive_irq_chip;
956 }
957 EXPORT_SYMBOL_GPL(is_xive_irq);
958 
959 void xive_cleanup_irq_data(struct xive_irq_data *xd)
960 {
961 	if (xd->eoi_mmio) {
962 		unmap_kernel_range((unsigned long)xd->eoi_mmio,
963 				   1u << xd->esb_shift);
964 		iounmap(xd->eoi_mmio);
965 		if (xd->eoi_mmio == xd->trig_mmio)
966 			xd->trig_mmio = NULL;
967 		xd->eoi_mmio = NULL;
968 	}
969 	if (xd->trig_mmio) {
970 		unmap_kernel_range((unsigned long)xd->trig_mmio,
971 				   1u << xd->esb_shift);
972 		iounmap(xd->trig_mmio);
973 		xd->trig_mmio = NULL;
974 	}
975 }
976 EXPORT_SYMBOL_GPL(xive_cleanup_irq_data);
977 
978 static int xive_irq_alloc_data(unsigned int virq, irq_hw_number_t hw)
979 {
980 	struct xive_irq_data *xd;
981 	int rc;
982 
983 	xd = kzalloc(sizeof(struct xive_irq_data), GFP_KERNEL);
984 	if (!xd)
985 		return -ENOMEM;
986 	rc = xive_ops->populate_irq_data(hw, xd);
987 	if (rc) {
988 		kfree(xd);
989 		return rc;
990 	}
991 	xd->target = XIVE_INVALID_TARGET;
992 	irq_set_handler_data(virq, xd);
993 
994 	/*
995 	 * Turn OFF by default the interrupt being mapped. A side
996 	 * effect of this check is the mapping the ESB page of the
997 	 * interrupt in the Linux address space. This prevents page
998 	 * fault issues in the crash handler which masks all
999 	 * interrupts.
1000 	 */
1001 	xive_esb_read(xd, XIVE_ESB_SET_PQ_01);
1002 
1003 	return 0;
1004 }
1005 
1006 static void xive_irq_free_data(unsigned int virq)
1007 {
1008 	struct xive_irq_data *xd = irq_get_handler_data(virq);
1009 
1010 	if (!xd)
1011 		return;
1012 	irq_set_handler_data(virq, NULL);
1013 	xive_cleanup_irq_data(xd);
1014 	kfree(xd);
1015 }
1016 
1017 #ifdef CONFIG_SMP
1018 
1019 static void xive_cause_ipi(int cpu)
1020 {
1021 	struct xive_cpu *xc;
1022 	struct xive_irq_data *xd;
1023 
1024 	xc = per_cpu(xive_cpu, cpu);
1025 
1026 	DBG_VERBOSE("IPI CPU %d -> %d (HW IRQ 0x%x)\n",
1027 		    smp_processor_id(), cpu, xc->hw_ipi);
1028 
1029 	xd = &xc->ipi_data;
1030 	if (WARN_ON(!xd->trig_mmio))
1031 		return;
1032 	out_be64(xd->trig_mmio, 0);
1033 }
1034 
1035 static irqreturn_t xive_muxed_ipi_action(int irq, void *dev_id)
1036 {
1037 	return smp_ipi_demux();
1038 }
1039 
1040 static void xive_ipi_eoi(struct irq_data *d)
1041 {
1042 	struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1043 
1044 	/* Handle possible race with unplug and drop stale IPIs */
1045 	if (!xc)
1046 		return;
1047 
1048 	DBG_VERBOSE("IPI eoi: irq=%d [0x%lx] (HW IRQ 0x%x) pending=%02x\n",
1049 		    d->irq, irqd_to_hwirq(d), xc->hw_ipi, xc->pending_prio);
1050 
1051 	xive_do_source_eoi(&xc->ipi_data);
1052 	xive_do_queue_eoi(xc);
1053 }
1054 
1055 static void xive_ipi_do_nothing(struct irq_data *d)
1056 {
1057 	/*
1058 	 * Nothing to do, we never mask/unmask IPIs, but the callback
1059 	 * has to exist for the struct irq_chip.
1060 	 */
1061 }
1062 
1063 static struct irq_chip xive_ipi_chip = {
1064 	.name = "XIVE-IPI",
1065 	.irq_eoi = xive_ipi_eoi,
1066 	.irq_mask = xive_ipi_do_nothing,
1067 	.irq_unmask = xive_ipi_do_nothing,
1068 };
1069 
1070 static void __init xive_request_ipi(void)
1071 {
1072 	unsigned int virq;
1073 
1074 	/*
1075 	 * Initialization failed, move on, we might manage to
1076 	 * reach the point where we display our errors before
1077 	 * the system falls appart
1078 	 */
1079 	if (!xive_irq_domain)
1080 		return;
1081 
1082 	/* Initialize it */
1083 	virq = irq_create_mapping(xive_irq_domain, XIVE_IPI_HW_IRQ);
1084 	xive_ipi_irq = virq;
1085 
1086 	WARN_ON(request_irq(virq, xive_muxed_ipi_action,
1087 			    IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL));
1088 }
1089 
1090 static int xive_setup_cpu_ipi(unsigned int cpu)
1091 {
1092 	struct xive_cpu *xc;
1093 	int rc;
1094 
1095 	pr_debug("Setting up IPI for CPU %d\n", cpu);
1096 
1097 	xc = per_cpu(xive_cpu, cpu);
1098 
1099 	/* Check if we are already setup */
1100 	if (xc->hw_ipi != XIVE_BAD_IRQ)
1101 		return 0;
1102 
1103 	/* Grab an IPI from the backend, this will populate xc->hw_ipi */
1104 	if (xive_ops->get_ipi(cpu, xc))
1105 		return -EIO;
1106 
1107 	/*
1108 	 * Populate the IRQ data in the xive_cpu structure and
1109 	 * configure the HW / enable the IPIs.
1110 	 */
1111 	rc = xive_ops->populate_irq_data(xc->hw_ipi, &xc->ipi_data);
1112 	if (rc) {
1113 		pr_err("Failed to populate IPI data on CPU %d\n", cpu);
1114 		return -EIO;
1115 	}
1116 	rc = xive_ops->configure_irq(xc->hw_ipi,
1117 				     get_hard_smp_processor_id(cpu),
1118 				     xive_irq_priority, xive_ipi_irq);
1119 	if (rc) {
1120 		pr_err("Failed to map IPI CPU %d\n", cpu);
1121 		return -EIO;
1122 	}
1123 	pr_devel("CPU %d HW IPI %x, virq %d, trig_mmio=%p\n", cpu,
1124 	    xc->hw_ipi, xive_ipi_irq, xc->ipi_data.trig_mmio);
1125 
1126 	/* Unmask it */
1127 	xive_do_source_set_mask(&xc->ipi_data, false);
1128 
1129 	return 0;
1130 }
1131 
1132 static void xive_cleanup_cpu_ipi(unsigned int cpu, struct xive_cpu *xc)
1133 {
1134 	/* Disable the IPI and free the IRQ data */
1135 
1136 	/* Already cleaned up ? */
1137 	if (xc->hw_ipi == XIVE_BAD_IRQ)
1138 		return;
1139 
1140 	/* Mask the IPI */
1141 	xive_do_source_set_mask(&xc->ipi_data, true);
1142 
1143 	/*
1144 	 * Note: We don't call xive_cleanup_irq_data() to free
1145 	 * the mappings as this is called from an IPI on kexec
1146 	 * which is not a safe environment to call iounmap()
1147 	 */
1148 
1149 	/* Deconfigure/mask in the backend */
1150 	xive_ops->configure_irq(xc->hw_ipi, hard_smp_processor_id(),
1151 				0xff, xive_ipi_irq);
1152 
1153 	/* Free the IPIs in the backend */
1154 	xive_ops->put_ipi(cpu, xc);
1155 }
1156 
1157 void __init xive_smp_probe(void)
1158 {
1159 	smp_ops->cause_ipi = xive_cause_ipi;
1160 
1161 	/* Register the IPI */
1162 	xive_request_ipi();
1163 
1164 	/* Allocate and setup IPI for the boot CPU */
1165 	xive_setup_cpu_ipi(smp_processor_id());
1166 }
1167 
1168 #endif /* CONFIG_SMP */
1169 
1170 static int xive_irq_domain_map(struct irq_domain *h, unsigned int virq,
1171 			       irq_hw_number_t hw)
1172 {
1173 	int rc;
1174 
1175 	/*
1176 	 * Mark interrupts as edge sensitive by default so that resend
1177 	 * actually works. Will fix that up below if needed.
1178 	 */
1179 	irq_clear_status_flags(virq, IRQ_LEVEL);
1180 
1181 #ifdef CONFIG_SMP
1182 	/* IPIs are special and come up with HW number 0 */
1183 	if (hw == XIVE_IPI_HW_IRQ) {
1184 		/*
1185 		 * IPIs are marked per-cpu. We use separate HW interrupts under
1186 		 * the hood but associated with the same "linux" interrupt
1187 		 */
1188 		irq_set_chip_and_handler(virq, &xive_ipi_chip,
1189 					 handle_percpu_irq);
1190 		return 0;
1191 	}
1192 #endif
1193 
1194 	rc = xive_irq_alloc_data(virq, hw);
1195 	if (rc)
1196 		return rc;
1197 
1198 	irq_set_chip_and_handler(virq, &xive_irq_chip, handle_fasteoi_irq);
1199 
1200 	return 0;
1201 }
1202 
1203 static void xive_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
1204 {
1205 	struct irq_data *data = irq_get_irq_data(virq);
1206 	unsigned int hw_irq;
1207 
1208 	/* XXX Assign BAD number */
1209 	if (!data)
1210 		return;
1211 	hw_irq = (unsigned int)irqd_to_hwirq(data);
1212 	if (hw_irq != XIVE_IPI_HW_IRQ)
1213 		xive_irq_free_data(virq);
1214 }
1215 
1216 static int xive_irq_domain_xlate(struct irq_domain *h, struct device_node *ct,
1217 				 const u32 *intspec, unsigned int intsize,
1218 				 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1219 
1220 {
1221 	*out_hwirq = intspec[0];
1222 
1223 	/*
1224 	 * If intsize is at least 2, we look for the type in the second cell,
1225 	 * we assume the LSB indicates a level interrupt.
1226 	 */
1227 	if (intsize > 1) {
1228 		if (intspec[1] & 1)
1229 			*out_flags = IRQ_TYPE_LEVEL_LOW;
1230 		else
1231 			*out_flags = IRQ_TYPE_EDGE_RISING;
1232 	} else
1233 		*out_flags = IRQ_TYPE_LEVEL_LOW;
1234 
1235 	return 0;
1236 }
1237 
1238 static int xive_irq_domain_match(struct irq_domain *h, struct device_node *node,
1239 				 enum irq_domain_bus_token bus_token)
1240 {
1241 	return xive_ops->match(node);
1242 }
1243 
1244 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS
1245 static const char * const esb_names[] = { "RESET", "OFF", "PENDING", "QUEUED" };
1246 
1247 static const struct {
1248 	u64  mask;
1249 	char *name;
1250 } xive_irq_flags[] = {
1251 	{ XIVE_IRQ_FLAG_STORE_EOI, "STORE_EOI" },
1252 	{ XIVE_IRQ_FLAG_LSI,       "LSI"       },
1253 	{ XIVE_IRQ_FLAG_H_INT_ESB, "H_INT_ESB" },
1254 	{ XIVE_IRQ_FLAG_NO_EOI,    "NO_EOI"    },
1255 };
1256 
1257 static void xive_irq_domain_debug_show(struct seq_file *m, struct irq_domain *d,
1258 				       struct irq_data *irqd, int ind)
1259 {
1260 	struct xive_irq_data *xd;
1261 	u64 val;
1262 	int i;
1263 
1264 	/* No IRQ domain level information. To be done */
1265 	if (!irqd)
1266 		return;
1267 
1268 	if (!is_xive_irq(irq_data_get_irq_chip(irqd)))
1269 		return;
1270 
1271 	seq_printf(m, "%*sXIVE:\n", ind, "");
1272 	ind++;
1273 
1274 	xd = irq_data_get_irq_handler_data(irqd);
1275 	if (!xd) {
1276 		seq_printf(m, "%*snot assigned\n", ind, "");
1277 		return;
1278 	}
1279 
1280 	val = xive_esb_read(xd, XIVE_ESB_GET);
1281 	seq_printf(m, "%*sESB:      %s\n", ind, "", esb_names[val & 0x3]);
1282 	seq_printf(m, "%*sPstate:   %s %s\n", ind, "", xd->stale_p ? "stale" : "",
1283 		   xd->saved_p ? "saved" : "");
1284 	seq_printf(m, "%*sTarget:   %d\n", ind, "", xd->target);
1285 	seq_printf(m, "%*sChip:     %d\n", ind, "", xd->src_chip);
1286 	seq_printf(m, "%*sTrigger:  0x%016llx\n", ind, "", xd->trig_page);
1287 	seq_printf(m, "%*sEOI:      0x%016llx\n", ind, "", xd->eoi_page);
1288 	seq_printf(m, "%*sFlags:    0x%llx\n", ind, "", xd->flags);
1289 	for (i = 0; i < ARRAY_SIZE(xive_irq_flags); i++) {
1290 		if (xd->flags & xive_irq_flags[i].mask)
1291 			seq_printf(m, "%*s%s\n", ind + 12, "", xive_irq_flags[i].name);
1292 	}
1293 }
1294 #endif
1295 
1296 static const struct irq_domain_ops xive_irq_domain_ops = {
1297 	.match = xive_irq_domain_match,
1298 	.map = xive_irq_domain_map,
1299 	.unmap = xive_irq_domain_unmap,
1300 	.xlate = xive_irq_domain_xlate,
1301 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS
1302 	.debug_show = xive_irq_domain_debug_show,
1303 #endif
1304 };
1305 
1306 static void __init xive_init_host(struct device_node *np)
1307 {
1308 	xive_irq_domain = irq_domain_add_nomap(np, XIVE_MAX_IRQ,
1309 					       &xive_irq_domain_ops, NULL);
1310 	if (WARN_ON(xive_irq_domain == NULL))
1311 		return;
1312 	irq_set_default_host(xive_irq_domain);
1313 }
1314 
1315 static void xive_cleanup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)
1316 {
1317 	if (xc->queue[xive_irq_priority].qpage)
1318 		xive_ops->cleanup_queue(cpu, xc, xive_irq_priority);
1319 }
1320 
1321 static int xive_setup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)
1322 {
1323 	int rc = 0;
1324 
1325 	/* We setup 1 queues for now with a 64k page */
1326 	if (!xc->queue[xive_irq_priority].qpage)
1327 		rc = xive_ops->setup_queue(cpu, xc, xive_irq_priority);
1328 
1329 	return rc;
1330 }
1331 
1332 static int xive_prepare_cpu(unsigned int cpu)
1333 {
1334 	struct xive_cpu *xc;
1335 
1336 	xc = per_cpu(xive_cpu, cpu);
1337 	if (!xc) {
1338 		struct device_node *np;
1339 
1340 		xc = kzalloc_node(sizeof(struct xive_cpu),
1341 				  GFP_KERNEL, cpu_to_node(cpu));
1342 		if (!xc)
1343 			return -ENOMEM;
1344 		np = of_get_cpu_node(cpu, NULL);
1345 		if (np)
1346 			xc->chip_id = of_get_ibm_chip_id(np);
1347 		of_node_put(np);
1348 		xc->hw_ipi = XIVE_BAD_IRQ;
1349 
1350 		per_cpu(xive_cpu, cpu) = xc;
1351 	}
1352 
1353 	/* Setup EQs if not already */
1354 	return xive_setup_cpu_queues(cpu, xc);
1355 }
1356 
1357 static void xive_setup_cpu(void)
1358 {
1359 	struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1360 
1361 	/* The backend might have additional things to do */
1362 	if (xive_ops->setup_cpu)
1363 		xive_ops->setup_cpu(smp_processor_id(), xc);
1364 
1365 	/* Set CPPR to 0xff to enable flow of interrupts */
1366 	xc->cppr = 0xff;
1367 	out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);
1368 }
1369 
1370 #ifdef CONFIG_SMP
1371 void xive_smp_setup_cpu(void)
1372 {
1373 	pr_devel("SMP setup CPU %d\n", smp_processor_id());
1374 
1375 	/* This will have already been done on the boot CPU */
1376 	if (smp_processor_id() != boot_cpuid)
1377 		xive_setup_cpu();
1378 
1379 }
1380 
1381 int xive_smp_prepare_cpu(unsigned int cpu)
1382 {
1383 	int rc;
1384 
1385 	/* Allocate per-CPU data and queues */
1386 	rc = xive_prepare_cpu(cpu);
1387 	if (rc)
1388 		return rc;
1389 
1390 	/* Allocate and setup IPI for the new CPU */
1391 	return xive_setup_cpu_ipi(cpu);
1392 }
1393 
1394 #ifdef CONFIG_HOTPLUG_CPU
1395 static void xive_flush_cpu_queue(unsigned int cpu, struct xive_cpu *xc)
1396 {
1397 	u32 irq;
1398 
1399 	/* We assume local irqs are disabled */
1400 	WARN_ON(!irqs_disabled());
1401 
1402 	/* Check what's already in the CPU queue */
1403 	while ((irq = xive_scan_interrupts(xc, false)) != 0) {
1404 		/*
1405 		 * We need to re-route that interrupt to its new destination.
1406 		 * First get and lock the descriptor
1407 		 */
1408 		struct irq_desc *desc = irq_to_desc(irq);
1409 		struct irq_data *d = irq_desc_get_irq_data(desc);
1410 		struct xive_irq_data *xd;
1411 		unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
1412 
1413 		/*
1414 		 * Ignore anything that isn't a XIVE irq and ignore
1415 		 * IPIs, so can just be dropped.
1416 		 */
1417 		if (d->domain != xive_irq_domain || hw_irq == XIVE_IPI_HW_IRQ)
1418 			continue;
1419 
1420 		/*
1421 		 * The IRQ should have already been re-routed, it's just a
1422 		 * stale in the old queue, so re-trigger it in order to make
1423 		 * it reach is new destination.
1424 		 */
1425 #ifdef DEBUG_FLUSH
1426 		pr_info("CPU %d: Got irq %d while offline, re-sending...\n",
1427 			cpu, irq);
1428 #endif
1429 		raw_spin_lock(&desc->lock);
1430 		xd = irq_desc_get_handler_data(desc);
1431 
1432 		/*
1433 		 * Clear saved_p to indicate that it's no longer pending
1434 		 */
1435 		xd->saved_p = false;
1436 
1437 		/*
1438 		 * For LSIs, we EOI, this will cause a resend if it's
1439 		 * still asserted. Otherwise do an MSI retrigger.
1440 		 */
1441 		if (xd->flags & XIVE_IRQ_FLAG_LSI)
1442 			xive_do_source_eoi(xd);
1443 		else
1444 			xive_irq_retrigger(d);
1445 
1446 		raw_spin_unlock(&desc->lock);
1447 	}
1448 }
1449 
1450 void xive_smp_disable_cpu(void)
1451 {
1452 	struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1453 	unsigned int cpu = smp_processor_id();
1454 
1455 	/* Migrate interrupts away from the CPU */
1456 	irq_migrate_all_off_this_cpu();
1457 
1458 	/* Set CPPR to 0 to disable flow of interrupts */
1459 	xc->cppr = 0;
1460 	out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1461 
1462 	/* Flush everything still in the queue */
1463 	xive_flush_cpu_queue(cpu, xc);
1464 
1465 	/* Re-enable CPPR  */
1466 	xc->cppr = 0xff;
1467 	out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);
1468 }
1469 
1470 void xive_flush_interrupt(void)
1471 {
1472 	struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1473 	unsigned int cpu = smp_processor_id();
1474 
1475 	/* Called if an interrupt occurs while the CPU is hot unplugged */
1476 	xive_flush_cpu_queue(cpu, xc);
1477 }
1478 
1479 #endif /* CONFIG_HOTPLUG_CPU */
1480 
1481 #endif /* CONFIG_SMP */
1482 
1483 void xive_teardown_cpu(void)
1484 {
1485 	struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1486 	unsigned int cpu = smp_processor_id();
1487 
1488 	/* Set CPPR to 0 to disable flow of interrupts */
1489 	xc->cppr = 0;
1490 	out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1491 
1492 	if (xive_ops->teardown_cpu)
1493 		xive_ops->teardown_cpu(cpu, xc);
1494 
1495 #ifdef CONFIG_SMP
1496 	/* Get rid of IPI */
1497 	xive_cleanup_cpu_ipi(cpu, xc);
1498 #endif
1499 
1500 	/* Disable and free the queues */
1501 	xive_cleanup_cpu_queues(cpu, xc);
1502 }
1503 
1504 void xive_shutdown(void)
1505 {
1506 	xive_ops->shutdown();
1507 }
1508 
1509 bool __init xive_core_init(struct device_node *np, const struct xive_ops *ops,
1510 			   void __iomem *area, u32 offset, u8 max_prio)
1511 {
1512 	xive_tima = area;
1513 	xive_tima_offset = offset;
1514 	xive_ops = ops;
1515 	xive_irq_priority = max_prio;
1516 
1517 	ppc_md.get_irq = xive_get_irq;
1518 	__xive_enabled = true;
1519 
1520 	pr_devel("Initializing host..\n");
1521 	xive_init_host(np);
1522 
1523 	pr_devel("Initializing boot CPU..\n");
1524 
1525 	/* Allocate per-CPU data and queues */
1526 	xive_prepare_cpu(smp_processor_id());
1527 
1528 	/* Get ready for interrupts */
1529 	xive_setup_cpu();
1530 
1531 	pr_info("Interrupt handling initialized with %s backend\n",
1532 		xive_ops->name);
1533 	pr_info("Using priority %d for all interrupts\n", max_prio);
1534 
1535 	return true;
1536 }
1537 
1538 __be32 *xive_queue_page_alloc(unsigned int cpu, u32 queue_shift)
1539 {
1540 	unsigned int alloc_order;
1541 	struct page *pages;
1542 	__be32 *qpage;
1543 
1544 	alloc_order = xive_alloc_order(queue_shift);
1545 	pages = alloc_pages_node(cpu_to_node(cpu), GFP_KERNEL, alloc_order);
1546 	if (!pages)
1547 		return ERR_PTR(-ENOMEM);
1548 	qpage = (__be32 *)page_address(pages);
1549 	memset(qpage, 0, 1 << queue_shift);
1550 
1551 	return qpage;
1552 }
1553 
1554 static int __init xive_off(char *arg)
1555 {
1556 	xive_cmdline_disabled = true;
1557 	return 0;
1558 }
1559 __setup("xive=off", xive_off);
1560 
1561 static void xive_debug_show_cpu(struct seq_file *m, int cpu)
1562 {
1563 	struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
1564 
1565 	seq_printf(m, "CPU %d:", cpu);
1566 	if (xc) {
1567 		seq_printf(m, "pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr);
1568 
1569 #ifdef CONFIG_SMP
1570 		{
1571 			u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET);
1572 
1573 			seq_printf(m, "IPI=0x%08x PQ=%c%c ", xc->hw_ipi,
1574 				   val & XIVE_ESB_VAL_P ? 'P' : '-',
1575 				   val & XIVE_ESB_VAL_Q ? 'Q' : '-');
1576 		}
1577 #endif
1578 		{
1579 			struct xive_q *q = &xc->queue[xive_irq_priority];
1580 			u32 i0, i1, idx;
1581 
1582 			if (q->qpage) {
1583 				idx = q->idx;
1584 				i0 = be32_to_cpup(q->qpage + idx);
1585 				idx = (idx + 1) & q->msk;
1586 				i1 = be32_to_cpup(q->qpage + idx);
1587 				seq_printf(m, "EQ idx=%d T=%d %08x %08x ...",
1588 					   q->idx, q->toggle, i0, i1);
1589 			}
1590 		}
1591 	}
1592 	seq_puts(m, "\n");
1593 }
1594 
1595 static void xive_debug_show_irq(struct seq_file *m, u32 hw_irq, struct irq_data *d)
1596 {
1597 	struct irq_chip *chip = irq_data_get_irq_chip(d);
1598 	int rc;
1599 	u32 target;
1600 	u8 prio;
1601 	u32 lirq;
1602 
1603 	if (!is_xive_irq(chip))
1604 		return;
1605 
1606 	rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq);
1607 	if (rc) {
1608 		seq_printf(m, "IRQ 0x%08x : no config rc=%d\n", hw_irq, rc);
1609 		return;
1610 	}
1611 
1612 	seq_printf(m, "IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ",
1613 		   hw_irq, target, prio, lirq);
1614 
1615 	if (d) {
1616 		struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
1617 		u64 val = xive_esb_read(xd, XIVE_ESB_GET);
1618 
1619 		seq_printf(m, "flags=%c%c%c PQ=%c%c",
1620 			   xd->flags & XIVE_IRQ_FLAG_STORE_EOI ? 'S' : ' ',
1621 			   xd->flags & XIVE_IRQ_FLAG_LSI ? 'L' : ' ',
1622 			   xd->flags & XIVE_IRQ_FLAG_H_INT_ESB ? 'H' : ' ',
1623 			   val & XIVE_ESB_VAL_P ? 'P' : '-',
1624 			   val & XIVE_ESB_VAL_Q ? 'Q' : '-');
1625 	}
1626 	seq_puts(m, "\n");
1627 }
1628 
1629 static int xive_core_debug_show(struct seq_file *m, void *private)
1630 {
1631 	unsigned int i;
1632 	struct irq_desc *desc;
1633 	int cpu;
1634 
1635 	if (xive_ops->debug_show)
1636 		xive_ops->debug_show(m, private);
1637 
1638 	for_each_possible_cpu(cpu)
1639 		xive_debug_show_cpu(m, cpu);
1640 
1641 	for_each_irq_desc(i, desc) {
1642 		struct irq_data *d = irq_desc_get_irq_data(desc);
1643 		unsigned int hw_irq;
1644 
1645 		if (!d)
1646 			continue;
1647 
1648 		hw_irq = (unsigned int)irqd_to_hwirq(d);
1649 
1650 		/* IPIs are special (HW number 0) */
1651 		if (hw_irq != XIVE_IPI_HW_IRQ)
1652 			xive_debug_show_irq(m, hw_irq, d);
1653 	}
1654 	return 0;
1655 }
1656 DEFINE_SHOW_ATTRIBUTE(xive_core_debug);
1657 
1658 int xive_core_debug_init(void)
1659 {
1660 	if (xive_enabled())
1661 		debugfs_create_file("xive", 0400, powerpc_debugfs_root,
1662 				    NULL, &xive_core_debug_fops);
1663 	return 0;
1664 }
1665