1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2016,2017 IBM Corporation. 4 */ 5 6 #define pr_fmt(fmt) "xive: " fmt 7 8 #include <linux/types.h> 9 #include <linux/threads.h> 10 #include <linux/kernel.h> 11 #include <linux/irq.h> 12 #include <linux/debugfs.h> 13 #include <linux/smp.h> 14 #include <linux/interrupt.h> 15 #include <linux/seq_file.h> 16 #include <linux/init.h> 17 #include <linux/cpu.h> 18 #include <linux/of.h> 19 #include <linux/slab.h> 20 #include <linux/spinlock.h> 21 #include <linux/msi.h> 22 #include <linux/vmalloc.h> 23 24 #include <asm/debugfs.h> 25 #include <asm/prom.h> 26 #include <asm/io.h> 27 #include <asm/smp.h> 28 #include <asm/machdep.h> 29 #include <asm/irq.h> 30 #include <asm/errno.h> 31 #include <asm/xive.h> 32 #include <asm/xive-regs.h> 33 #include <asm/xmon.h> 34 35 #include "xive-internal.h" 36 37 #undef DEBUG_FLUSH 38 #undef DEBUG_ALL 39 40 #ifdef DEBUG_ALL 41 #define DBG_VERBOSE(fmt, ...) pr_devel("cpu %d - " fmt, \ 42 smp_processor_id(), ## __VA_ARGS__) 43 #else 44 #define DBG_VERBOSE(fmt...) do { } while(0) 45 #endif 46 47 bool __xive_enabled; 48 EXPORT_SYMBOL_GPL(__xive_enabled); 49 bool xive_cmdline_disabled; 50 51 /* We use only one priority for now */ 52 static u8 xive_irq_priority; 53 54 /* TIMA exported to KVM */ 55 void __iomem *xive_tima; 56 EXPORT_SYMBOL_GPL(xive_tima); 57 u32 xive_tima_offset; 58 59 /* Backend ops */ 60 static const struct xive_ops *xive_ops; 61 62 /* Our global interrupt domain */ 63 static struct irq_domain *xive_irq_domain; 64 65 #ifdef CONFIG_SMP 66 /* The IPIs all use the same logical irq number */ 67 static u32 xive_ipi_irq; 68 #endif 69 70 /* Xive state for each CPU */ 71 static DEFINE_PER_CPU(struct xive_cpu *, xive_cpu); 72 73 /* An invalid CPU target */ 74 #define XIVE_INVALID_TARGET (-1) 75 76 /* 77 * Read the next entry in a queue, return its content if it's valid 78 * or 0 if there is no new entry. 79 * 80 * The queue pointer is moved forward unless "just_peek" is set 81 */ 82 static u32 xive_read_eq(struct xive_q *q, bool just_peek) 83 { 84 u32 cur; 85 86 if (!q->qpage) 87 return 0; 88 cur = be32_to_cpup(q->qpage + q->idx); 89 90 /* Check valid bit (31) vs current toggle polarity */ 91 if ((cur >> 31) == q->toggle) 92 return 0; 93 94 /* If consuming from the queue ... */ 95 if (!just_peek) { 96 /* Next entry */ 97 q->idx = (q->idx + 1) & q->msk; 98 99 /* Wrap around: flip valid toggle */ 100 if (q->idx == 0) 101 q->toggle ^= 1; 102 } 103 /* Mask out the valid bit (31) */ 104 return cur & 0x7fffffff; 105 } 106 107 /* 108 * Scans all the queue that may have interrupts in them 109 * (based on "pending_prio") in priority order until an 110 * interrupt is found or all the queues are empty. 111 * 112 * Then updates the CPPR (Current Processor Priority 113 * Register) based on the most favored interrupt found 114 * (0xff if none) and return what was found (0 if none). 115 * 116 * If just_peek is set, return the most favored pending 117 * interrupt if any but don't update the queue pointers. 118 * 119 * Note: This function can operate generically on any number 120 * of queues (up to 8). The current implementation of the XIVE 121 * driver only uses a single queue however. 122 * 123 * Note2: This will also "flush" "the pending_count" of a queue 124 * into the "count" when that queue is observed to be empty. 125 * This is used to keep track of the amount of interrupts 126 * targetting a queue. When an interrupt is moved away from 127 * a queue, we only decrement that queue count once the queue 128 * has been observed empty to avoid races. 129 */ 130 static u32 xive_scan_interrupts(struct xive_cpu *xc, bool just_peek) 131 { 132 u32 irq = 0; 133 u8 prio = 0; 134 135 /* Find highest pending priority */ 136 while (xc->pending_prio != 0) { 137 struct xive_q *q; 138 139 prio = ffs(xc->pending_prio) - 1; 140 DBG_VERBOSE("scan_irq: trying prio %d\n", prio); 141 142 /* Try to fetch */ 143 irq = xive_read_eq(&xc->queue[prio], just_peek); 144 145 /* Found something ? That's it */ 146 if (irq) { 147 if (just_peek || irq_to_desc(irq)) 148 break; 149 /* 150 * We should never get here; if we do then we must 151 * have failed to synchronize the interrupt properly 152 * when shutting it down. 153 */ 154 pr_crit("xive: got interrupt %d without descriptor, dropping\n", 155 irq); 156 WARN_ON(1); 157 continue; 158 } 159 160 /* Clear pending bits */ 161 xc->pending_prio &= ~(1 << prio); 162 163 /* 164 * Check if the queue count needs adjusting due to 165 * interrupts being moved away. See description of 166 * xive_dec_target_count() 167 */ 168 q = &xc->queue[prio]; 169 if (atomic_read(&q->pending_count)) { 170 int p = atomic_xchg(&q->pending_count, 0); 171 if (p) { 172 WARN_ON(p > atomic_read(&q->count)); 173 atomic_sub(p, &q->count); 174 } 175 } 176 } 177 178 /* If nothing was found, set CPPR to 0xff */ 179 if (irq == 0) 180 prio = 0xff; 181 182 /* Update HW CPPR to match if necessary */ 183 if (prio != xc->cppr) { 184 DBG_VERBOSE("scan_irq: adjusting CPPR to %d\n", prio); 185 xc->cppr = prio; 186 out_8(xive_tima + xive_tima_offset + TM_CPPR, prio); 187 } 188 189 return irq; 190 } 191 192 /* 193 * This is used to perform the magic loads from an ESB 194 * described in xive-regs.h 195 */ 196 static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset) 197 { 198 u64 val; 199 200 if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI) 201 offset |= XIVE_ESB_LD_ST_MO; 202 203 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw) 204 val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0); 205 else 206 val = in_be64(xd->eoi_mmio + offset); 207 208 return (u8)val; 209 } 210 211 static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data) 212 { 213 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw) 214 xive_ops->esb_rw(xd->hw_irq, offset, data, 1); 215 else 216 out_be64(xd->eoi_mmio + offset, data); 217 } 218 219 #ifdef CONFIG_XMON 220 static notrace void xive_dump_eq(const char *name, struct xive_q *q) 221 { 222 u32 i0, i1, idx; 223 224 if (!q->qpage) 225 return; 226 idx = q->idx; 227 i0 = be32_to_cpup(q->qpage + idx); 228 idx = (idx + 1) & q->msk; 229 i1 = be32_to_cpup(q->qpage + idx); 230 xmon_printf("%s idx=%d T=%d %08x %08x ...", name, 231 q->idx, q->toggle, i0, i1); 232 } 233 234 notrace void xmon_xive_do_dump(int cpu) 235 { 236 struct xive_cpu *xc = per_cpu(xive_cpu, cpu); 237 238 xmon_printf("CPU %d:", cpu); 239 if (xc) { 240 xmon_printf("pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr); 241 242 #ifdef CONFIG_SMP 243 { 244 u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET); 245 246 xmon_printf("IPI=0x%08x PQ=%c%c ", xc->hw_ipi, 247 val & XIVE_ESB_VAL_P ? 'P' : '-', 248 val & XIVE_ESB_VAL_Q ? 'Q' : '-'); 249 } 250 #endif 251 xive_dump_eq("EQ", &xc->queue[xive_irq_priority]); 252 } 253 xmon_printf("\n"); 254 } 255 256 int xmon_xive_get_irq_config(u32 hw_irq, struct irq_data *d) 257 { 258 struct irq_chip *chip = irq_data_get_irq_chip(d); 259 int rc; 260 u32 target; 261 u8 prio; 262 u32 lirq; 263 264 if (!is_xive_irq(chip)) 265 return -EINVAL; 266 267 rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq); 268 if (rc) { 269 xmon_printf("IRQ 0x%08x : no config rc=%d\n", hw_irq, rc); 270 return rc; 271 } 272 273 xmon_printf("IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ", 274 hw_irq, target, prio, lirq); 275 276 if (d) { 277 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 278 u64 val = xive_esb_read(xd, XIVE_ESB_GET); 279 280 xmon_printf("flags=%c%c%c PQ=%c%c", 281 xd->flags & XIVE_IRQ_FLAG_STORE_EOI ? 'S' : ' ', 282 xd->flags & XIVE_IRQ_FLAG_LSI ? 'L' : ' ', 283 xd->flags & XIVE_IRQ_FLAG_H_INT_ESB ? 'H' : ' ', 284 val & XIVE_ESB_VAL_P ? 'P' : '-', 285 val & XIVE_ESB_VAL_Q ? 'Q' : '-'); 286 } 287 288 xmon_printf("\n"); 289 return 0; 290 } 291 292 void xmon_xive_get_irq_all(void) 293 { 294 unsigned int i; 295 struct irq_desc *desc; 296 297 for_each_irq_desc(i, desc) { 298 struct irq_data *d = irq_desc_get_irq_data(desc); 299 unsigned int hwirq = (unsigned int)irqd_to_hwirq(d); 300 301 if (d->domain == xive_irq_domain) 302 xmon_xive_get_irq_config(hwirq, d); 303 } 304 } 305 306 #endif /* CONFIG_XMON */ 307 308 static unsigned int xive_get_irq(void) 309 { 310 struct xive_cpu *xc = __this_cpu_read(xive_cpu); 311 u32 irq; 312 313 /* 314 * This can be called either as a result of a HW interrupt or 315 * as a "replay" because EOI decided there was still something 316 * in one of the queues. 317 * 318 * First we perform an ACK cycle in order to update our mask 319 * of pending priorities. This will also have the effect of 320 * updating the CPPR to the most favored pending interrupts. 321 * 322 * In the future, if we have a way to differentiate a first 323 * entry (on HW interrupt) from a replay triggered by EOI, 324 * we could skip this on replays unless we soft-mask tells us 325 * that a new HW interrupt occurred. 326 */ 327 xive_ops->update_pending(xc); 328 329 DBG_VERBOSE("get_irq: pending=%02x\n", xc->pending_prio); 330 331 /* Scan our queue(s) for interrupts */ 332 irq = xive_scan_interrupts(xc, false); 333 334 DBG_VERBOSE("get_irq: got irq 0x%x, new pending=0x%02x\n", 335 irq, xc->pending_prio); 336 337 /* Return pending interrupt if any */ 338 if (irq == XIVE_BAD_IRQ) 339 return 0; 340 return irq; 341 } 342 343 /* 344 * After EOI'ing an interrupt, we need to re-check the queue 345 * to see if another interrupt is pending since multiple 346 * interrupts can coalesce into a single notification to the 347 * CPU. 348 * 349 * If we find that there is indeed more in there, we call 350 * force_external_irq_replay() to make Linux synthetize an 351 * external interrupt on the next call to local_irq_restore(). 352 */ 353 static void xive_do_queue_eoi(struct xive_cpu *xc) 354 { 355 if (xive_scan_interrupts(xc, true) != 0) { 356 DBG_VERBOSE("eoi: pending=0x%02x\n", xc->pending_prio); 357 force_external_irq_replay(); 358 } 359 } 360 361 /* 362 * EOI an interrupt at the source. There are several methods 363 * to do this depending on the HW version and source type 364 */ 365 static void xive_do_source_eoi(struct xive_irq_data *xd) 366 { 367 u8 eoi_val; 368 369 xd->stale_p = false; 370 371 /* If the XIVE supports the new "store EOI facility, use it */ 372 if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI) { 373 xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0); 374 return; 375 } 376 377 /* 378 * For LSIs, we use the "EOI cycle" special load rather than 379 * PQ bits, as they are automatically re-triggered in HW when 380 * still pending. 381 */ 382 if (xd->flags & XIVE_IRQ_FLAG_LSI) { 383 xive_esb_read(xd, XIVE_ESB_LOAD_EOI); 384 return; 385 } 386 387 /* 388 * Otherwise, we use the special MMIO that does a clear of 389 * both P and Q and returns the old Q. This allows us to then 390 * do a re-trigger if Q was set rather than synthesizing an 391 * interrupt in software 392 */ 393 eoi_val = xive_esb_read(xd, XIVE_ESB_SET_PQ_00); 394 DBG_VERBOSE("eoi_val=%x\n", eoi_val); 395 396 /* Re-trigger if needed */ 397 if ((eoi_val & XIVE_ESB_VAL_Q) && xd->trig_mmio) 398 out_be64(xd->trig_mmio, 0); 399 } 400 401 /* irq_chip eoi callback, called with irq descriptor lock held */ 402 static void xive_irq_eoi(struct irq_data *d) 403 { 404 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 405 struct xive_cpu *xc = __this_cpu_read(xive_cpu); 406 407 DBG_VERBOSE("eoi_irq: irq=%d [0x%lx] pending=%02x\n", 408 d->irq, irqd_to_hwirq(d), xc->pending_prio); 409 410 /* 411 * EOI the source if it hasn't been disabled and hasn't 412 * been passed-through to a KVM guest 413 */ 414 if (!irqd_irq_disabled(d) && !irqd_is_forwarded_to_vcpu(d) && 415 !(xd->flags & XIVE_IRQ_FLAG_NO_EOI)) 416 xive_do_source_eoi(xd); 417 else 418 xd->stale_p = true; 419 420 /* 421 * Clear saved_p to indicate that it's no longer occupying 422 * a queue slot on the target queue 423 */ 424 xd->saved_p = false; 425 426 /* Check for more work in the queue */ 427 xive_do_queue_eoi(xc); 428 } 429 430 /* 431 * Helper used to mask and unmask an interrupt source. 432 */ 433 static void xive_do_source_set_mask(struct xive_irq_data *xd, 434 bool mask) 435 { 436 u64 val; 437 438 /* 439 * If the interrupt had P set, it may be in a queue. 440 * 441 * We need to make sure we don't re-enable it until it 442 * has been fetched from that queue and EOId. We keep 443 * a copy of that P state and use it to restore the 444 * ESB accordingly on unmask. 445 */ 446 if (mask) { 447 val = xive_esb_read(xd, XIVE_ESB_SET_PQ_01); 448 if (!xd->stale_p && !!(val & XIVE_ESB_VAL_P)) 449 xd->saved_p = true; 450 xd->stale_p = false; 451 } else if (xd->saved_p) { 452 xive_esb_read(xd, XIVE_ESB_SET_PQ_10); 453 xd->saved_p = false; 454 } else { 455 xive_esb_read(xd, XIVE_ESB_SET_PQ_00); 456 xd->stale_p = false; 457 } 458 } 459 460 /* 461 * Try to chose "cpu" as a new interrupt target. Increments 462 * the queue accounting for that target if it's not already 463 * full. 464 */ 465 static bool xive_try_pick_target(int cpu) 466 { 467 struct xive_cpu *xc = per_cpu(xive_cpu, cpu); 468 struct xive_q *q = &xc->queue[xive_irq_priority]; 469 int max; 470 471 /* 472 * Calculate max number of interrupts in that queue. 473 * 474 * We leave a gap of 1 just in case... 475 */ 476 max = (q->msk + 1) - 1; 477 return !!atomic_add_unless(&q->count, 1, max); 478 } 479 480 /* 481 * Un-account an interrupt for a target CPU. We don't directly 482 * decrement q->count since the interrupt might still be present 483 * in the queue. 484 * 485 * Instead increment a separate counter "pending_count" which 486 * will be substracted from "count" later when that CPU observes 487 * the queue to be empty. 488 */ 489 static void xive_dec_target_count(int cpu) 490 { 491 struct xive_cpu *xc = per_cpu(xive_cpu, cpu); 492 struct xive_q *q = &xc->queue[xive_irq_priority]; 493 494 if (WARN_ON(cpu < 0 || !xc)) { 495 pr_err("%s: cpu=%d xc=%p\n", __func__, cpu, xc); 496 return; 497 } 498 499 /* 500 * We increment the "pending count" which will be used 501 * to decrement the target queue count whenever it's next 502 * processed and found empty. This ensure that we don't 503 * decrement while we still have the interrupt there 504 * occupying a slot. 505 */ 506 atomic_inc(&q->pending_count); 507 } 508 509 /* Find a tentative CPU target in a CPU mask */ 510 static int xive_find_target_in_mask(const struct cpumask *mask, 511 unsigned int fuzz) 512 { 513 int cpu, first, num, i; 514 515 /* Pick up a starting point CPU in the mask based on fuzz */ 516 num = min_t(int, cpumask_weight(mask), nr_cpu_ids); 517 first = fuzz % num; 518 519 /* Locate it */ 520 cpu = cpumask_first(mask); 521 for (i = 0; i < first && cpu < nr_cpu_ids; i++) 522 cpu = cpumask_next(cpu, mask); 523 524 /* Sanity check */ 525 if (WARN_ON(cpu >= nr_cpu_ids)) 526 cpu = cpumask_first(cpu_online_mask); 527 528 /* Remember first one to handle wrap-around */ 529 first = cpu; 530 531 /* 532 * Now go through the entire mask until we find a valid 533 * target. 534 */ 535 do { 536 /* 537 * We re-check online as the fallback case passes us 538 * an untested affinity mask 539 */ 540 if (cpu_online(cpu) && xive_try_pick_target(cpu)) 541 return cpu; 542 cpu = cpumask_next(cpu, mask); 543 /* Wrap around */ 544 if (cpu >= nr_cpu_ids) 545 cpu = cpumask_first(mask); 546 } while (cpu != first); 547 548 return -1; 549 } 550 551 /* 552 * Pick a target CPU for an interrupt. This is done at 553 * startup or if the affinity is changed in a way that 554 * invalidates the current target. 555 */ 556 static int xive_pick_irq_target(struct irq_data *d, 557 const struct cpumask *affinity) 558 { 559 static unsigned int fuzz; 560 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 561 cpumask_var_t mask; 562 int cpu = -1; 563 564 /* 565 * If we have chip IDs, first we try to build a mask of 566 * CPUs matching the CPU and find a target in there 567 */ 568 if (xd->src_chip != XIVE_INVALID_CHIP_ID && 569 zalloc_cpumask_var(&mask, GFP_ATOMIC)) { 570 /* Build a mask of matching chip IDs */ 571 for_each_cpu_and(cpu, affinity, cpu_online_mask) { 572 struct xive_cpu *xc = per_cpu(xive_cpu, cpu); 573 if (xc->chip_id == xd->src_chip) 574 cpumask_set_cpu(cpu, mask); 575 } 576 /* Try to find a target */ 577 if (cpumask_empty(mask)) 578 cpu = -1; 579 else 580 cpu = xive_find_target_in_mask(mask, fuzz++); 581 free_cpumask_var(mask); 582 if (cpu >= 0) 583 return cpu; 584 fuzz--; 585 } 586 587 /* No chip IDs, fallback to using the affinity mask */ 588 return xive_find_target_in_mask(affinity, fuzz++); 589 } 590 591 static unsigned int xive_irq_startup(struct irq_data *d) 592 { 593 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 594 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 595 int target, rc; 596 597 xd->saved_p = false; 598 xd->stale_p = false; 599 pr_devel("xive_irq_startup: irq %d [0x%x] data @%p\n", 600 d->irq, hw_irq, d); 601 602 #ifdef CONFIG_PCI_MSI 603 /* 604 * The generic MSI code returns with the interrupt disabled on the 605 * card, using the MSI mask bits. Firmware doesn't appear to unmask 606 * at that level, so we do it here by hand. 607 */ 608 if (irq_data_get_msi_desc(d)) 609 pci_msi_unmask_irq(d); 610 #endif 611 612 /* Pick a target */ 613 target = xive_pick_irq_target(d, irq_data_get_affinity_mask(d)); 614 if (target == XIVE_INVALID_TARGET) { 615 /* Try again breaking affinity */ 616 target = xive_pick_irq_target(d, cpu_online_mask); 617 if (target == XIVE_INVALID_TARGET) 618 return -ENXIO; 619 pr_warn("irq %d started with broken affinity\n", d->irq); 620 } 621 622 /* Sanity check */ 623 if (WARN_ON(target == XIVE_INVALID_TARGET || 624 target >= nr_cpu_ids)) 625 target = smp_processor_id(); 626 627 xd->target = target; 628 629 /* 630 * Configure the logical number to be the Linux IRQ number 631 * and set the target queue 632 */ 633 rc = xive_ops->configure_irq(hw_irq, 634 get_hard_smp_processor_id(target), 635 xive_irq_priority, d->irq); 636 if (rc) 637 return rc; 638 639 /* Unmask the ESB */ 640 xive_do_source_set_mask(xd, false); 641 642 return 0; 643 } 644 645 /* called with irq descriptor lock held */ 646 static void xive_irq_shutdown(struct irq_data *d) 647 { 648 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 649 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 650 651 pr_devel("xive_irq_shutdown: irq %d [0x%x] data @%p\n", 652 d->irq, hw_irq, d); 653 654 if (WARN_ON(xd->target == XIVE_INVALID_TARGET)) 655 return; 656 657 /* Mask the interrupt at the source */ 658 xive_do_source_set_mask(xd, true); 659 660 /* 661 * Mask the interrupt in HW in the IVT/EAS and set the number 662 * to be the "bad" IRQ number 663 */ 664 xive_ops->configure_irq(hw_irq, 665 get_hard_smp_processor_id(xd->target), 666 0xff, XIVE_BAD_IRQ); 667 668 xive_dec_target_count(xd->target); 669 xd->target = XIVE_INVALID_TARGET; 670 } 671 672 static void xive_irq_unmask(struct irq_data *d) 673 { 674 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 675 676 pr_devel("xive_irq_unmask: irq %d data @%p\n", d->irq, xd); 677 678 xive_do_source_set_mask(xd, false); 679 } 680 681 static void xive_irq_mask(struct irq_data *d) 682 { 683 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 684 685 pr_devel("xive_irq_mask: irq %d data @%p\n", d->irq, xd); 686 687 xive_do_source_set_mask(xd, true); 688 } 689 690 static int xive_irq_set_affinity(struct irq_data *d, 691 const struct cpumask *cpumask, 692 bool force) 693 { 694 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 695 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 696 u32 target, old_target; 697 int rc = 0; 698 699 pr_devel("xive_irq_set_affinity: irq %d\n", d->irq); 700 701 /* Is this valid ? */ 702 if (cpumask_any_and(cpumask, cpu_online_mask) >= nr_cpu_ids) 703 return -EINVAL; 704 705 /* Don't do anything if the interrupt isn't started */ 706 if (!irqd_is_started(d)) 707 return IRQ_SET_MASK_OK; 708 709 /* 710 * If existing target is already in the new mask, and is 711 * online then do nothing. 712 */ 713 if (xd->target != XIVE_INVALID_TARGET && 714 cpu_online(xd->target) && 715 cpumask_test_cpu(xd->target, cpumask)) 716 return IRQ_SET_MASK_OK; 717 718 /* Pick a new target */ 719 target = xive_pick_irq_target(d, cpumask); 720 721 /* No target found */ 722 if (target == XIVE_INVALID_TARGET) 723 return -ENXIO; 724 725 /* Sanity check */ 726 if (WARN_ON(target >= nr_cpu_ids)) 727 target = smp_processor_id(); 728 729 old_target = xd->target; 730 731 /* 732 * Only configure the irq if it's not currently passed-through to 733 * a KVM guest 734 */ 735 if (!irqd_is_forwarded_to_vcpu(d)) 736 rc = xive_ops->configure_irq(hw_irq, 737 get_hard_smp_processor_id(target), 738 xive_irq_priority, d->irq); 739 if (rc < 0) { 740 pr_err("Error %d reconfiguring irq %d\n", rc, d->irq); 741 return rc; 742 } 743 744 pr_devel(" target: 0x%x\n", target); 745 xd->target = target; 746 747 /* Give up previous target */ 748 if (old_target != XIVE_INVALID_TARGET) 749 xive_dec_target_count(old_target); 750 751 return IRQ_SET_MASK_OK; 752 } 753 754 static int xive_irq_set_type(struct irq_data *d, unsigned int flow_type) 755 { 756 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 757 758 /* 759 * We only support these. This has really no effect other than setting 760 * the corresponding descriptor bits mind you but those will in turn 761 * affect the resend function when re-enabling an edge interrupt. 762 * 763 * Set set the default to edge as explained in map(). 764 */ 765 if (flow_type == IRQ_TYPE_DEFAULT || flow_type == IRQ_TYPE_NONE) 766 flow_type = IRQ_TYPE_EDGE_RISING; 767 768 if (flow_type != IRQ_TYPE_EDGE_RISING && 769 flow_type != IRQ_TYPE_LEVEL_LOW) 770 return -EINVAL; 771 772 irqd_set_trigger_type(d, flow_type); 773 774 /* 775 * Double check it matches what the FW thinks 776 * 777 * NOTE: We don't know yet if the PAPR interface will provide 778 * the LSI vs MSI information apart from the device-tree so 779 * this check might have to move into an optional backend call 780 * that is specific to the native backend 781 */ 782 if ((flow_type == IRQ_TYPE_LEVEL_LOW) != 783 !!(xd->flags & XIVE_IRQ_FLAG_LSI)) { 784 pr_warn("Interrupt %d (HW 0x%x) type mismatch, Linux says %s, FW says %s\n", 785 d->irq, (u32)irqd_to_hwirq(d), 786 (flow_type == IRQ_TYPE_LEVEL_LOW) ? "Level" : "Edge", 787 (xd->flags & XIVE_IRQ_FLAG_LSI) ? "Level" : "Edge"); 788 } 789 790 return IRQ_SET_MASK_OK_NOCOPY; 791 } 792 793 static int xive_irq_retrigger(struct irq_data *d) 794 { 795 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 796 797 /* This should be only for MSIs */ 798 if (WARN_ON(xd->flags & XIVE_IRQ_FLAG_LSI)) 799 return 0; 800 801 /* 802 * To perform a retrigger, we first set the PQ bits to 803 * 11, then perform an EOI. 804 */ 805 xive_esb_read(xd, XIVE_ESB_SET_PQ_11); 806 xive_do_source_eoi(xd); 807 808 return 1; 809 } 810 811 /* 812 * Caller holds the irq descriptor lock, so this won't be called 813 * concurrently with xive_get_irqchip_state on the same interrupt. 814 */ 815 static int xive_irq_set_vcpu_affinity(struct irq_data *d, void *state) 816 { 817 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 818 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 819 int rc; 820 u8 pq; 821 822 /* 823 * This is called by KVM with state non-NULL for enabling 824 * pass-through or NULL for disabling it 825 */ 826 if (state) { 827 irqd_set_forwarded_to_vcpu(d); 828 829 /* Set it to PQ=10 state to prevent further sends */ 830 pq = xive_esb_read(xd, XIVE_ESB_SET_PQ_10); 831 if (!xd->stale_p) { 832 xd->saved_p = !!(pq & XIVE_ESB_VAL_P); 833 xd->stale_p = !xd->saved_p; 834 } 835 836 /* No target ? nothing to do */ 837 if (xd->target == XIVE_INVALID_TARGET) { 838 /* 839 * An untargetted interrupt should have been 840 * also masked at the source 841 */ 842 WARN_ON(xd->saved_p); 843 844 return 0; 845 } 846 847 /* 848 * If P was set, adjust state to PQ=11 to indicate 849 * that a resend is needed for the interrupt to reach 850 * the guest. Also remember the value of P. 851 * 852 * This also tells us that it's in flight to a host queue 853 * or has already been fetched but hasn't been EOIed yet 854 * by the host. This it's potentially using up a host 855 * queue slot. This is important to know because as long 856 * as this is the case, we must not hard-unmask it when 857 * "returning" that interrupt to the host. 858 * 859 * This saved_p is cleared by the host EOI, when we know 860 * for sure the queue slot is no longer in use. 861 */ 862 if (xd->saved_p) { 863 xive_esb_read(xd, XIVE_ESB_SET_PQ_11); 864 865 /* 866 * Sync the XIVE source HW to ensure the interrupt 867 * has gone through the EAS before we change its 868 * target to the guest. That should guarantee us 869 * that we *will* eventually get an EOI for it on 870 * the host. Otherwise there would be a small window 871 * for P to be seen here but the interrupt going 872 * to the guest queue. 873 */ 874 if (xive_ops->sync_source) 875 xive_ops->sync_source(hw_irq); 876 } 877 } else { 878 irqd_clr_forwarded_to_vcpu(d); 879 880 /* No host target ? hard mask and return */ 881 if (xd->target == XIVE_INVALID_TARGET) { 882 xive_do_source_set_mask(xd, true); 883 return 0; 884 } 885 886 /* 887 * Sync the XIVE source HW to ensure the interrupt 888 * has gone through the EAS before we change its 889 * target to the host. 890 */ 891 if (xive_ops->sync_source) 892 xive_ops->sync_source(hw_irq); 893 894 /* 895 * By convention we are called with the interrupt in 896 * a PQ=10 or PQ=11 state, ie, it won't fire and will 897 * have latched in Q whether there's a pending HW 898 * interrupt or not. 899 * 900 * First reconfigure the target. 901 */ 902 rc = xive_ops->configure_irq(hw_irq, 903 get_hard_smp_processor_id(xd->target), 904 xive_irq_priority, d->irq); 905 if (rc) 906 return rc; 907 908 /* 909 * Then if saved_p is not set, effectively re-enable the 910 * interrupt with an EOI. If it is set, we know there is 911 * still a message in a host queue somewhere that will be 912 * EOId eventually. 913 * 914 * Note: We don't check irqd_irq_disabled(). Effectively, 915 * we *will* let the irq get through even if masked if the 916 * HW is still firing it in order to deal with the whole 917 * saved_p business properly. If the interrupt triggers 918 * while masked, the generic code will re-mask it anyway. 919 */ 920 if (!xd->saved_p) 921 xive_do_source_eoi(xd); 922 923 } 924 return 0; 925 } 926 927 /* Called with irq descriptor lock held. */ 928 static int xive_get_irqchip_state(struct irq_data *data, 929 enum irqchip_irq_state which, bool *state) 930 { 931 struct xive_irq_data *xd = irq_data_get_irq_handler_data(data); 932 u8 pq; 933 934 switch (which) { 935 case IRQCHIP_STATE_ACTIVE: 936 pq = xive_esb_read(xd, XIVE_ESB_GET); 937 938 /* 939 * The esb value being all 1's means we couldn't get 940 * the PQ state of the interrupt through mmio. It may 941 * happen, for example when querying a PHB interrupt 942 * while the PHB is in an error state. We consider the 943 * interrupt to be inactive in that case. 944 */ 945 *state = (pq != XIVE_ESB_INVALID) && !xd->stale_p && 946 (xd->saved_p || !!(pq & XIVE_ESB_VAL_P)); 947 return 0; 948 default: 949 return -EINVAL; 950 } 951 } 952 953 static struct irq_chip xive_irq_chip = { 954 .name = "XIVE-IRQ", 955 .irq_startup = xive_irq_startup, 956 .irq_shutdown = xive_irq_shutdown, 957 .irq_eoi = xive_irq_eoi, 958 .irq_mask = xive_irq_mask, 959 .irq_unmask = xive_irq_unmask, 960 .irq_set_affinity = xive_irq_set_affinity, 961 .irq_set_type = xive_irq_set_type, 962 .irq_retrigger = xive_irq_retrigger, 963 .irq_set_vcpu_affinity = xive_irq_set_vcpu_affinity, 964 .irq_get_irqchip_state = xive_get_irqchip_state, 965 }; 966 967 bool is_xive_irq(struct irq_chip *chip) 968 { 969 return chip == &xive_irq_chip; 970 } 971 EXPORT_SYMBOL_GPL(is_xive_irq); 972 973 void xive_cleanup_irq_data(struct xive_irq_data *xd) 974 { 975 if (xd->eoi_mmio) { 976 unmap_kernel_range((unsigned long)xd->eoi_mmio, 977 1u << xd->esb_shift); 978 iounmap(xd->eoi_mmio); 979 if (xd->eoi_mmio == xd->trig_mmio) 980 xd->trig_mmio = NULL; 981 xd->eoi_mmio = NULL; 982 } 983 if (xd->trig_mmio) { 984 unmap_kernel_range((unsigned long)xd->trig_mmio, 985 1u << xd->esb_shift); 986 iounmap(xd->trig_mmio); 987 xd->trig_mmio = NULL; 988 } 989 } 990 EXPORT_SYMBOL_GPL(xive_cleanup_irq_data); 991 992 static int xive_irq_alloc_data(unsigned int virq, irq_hw_number_t hw) 993 { 994 struct xive_irq_data *xd; 995 int rc; 996 997 xd = kzalloc(sizeof(struct xive_irq_data), GFP_KERNEL); 998 if (!xd) 999 return -ENOMEM; 1000 rc = xive_ops->populate_irq_data(hw, xd); 1001 if (rc) { 1002 kfree(xd); 1003 return rc; 1004 } 1005 xd->target = XIVE_INVALID_TARGET; 1006 irq_set_handler_data(virq, xd); 1007 1008 /* 1009 * Turn OFF by default the interrupt being mapped. A side 1010 * effect of this check is the mapping the ESB page of the 1011 * interrupt in the Linux address space. This prevents page 1012 * fault issues in the crash handler which masks all 1013 * interrupts. 1014 */ 1015 xive_esb_read(xd, XIVE_ESB_SET_PQ_01); 1016 1017 return 0; 1018 } 1019 1020 static void xive_irq_free_data(unsigned int virq) 1021 { 1022 struct xive_irq_data *xd = irq_get_handler_data(virq); 1023 1024 if (!xd) 1025 return; 1026 irq_set_handler_data(virq, NULL); 1027 xive_cleanup_irq_data(xd); 1028 kfree(xd); 1029 } 1030 1031 #ifdef CONFIG_SMP 1032 1033 static void xive_cause_ipi(int cpu) 1034 { 1035 struct xive_cpu *xc; 1036 struct xive_irq_data *xd; 1037 1038 xc = per_cpu(xive_cpu, cpu); 1039 1040 DBG_VERBOSE("IPI CPU %d -> %d (HW IRQ 0x%x)\n", 1041 smp_processor_id(), cpu, xc->hw_ipi); 1042 1043 xd = &xc->ipi_data; 1044 if (WARN_ON(!xd->trig_mmio)) 1045 return; 1046 out_be64(xd->trig_mmio, 0); 1047 } 1048 1049 static irqreturn_t xive_muxed_ipi_action(int irq, void *dev_id) 1050 { 1051 return smp_ipi_demux(); 1052 } 1053 1054 static void xive_ipi_eoi(struct irq_data *d) 1055 { 1056 struct xive_cpu *xc = __this_cpu_read(xive_cpu); 1057 1058 /* Handle possible race with unplug and drop stale IPIs */ 1059 if (!xc) 1060 return; 1061 1062 DBG_VERBOSE("IPI eoi: irq=%d [0x%lx] (HW IRQ 0x%x) pending=%02x\n", 1063 d->irq, irqd_to_hwirq(d), xc->hw_ipi, xc->pending_prio); 1064 1065 xive_do_source_eoi(&xc->ipi_data); 1066 xive_do_queue_eoi(xc); 1067 } 1068 1069 static void xive_ipi_do_nothing(struct irq_data *d) 1070 { 1071 /* 1072 * Nothing to do, we never mask/unmask IPIs, but the callback 1073 * has to exist for the struct irq_chip. 1074 */ 1075 } 1076 1077 static struct irq_chip xive_ipi_chip = { 1078 .name = "XIVE-IPI", 1079 .irq_eoi = xive_ipi_eoi, 1080 .irq_mask = xive_ipi_do_nothing, 1081 .irq_unmask = xive_ipi_do_nothing, 1082 }; 1083 1084 /* 1085 * IPIs are marked per-cpu. We use separate HW interrupts under the 1086 * hood but associated with the same "linux" interrupt 1087 */ 1088 static int xive_ipi_irq_domain_map(struct irq_domain *h, unsigned int virq, 1089 irq_hw_number_t hw) 1090 { 1091 irq_set_chip_and_handler(virq, &xive_ipi_chip, handle_percpu_irq); 1092 return 0; 1093 } 1094 1095 static const struct irq_domain_ops xive_ipi_irq_domain_ops = { 1096 .map = xive_ipi_irq_domain_map, 1097 }; 1098 1099 static int __init xive_request_ipi(void) 1100 { 1101 struct fwnode_handle *fwnode; 1102 struct irq_domain *ipi_domain; 1103 unsigned int virq; 1104 int ret = -ENOMEM; 1105 1106 fwnode = irq_domain_alloc_named_fwnode("XIVE-IPI"); 1107 if (!fwnode) 1108 goto out; 1109 1110 ipi_domain = irq_domain_create_linear(fwnode, 1, 1111 &xive_ipi_irq_domain_ops, NULL); 1112 if (!ipi_domain) 1113 goto out_free_fwnode; 1114 1115 /* Initialize it */ 1116 virq = irq_create_mapping(ipi_domain, XIVE_IPI_HW_IRQ); 1117 if (!virq) { 1118 ret = -EINVAL; 1119 goto out_free_domain; 1120 } 1121 1122 xive_ipi_irq = virq; 1123 1124 ret = request_irq(virq, xive_muxed_ipi_action, 1125 IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL); 1126 1127 WARN(ret < 0, "Failed to request IPI %d: %d\n", virq, ret); 1128 return ret; 1129 1130 out_free_domain: 1131 irq_domain_remove(ipi_domain); 1132 out_free_fwnode: 1133 irq_domain_free_fwnode(fwnode); 1134 out: 1135 return ret; 1136 } 1137 1138 static int xive_setup_cpu_ipi(unsigned int cpu) 1139 { 1140 struct xive_cpu *xc; 1141 int rc; 1142 1143 pr_debug("Setting up IPI for CPU %d\n", cpu); 1144 1145 xc = per_cpu(xive_cpu, cpu); 1146 1147 /* Check if we are already setup */ 1148 if (xc->hw_ipi != XIVE_BAD_IRQ) 1149 return 0; 1150 1151 /* Grab an IPI from the backend, this will populate xc->hw_ipi */ 1152 if (xive_ops->get_ipi(cpu, xc)) 1153 return -EIO; 1154 1155 /* 1156 * Populate the IRQ data in the xive_cpu structure and 1157 * configure the HW / enable the IPIs. 1158 */ 1159 rc = xive_ops->populate_irq_data(xc->hw_ipi, &xc->ipi_data); 1160 if (rc) { 1161 pr_err("Failed to populate IPI data on CPU %d\n", cpu); 1162 return -EIO; 1163 } 1164 rc = xive_ops->configure_irq(xc->hw_ipi, 1165 get_hard_smp_processor_id(cpu), 1166 xive_irq_priority, xive_ipi_irq); 1167 if (rc) { 1168 pr_err("Failed to map IPI CPU %d\n", cpu); 1169 return -EIO; 1170 } 1171 pr_devel("CPU %d HW IPI %x, virq %d, trig_mmio=%p\n", cpu, 1172 xc->hw_ipi, xive_ipi_irq, xc->ipi_data.trig_mmio); 1173 1174 /* Unmask it */ 1175 xive_do_source_set_mask(&xc->ipi_data, false); 1176 1177 return 0; 1178 } 1179 1180 static void xive_cleanup_cpu_ipi(unsigned int cpu, struct xive_cpu *xc) 1181 { 1182 /* Disable the IPI and free the IRQ data */ 1183 1184 /* Already cleaned up ? */ 1185 if (xc->hw_ipi == XIVE_BAD_IRQ) 1186 return; 1187 1188 /* Mask the IPI */ 1189 xive_do_source_set_mask(&xc->ipi_data, true); 1190 1191 /* 1192 * Note: We don't call xive_cleanup_irq_data() to free 1193 * the mappings as this is called from an IPI on kexec 1194 * which is not a safe environment to call iounmap() 1195 */ 1196 1197 /* Deconfigure/mask in the backend */ 1198 xive_ops->configure_irq(xc->hw_ipi, hard_smp_processor_id(), 1199 0xff, xive_ipi_irq); 1200 1201 /* Free the IPIs in the backend */ 1202 xive_ops->put_ipi(cpu, xc); 1203 } 1204 1205 void __init xive_smp_probe(void) 1206 { 1207 smp_ops->cause_ipi = xive_cause_ipi; 1208 1209 /* Register the IPI */ 1210 xive_request_ipi(); 1211 1212 /* Allocate and setup IPI for the boot CPU */ 1213 xive_setup_cpu_ipi(smp_processor_id()); 1214 } 1215 1216 #endif /* CONFIG_SMP */ 1217 1218 static int xive_irq_domain_map(struct irq_domain *h, unsigned int virq, 1219 irq_hw_number_t hw) 1220 { 1221 int rc; 1222 1223 /* 1224 * Mark interrupts as edge sensitive by default so that resend 1225 * actually works. Will fix that up below if needed. 1226 */ 1227 irq_clear_status_flags(virq, IRQ_LEVEL); 1228 1229 rc = xive_irq_alloc_data(virq, hw); 1230 if (rc) 1231 return rc; 1232 1233 irq_set_chip_and_handler(virq, &xive_irq_chip, handle_fasteoi_irq); 1234 1235 return 0; 1236 } 1237 1238 static void xive_irq_domain_unmap(struct irq_domain *d, unsigned int virq) 1239 { 1240 xive_irq_free_data(virq); 1241 } 1242 1243 static int xive_irq_domain_xlate(struct irq_domain *h, struct device_node *ct, 1244 const u32 *intspec, unsigned int intsize, 1245 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 1246 1247 { 1248 *out_hwirq = intspec[0]; 1249 1250 /* 1251 * If intsize is at least 2, we look for the type in the second cell, 1252 * we assume the LSB indicates a level interrupt. 1253 */ 1254 if (intsize > 1) { 1255 if (intspec[1] & 1) 1256 *out_flags = IRQ_TYPE_LEVEL_LOW; 1257 else 1258 *out_flags = IRQ_TYPE_EDGE_RISING; 1259 } else 1260 *out_flags = IRQ_TYPE_LEVEL_LOW; 1261 1262 return 0; 1263 } 1264 1265 static int xive_irq_domain_match(struct irq_domain *h, struct device_node *node, 1266 enum irq_domain_bus_token bus_token) 1267 { 1268 return xive_ops->match(node); 1269 } 1270 1271 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS 1272 static const char * const esb_names[] = { "RESET", "OFF", "PENDING", "QUEUED" }; 1273 1274 static const struct { 1275 u64 mask; 1276 char *name; 1277 } xive_irq_flags[] = { 1278 { XIVE_IRQ_FLAG_STORE_EOI, "STORE_EOI" }, 1279 { XIVE_IRQ_FLAG_LSI, "LSI" }, 1280 { XIVE_IRQ_FLAG_H_INT_ESB, "H_INT_ESB" }, 1281 { XIVE_IRQ_FLAG_NO_EOI, "NO_EOI" }, 1282 }; 1283 1284 static void xive_irq_domain_debug_show(struct seq_file *m, struct irq_domain *d, 1285 struct irq_data *irqd, int ind) 1286 { 1287 struct xive_irq_data *xd; 1288 u64 val; 1289 int i; 1290 1291 /* No IRQ domain level information. To be done */ 1292 if (!irqd) 1293 return; 1294 1295 if (!is_xive_irq(irq_data_get_irq_chip(irqd))) 1296 return; 1297 1298 seq_printf(m, "%*sXIVE:\n", ind, ""); 1299 ind++; 1300 1301 xd = irq_data_get_irq_handler_data(irqd); 1302 if (!xd) { 1303 seq_printf(m, "%*snot assigned\n", ind, ""); 1304 return; 1305 } 1306 1307 val = xive_esb_read(xd, XIVE_ESB_GET); 1308 seq_printf(m, "%*sESB: %s\n", ind, "", esb_names[val & 0x3]); 1309 seq_printf(m, "%*sPstate: %s %s\n", ind, "", xd->stale_p ? "stale" : "", 1310 xd->saved_p ? "saved" : ""); 1311 seq_printf(m, "%*sTarget: %d\n", ind, "", xd->target); 1312 seq_printf(m, "%*sChip: %d\n", ind, "", xd->src_chip); 1313 seq_printf(m, "%*sTrigger: 0x%016llx\n", ind, "", xd->trig_page); 1314 seq_printf(m, "%*sEOI: 0x%016llx\n", ind, "", xd->eoi_page); 1315 seq_printf(m, "%*sFlags: 0x%llx\n", ind, "", xd->flags); 1316 for (i = 0; i < ARRAY_SIZE(xive_irq_flags); i++) { 1317 if (xd->flags & xive_irq_flags[i].mask) 1318 seq_printf(m, "%*s%s\n", ind + 12, "", xive_irq_flags[i].name); 1319 } 1320 } 1321 #endif 1322 1323 static const struct irq_domain_ops xive_irq_domain_ops = { 1324 .match = xive_irq_domain_match, 1325 .map = xive_irq_domain_map, 1326 .unmap = xive_irq_domain_unmap, 1327 .xlate = xive_irq_domain_xlate, 1328 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS 1329 .debug_show = xive_irq_domain_debug_show, 1330 #endif 1331 }; 1332 1333 static void __init xive_init_host(struct device_node *np) 1334 { 1335 xive_irq_domain = irq_domain_add_nomap(np, XIVE_MAX_IRQ, 1336 &xive_irq_domain_ops, NULL); 1337 if (WARN_ON(xive_irq_domain == NULL)) 1338 return; 1339 irq_set_default_host(xive_irq_domain); 1340 } 1341 1342 static void xive_cleanup_cpu_queues(unsigned int cpu, struct xive_cpu *xc) 1343 { 1344 if (xc->queue[xive_irq_priority].qpage) 1345 xive_ops->cleanup_queue(cpu, xc, xive_irq_priority); 1346 } 1347 1348 static int xive_setup_cpu_queues(unsigned int cpu, struct xive_cpu *xc) 1349 { 1350 int rc = 0; 1351 1352 /* We setup 1 queues for now with a 64k page */ 1353 if (!xc->queue[xive_irq_priority].qpage) 1354 rc = xive_ops->setup_queue(cpu, xc, xive_irq_priority); 1355 1356 return rc; 1357 } 1358 1359 static int xive_prepare_cpu(unsigned int cpu) 1360 { 1361 struct xive_cpu *xc; 1362 1363 xc = per_cpu(xive_cpu, cpu); 1364 if (!xc) { 1365 struct device_node *np; 1366 1367 xc = kzalloc_node(sizeof(struct xive_cpu), 1368 GFP_KERNEL, cpu_to_node(cpu)); 1369 if (!xc) 1370 return -ENOMEM; 1371 np = of_get_cpu_node(cpu, NULL); 1372 if (np) 1373 xc->chip_id = of_get_ibm_chip_id(np); 1374 of_node_put(np); 1375 xc->hw_ipi = XIVE_BAD_IRQ; 1376 1377 per_cpu(xive_cpu, cpu) = xc; 1378 } 1379 1380 /* Setup EQs if not already */ 1381 return xive_setup_cpu_queues(cpu, xc); 1382 } 1383 1384 static void xive_setup_cpu(void) 1385 { 1386 struct xive_cpu *xc = __this_cpu_read(xive_cpu); 1387 1388 /* The backend might have additional things to do */ 1389 if (xive_ops->setup_cpu) 1390 xive_ops->setup_cpu(smp_processor_id(), xc); 1391 1392 /* Set CPPR to 0xff to enable flow of interrupts */ 1393 xc->cppr = 0xff; 1394 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff); 1395 } 1396 1397 #ifdef CONFIG_SMP 1398 void xive_smp_setup_cpu(void) 1399 { 1400 pr_devel("SMP setup CPU %d\n", smp_processor_id()); 1401 1402 /* This will have already been done on the boot CPU */ 1403 if (smp_processor_id() != boot_cpuid) 1404 xive_setup_cpu(); 1405 1406 } 1407 1408 int xive_smp_prepare_cpu(unsigned int cpu) 1409 { 1410 int rc; 1411 1412 /* Allocate per-CPU data and queues */ 1413 rc = xive_prepare_cpu(cpu); 1414 if (rc) 1415 return rc; 1416 1417 /* Allocate and setup IPI for the new CPU */ 1418 return xive_setup_cpu_ipi(cpu); 1419 } 1420 1421 #ifdef CONFIG_HOTPLUG_CPU 1422 static void xive_flush_cpu_queue(unsigned int cpu, struct xive_cpu *xc) 1423 { 1424 u32 irq; 1425 1426 /* We assume local irqs are disabled */ 1427 WARN_ON(!irqs_disabled()); 1428 1429 /* Check what's already in the CPU queue */ 1430 while ((irq = xive_scan_interrupts(xc, false)) != 0) { 1431 /* 1432 * We need to re-route that interrupt to its new destination. 1433 * First get and lock the descriptor 1434 */ 1435 struct irq_desc *desc = irq_to_desc(irq); 1436 struct irq_data *d = irq_desc_get_irq_data(desc); 1437 struct xive_irq_data *xd; 1438 1439 /* 1440 * Ignore anything that isn't a XIVE irq and ignore 1441 * IPIs, so can just be dropped. 1442 */ 1443 if (d->domain != xive_irq_domain) 1444 continue; 1445 1446 /* 1447 * The IRQ should have already been re-routed, it's just a 1448 * stale in the old queue, so re-trigger it in order to make 1449 * it reach is new destination. 1450 */ 1451 #ifdef DEBUG_FLUSH 1452 pr_info("CPU %d: Got irq %d while offline, re-sending...\n", 1453 cpu, irq); 1454 #endif 1455 raw_spin_lock(&desc->lock); 1456 xd = irq_desc_get_handler_data(desc); 1457 1458 /* 1459 * Clear saved_p to indicate that it's no longer pending 1460 */ 1461 xd->saved_p = false; 1462 1463 /* 1464 * For LSIs, we EOI, this will cause a resend if it's 1465 * still asserted. Otherwise do an MSI retrigger. 1466 */ 1467 if (xd->flags & XIVE_IRQ_FLAG_LSI) 1468 xive_do_source_eoi(xd); 1469 else 1470 xive_irq_retrigger(d); 1471 1472 raw_spin_unlock(&desc->lock); 1473 } 1474 } 1475 1476 void xive_smp_disable_cpu(void) 1477 { 1478 struct xive_cpu *xc = __this_cpu_read(xive_cpu); 1479 unsigned int cpu = smp_processor_id(); 1480 1481 /* Migrate interrupts away from the CPU */ 1482 irq_migrate_all_off_this_cpu(); 1483 1484 /* Set CPPR to 0 to disable flow of interrupts */ 1485 xc->cppr = 0; 1486 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0); 1487 1488 /* Flush everything still in the queue */ 1489 xive_flush_cpu_queue(cpu, xc); 1490 1491 /* Re-enable CPPR */ 1492 xc->cppr = 0xff; 1493 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff); 1494 } 1495 1496 void xive_flush_interrupt(void) 1497 { 1498 struct xive_cpu *xc = __this_cpu_read(xive_cpu); 1499 unsigned int cpu = smp_processor_id(); 1500 1501 /* Called if an interrupt occurs while the CPU is hot unplugged */ 1502 xive_flush_cpu_queue(cpu, xc); 1503 } 1504 1505 #endif /* CONFIG_HOTPLUG_CPU */ 1506 1507 #endif /* CONFIG_SMP */ 1508 1509 void xive_teardown_cpu(void) 1510 { 1511 struct xive_cpu *xc = __this_cpu_read(xive_cpu); 1512 unsigned int cpu = smp_processor_id(); 1513 1514 /* Set CPPR to 0 to disable flow of interrupts */ 1515 xc->cppr = 0; 1516 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0); 1517 1518 if (xive_ops->teardown_cpu) 1519 xive_ops->teardown_cpu(cpu, xc); 1520 1521 #ifdef CONFIG_SMP 1522 /* Get rid of IPI */ 1523 xive_cleanup_cpu_ipi(cpu, xc); 1524 #endif 1525 1526 /* Disable and free the queues */ 1527 xive_cleanup_cpu_queues(cpu, xc); 1528 } 1529 1530 void xive_shutdown(void) 1531 { 1532 xive_ops->shutdown(); 1533 } 1534 1535 bool __init xive_core_init(struct device_node *np, const struct xive_ops *ops, 1536 void __iomem *area, u32 offset, u8 max_prio) 1537 { 1538 xive_tima = area; 1539 xive_tima_offset = offset; 1540 xive_ops = ops; 1541 xive_irq_priority = max_prio; 1542 1543 ppc_md.get_irq = xive_get_irq; 1544 __xive_enabled = true; 1545 1546 pr_devel("Initializing host..\n"); 1547 xive_init_host(np); 1548 1549 pr_devel("Initializing boot CPU..\n"); 1550 1551 /* Allocate per-CPU data and queues */ 1552 xive_prepare_cpu(smp_processor_id()); 1553 1554 /* Get ready for interrupts */ 1555 xive_setup_cpu(); 1556 1557 pr_info("Interrupt handling initialized with %s backend\n", 1558 xive_ops->name); 1559 pr_info("Using priority %d for all interrupts\n", max_prio); 1560 1561 return true; 1562 } 1563 1564 __be32 *xive_queue_page_alloc(unsigned int cpu, u32 queue_shift) 1565 { 1566 unsigned int alloc_order; 1567 struct page *pages; 1568 __be32 *qpage; 1569 1570 alloc_order = xive_alloc_order(queue_shift); 1571 pages = alloc_pages_node(cpu_to_node(cpu), GFP_KERNEL, alloc_order); 1572 if (!pages) 1573 return ERR_PTR(-ENOMEM); 1574 qpage = (__be32 *)page_address(pages); 1575 memset(qpage, 0, 1 << queue_shift); 1576 1577 return qpage; 1578 } 1579 1580 static int __init xive_off(char *arg) 1581 { 1582 xive_cmdline_disabled = true; 1583 return 0; 1584 } 1585 __setup("xive=off", xive_off); 1586 1587 static void xive_debug_show_cpu(struct seq_file *m, int cpu) 1588 { 1589 struct xive_cpu *xc = per_cpu(xive_cpu, cpu); 1590 1591 seq_printf(m, "CPU %d:", cpu); 1592 if (xc) { 1593 seq_printf(m, "pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr); 1594 1595 #ifdef CONFIG_SMP 1596 { 1597 u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET); 1598 1599 seq_printf(m, "IPI=0x%08x PQ=%c%c ", xc->hw_ipi, 1600 val & XIVE_ESB_VAL_P ? 'P' : '-', 1601 val & XIVE_ESB_VAL_Q ? 'Q' : '-'); 1602 } 1603 #endif 1604 { 1605 struct xive_q *q = &xc->queue[xive_irq_priority]; 1606 u32 i0, i1, idx; 1607 1608 if (q->qpage) { 1609 idx = q->idx; 1610 i0 = be32_to_cpup(q->qpage + idx); 1611 idx = (idx + 1) & q->msk; 1612 i1 = be32_to_cpup(q->qpage + idx); 1613 seq_printf(m, "EQ idx=%d T=%d %08x %08x ...", 1614 q->idx, q->toggle, i0, i1); 1615 } 1616 } 1617 } 1618 seq_puts(m, "\n"); 1619 } 1620 1621 static void xive_debug_show_irq(struct seq_file *m, struct irq_data *d) 1622 { 1623 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 1624 int rc; 1625 u32 target; 1626 u8 prio; 1627 u32 lirq; 1628 struct xive_irq_data *xd; 1629 u64 val; 1630 1631 rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq); 1632 if (rc) { 1633 seq_printf(m, "IRQ 0x%08x : no config rc=%d\n", hw_irq, rc); 1634 return; 1635 } 1636 1637 seq_printf(m, "IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ", 1638 hw_irq, target, prio, lirq); 1639 1640 xd = irq_data_get_irq_handler_data(d); 1641 val = xive_esb_read(xd, XIVE_ESB_GET); 1642 seq_printf(m, "flags=%c%c%c PQ=%c%c", 1643 xd->flags & XIVE_IRQ_FLAG_STORE_EOI ? 'S' : ' ', 1644 xd->flags & XIVE_IRQ_FLAG_LSI ? 'L' : ' ', 1645 xd->flags & XIVE_IRQ_FLAG_H_INT_ESB ? 'H' : ' ', 1646 val & XIVE_ESB_VAL_P ? 'P' : '-', 1647 val & XIVE_ESB_VAL_Q ? 'Q' : '-'); 1648 seq_puts(m, "\n"); 1649 } 1650 1651 static int xive_core_debug_show(struct seq_file *m, void *private) 1652 { 1653 unsigned int i; 1654 struct irq_desc *desc; 1655 int cpu; 1656 1657 if (xive_ops->debug_show) 1658 xive_ops->debug_show(m, private); 1659 1660 for_each_possible_cpu(cpu) 1661 xive_debug_show_cpu(m, cpu); 1662 1663 for_each_irq_desc(i, desc) { 1664 struct irq_data *d = irq_desc_get_irq_data(desc); 1665 1666 if (d->domain == xive_irq_domain) 1667 xive_debug_show_irq(m, d); 1668 } 1669 return 0; 1670 } 1671 DEFINE_SHOW_ATTRIBUTE(xive_core_debug); 1672 1673 int xive_core_debug_init(void) 1674 { 1675 if (xive_enabled()) 1676 debugfs_create_file("xive", 0400, powerpc_debugfs_root, 1677 NULL, &xive_core_debug_fops); 1678 return 0; 1679 } 1680