1 /* 2 * Copyright 2011 IBM Corporation. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 * 9 */ 10 #include <linux/types.h> 11 #include <linux/threads.h> 12 #include <linux/kernel.h> 13 #include <linux/irq.h> 14 #include <linux/debugfs.h> 15 #include <linux/smp.h> 16 #include <linux/interrupt.h> 17 #include <linux/seq_file.h> 18 #include <linux/init.h> 19 #include <linux/cpu.h> 20 #include <linux/of.h> 21 #include <linux/slab.h> 22 #include <linux/spinlock.h> 23 24 #include <asm/prom.h> 25 #include <asm/io.h> 26 #include <asm/smp.h> 27 #include <asm/machdep.h> 28 #include <asm/irq.h> 29 #include <asm/errno.h> 30 #include <asm/rtas.h> 31 #include <asm/xics.h> 32 #include <asm/firmware.h> 33 34 /* Globals common to all ICP/ICS implementations */ 35 const struct icp_ops *icp_ops; 36 37 unsigned int xics_default_server = 0xff; 38 unsigned int xics_default_distrib_server = 0; 39 unsigned int xics_interrupt_server_size = 8; 40 41 DEFINE_PER_CPU(struct xics_cppr, xics_cppr); 42 43 struct irq_host *xics_host; 44 45 static LIST_HEAD(ics_list); 46 47 void xics_update_irq_servers(void) 48 { 49 int i, j; 50 struct device_node *np; 51 u32 ilen; 52 const u32 *ireg; 53 u32 hcpuid; 54 55 /* Find the server numbers for the boot cpu. */ 56 np = of_get_cpu_node(boot_cpuid, NULL); 57 BUG_ON(!np); 58 59 hcpuid = get_hard_smp_processor_id(boot_cpuid); 60 xics_default_server = xics_default_distrib_server = hcpuid; 61 62 pr_devel("xics: xics_default_server = 0x%x\n", xics_default_server); 63 64 ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen); 65 if (!ireg) { 66 of_node_put(np); 67 return; 68 } 69 70 i = ilen / sizeof(int); 71 72 /* Global interrupt distribution server is specified in the last 73 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last 74 * entry fom this property for current boot cpu id and use it as 75 * default distribution server 76 */ 77 for (j = 0; j < i; j += 2) { 78 if (ireg[j] == hcpuid) { 79 xics_default_distrib_server = ireg[j+1]; 80 break; 81 } 82 } 83 pr_devel("xics: xics_default_distrib_server = 0x%x\n", 84 xics_default_distrib_server); 85 of_node_put(np); 86 } 87 88 /* GIQ stuff, currently only supported on RTAS setups, will have 89 * to be sorted properly for bare metal 90 */ 91 void xics_set_cpu_giq(unsigned int gserver, unsigned int join) 92 { 93 #ifdef CONFIG_PPC_RTAS 94 int index; 95 int status; 96 97 if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL)) 98 return; 99 100 index = (1UL << xics_interrupt_server_size) - 1 - gserver; 101 102 status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join); 103 104 WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n", 105 GLOBAL_INTERRUPT_QUEUE, index, join, status); 106 #endif 107 } 108 109 void xics_setup_cpu(void) 110 { 111 icp_ops->set_priority(LOWEST_PRIORITY); 112 113 xics_set_cpu_giq(xics_default_distrib_server, 1); 114 } 115 116 void xics_mask_unknown_vec(unsigned int vec) 117 { 118 struct ics *ics; 119 120 pr_err("Interrupt 0x%x (real) is invalid, disabling it.\n", vec); 121 122 list_for_each_entry(ics, &ics_list, link) 123 ics->mask_unknown(ics, vec); 124 } 125 126 127 #ifdef CONFIG_SMP 128 129 static void xics_request_ipi(void) 130 { 131 unsigned int ipi; 132 133 ipi = irq_create_mapping(xics_host, XICS_IPI); 134 BUG_ON(ipi == NO_IRQ); 135 136 /* 137 * IPIs are marked IRQF_DISABLED as they must run with irqs 138 * disabled, and PERCPU. The handler was set in map. 139 */ 140 BUG_ON(request_irq(ipi, icp_ops->ipi_action, 141 IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL)); 142 } 143 144 int __init xics_smp_probe(void) 145 { 146 /* Setup cause_ipi callback based on which ICP is used */ 147 smp_ops->cause_ipi = icp_ops->cause_ipi; 148 149 /* Register all the IPIs */ 150 xics_request_ipi(); 151 152 return cpumask_weight(cpu_possible_mask); 153 } 154 155 #endif /* CONFIG_SMP */ 156 157 void xics_teardown_cpu(void) 158 { 159 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr); 160 161 /* 162 * we have to reset the cppr index to 0 because we're 163 * not going to return from the IPI 164 */ 165 os_cppr->index = 0; 166 icp_ops->set_priority(0); 167 icp_ops->teardown_cpu(); 168 } 169 170 void xics_kexec_teardown_cpu(int secondary) 171 { 172 xics_teardown_cpu(); 173 174 icp_ops->flush_ipi(); 175 176 /* 177 * Some machines need to have at least one cpu in the GIQ, 178 * so leave the master cpu in the group. 179 */ 180 if (secondary) 181 xics_set_cpu_giq(xics_default_distrib_server, 0); 182 } 183 184 185 #ifdef CONFIG_HOTPLUG_CPU 186 187 /* Interrupts are disabled. */ 188 void xics_migrate_irqs_away(void) 189 { 190 int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id(); 191 unsigned int irq, virq; 192 193 /* If we used to be the default server, move to the new "boot_cpuid" */ 194 if (hw_cpu == xics_default_server) 195 xics_update_irq_servers(); 196 197 /* Reject any interrupt that was queued to us... */ 198 icp_ops->set_priority(0); 199 200 /* Remove ourselves from the global interrupt queue */ 201 xics_set_cpu_giq(xics_default_distrib_server, 0); 202 203 /* Allow IPIs again... */ 204 icp_ops->set_priority(DEFAULT_PRIORITY); 205 206 for_each_irq(virq) { 207 struct irq_desc *desc; 208 struct irq_chip *chip; 209 long server; 210 unsigned long flags; 211 struct ics *ics; 212 213 /* We can't set affinity on ISA interrupts */ 214 if (virq < NUM_ISA_INTERRUPTS) 215 continue; 216 if (!virq_is_host(virq, xics_host)) 217 continue; 218 irq = (unsigned int)virq_to_hw(virq); 219 /* We need to get IPIs still. */ 220 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) 221 continue; 222 desc = irq_to_desc(virq); 223 /* We only need to migrate enabled IRQS */ 224 if (!desc || !desc->action) 225 continue; 226 chip = irq_desc_get_chip(desc); 227 if (!chip || !chip->irq_set_affinity) 228 continue; 229 230 raw_spin_lock_irqsave(&desc->lock, flags); 231 232 /* Locate interrupt server */ 233 server = -1; 234 ics = irq_get_chip_data(virq); 235 if (ics) 236 server = ics->get_server(ics, irq); 237 if (server < 0) { 238 printk(KERN_ERR "%s: Can't find server for irq %d\n", 239 __func__, irq); 240 goto unlock; 241 } 242 243 /* We only support delivery to all cpus or to one cpu. 244 * The irq has to be migrated only in the single cpu 245 * case. 246 */ 247 if (server != hw_cpu) 248 goto unlock; 249 250 /* This is expected during cpu offline. */ 251 if (cpu_online(cpu)) 252 pr_warning("IRQ %u affinity broken off cpu %u\n", 253 virq, cpu); 254 255 /* Reset affinity to all cpus */ 256 raw_spin_unlock_irqrestore(&desc->lock, flags); 257 irq_set_affinity(virq, cpu_all_mask); 258 continue; 259 unlock: 260 raw_spin_unlock_irqrestore(&desc->lock, flags); 261 } 262 } 263 #endif /* CONFIG_HOTPLUG_CPU */ 264 265 #ifdef CONFIG_SMP 266 /* 267 * For the moment we only implement delivery to all cpus or one cpu. 268 * 269 * If the requested affinity is cpu_all_mask, we set global affinity. 270 * If not we set it to the first cpu in the mask, even if multiple cpus 271 * are set. This is so things like irqbalance (which set core and package 272 * wide affinities) do the right thing. 273 * 274 * We need to fix this to implement support for the links 275 */ 276 int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask, 277 unsigned int strict_check) 278 { 279 280 if (!distribute_irqs) 281 return xics_default_server; 282 283 if (!cpumask_subset(cpu_possible_mask, cpumask)) { 284 int server = cpumask_first_and(cpu_online_mask, cpumask); 285 286 if (server < nr_cpu_ids) 287 return get_hard_smp_processor_id(server); 288 289 if (strict_check) 290 return -1; 291 } 292 293 /* 294 * Workaround issue with some versions of JS20 firmware that 295 * deliver interrupts to cpus which haven't been started. This 296 * happens when using the maxcpus= boot option. 297 */ 298 if (cpumask_equal(cpu_online_mask, cpu_present_mask)) 299 return xics_default_distrib_server; 300 301 return xics_default_server; 302 } 303 #endif /* CONFIG_SMP */ 304 305 static int xics_host_match(struct irq_host *h, struct device_node *node) 306 { 307 struct ics *ics; 308 309 list_for_each_entry(ics, &ics_list, link) 310 if (ics->host_match(ics, node)) 311 return 1; 312 313 return 0; 314 } 315 316 /* Dummies */ 317 static void xics_ipi_unmask(struct irq_data *d) { } 318 static void xics_ipi_mask(struct irq_data *d) { } 319 320 static struct irq_chip xics_ipi_chip = { 321 .name = "XICS", 322 .irq_eoi = NULL, /* Patched at init time */ 323 .irq_mask = xics_ipi_mask, 324 .irq_unmask = xics_ipi_unmask, 325 }; 326 327 static int xics_host_map(struct irq_host *h, unsigned int virq, 328 irq_hw_number_t hw) 329 { 330 struct ics *ics; 331 332 pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw); 333 334 /* Insert the interrupt mapping into the radix tree for fast lookup */ 335 irq_radix_revmap_insert(xics_host, virq, hw); 336 337 /* They aren't all level sensitive but we just don't really know */ 338 irq_set_status_flags(virq, IRQ_LEVEL); 339 340 /* Don't call into ICS for IPIs */ 341 if (hw == XICS_IPI) { 342 irq_set_chip_and_handler(virq, &xics_ipi_chip, 343 handle_percpu_irq); 344 return 0; 345 } 346 347 /* Let the ICS setup the chip data */ 348 list_for_each_entry(ics, &ics_list, link) 349 if (ics->map(ics, virq) == 0) 350 return 0; 351 352 return -EINVAL; 353 } 354 355 static int xics_host_xlate(struct irq_host *h, struct device_node *ct, 356 const u32 *intspec, unsigned int intsize, 357 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 358 359 { 360 /* Current xics implementation translates everything 361 * to level. It is not technically right for MSIs but this 362 * is irrelevant at this point. We might get smarter in the future 363 */ 364 *out_hwirq = intspec[0]; 365 *out_flags = IRQ_TYPE_LEVEL_LOW; 366 367 return 0; 368 } 369 370 static struct irq_host_ops xics_host_ops = { 371 .match = xics_host_match, 372 .map = xics_host_map, 373 .xlate = xics_host_xlate, 374 }; 375 376 static void __init xics_init_host(void) 377 { 378 xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, &xics_host_ops, 379 XICS_IRQ_SPURIOUS); 380 BUG_ON(xics_host == NULL); 381 irq_set_default_host(xics_host); 382 } 383 384 void __init xics_register_ics(struct ics *ics) 385 { 386 list_add(&ics->link, &ics_list); 387 } 388 389 static void __init xics_get_server_size(void) 390 { 391 struct device_node *np; 392 const u32 *isize; 393 394 /* We fetch the interrupt server size from the first ICS node 395 * we find if any 396 */ 397 np = of_find_compatible_node(NULL, NULL, "ibm,ppc-xics"); 398 if (!np) 399 return; 400 isize = of_get_property(np, "ibm,interrupt-server#-size", NULL); 401 if (!isize) 402 return; 403 xics_interrupt_server_size = *isize; 404 of_node_put(np); 405 } 406 407 void __init xics_init(void) 408 { 409 int rc = -1; 410 411 /* Fist locate ICP */ 412 if (firmware_has_feature(FW_FEATURE_LPAR)) 413 rc = icp_hv_init(); 414 if (rc < 0) 415 rc = icp_native_init(); 416 if (rc < 0) { 417 pr_warning("XICS: Cannot find a Presentation Controller !\n"); 418 return; 419 } 420 421 /* Copy get_irq callback over to ppc_md */ 422 ppc_md.get_irq = icp_ops->get_irq; 423 424 /* Patch up IPI chip EOI */ 425 xics_ipi_chip.irq_eoi = icp_ops->eoi; 426 427 /* Now locate ICS */ 428 rc = ics_rtas_init(); 429 if (rc < 0) 430 rc = ics_opal_init(); 431 if (rc < 0) 432 pr_warning("XICS: Cannot find a Source Controller !\n"); 433 434 /* Initialize common bits */ 435 xics_get_server_size(); 436 xics_update_irq_servers(); 437 xics_init_host(); 438 xics_setup_cpu(); 439 } 440