1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Common routines for Tundra Semiconductor TSI108 host bridge. 4 * 5 * 2004-2005 (c) Tundra Semiconductor Corp. 6 * Author: Alex Bounine (alexandreb@tundra.com) 7 * Author: Roy Zang (tie-fei.zang@freescale.com) 8 * Add pci interrupt router host 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/pci.h> 14 #include <linux/irq.h> 15 #include <linux/interrupt.h> 16 17 #include <asm/byteorder.h> 18 #include <asm/io.h> 19 #include <asm/irq.h> 20 #include <linux/uaccess.h> 21 #include <asm/machdep.h> 22 #include <asm/pci-bridge.h> 23 #include <asm/tsi108.h> 24 #include <asm/tsi108_pci.h> 25 #include <asm/tsi108_irq.h> 26 #include <asm/prom.h> 27 28 #undef DEBUG 29 #ifdef DEBUG 30 #define DBG(x...) printk(x) 31 #else 32 #define DBG(x...) 33 #endif 34 35 #define tsi_mk_config_addr(bus, devfunc, offset) \ 36 ((((bus)<<16) | ((devfunc)<<8) | (offset & 0xfc)) + tsi108_pci_cfg_base) 37 38 u32 tsi108_pci_cfg_base; 39 static u32 tsi108_pci_cfg_phys; 40 u32 tsi108_csr_vir_base; 41 static struct irq_domain *pci_irq_host; 42 43 extern u32 get_vir_csrbase(void); 44 extern u32 tsi108_read_reg(u32 reg_offset); 45 extern void tsi108_write_reg(u32 reg_offset, u32 val); 46 47 int 48 tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc, 49 int offset, int len, u32 val) 50 { 51 volatile unsigned char *cfg_addr; 52 struct pci_controller *hose = pci_bus_to_host(bus); 53 54 if (ppc_md.pci_exclude_device) 55 if (ppc_md.pci_exclude_device(hose, bus->number, devfunc)) 56 return PCIBIOS_DEVICE_NOT_FOUND; 57 58 cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number, 59 devfunc, offset) | 60 (offset & 0x03)); 61 62 #ifdef DEBUG 63 printk("PCI CFG write : "); 64 printk("%d:0x%x:0x%x ", bus->number, devfunc, offset); 65 printk("%d ADDR=0x%08x ", len, (uint) cfg_addr); 66 printk("data = 0x%08x\n", val); 67 #endif 68 69 switch (len) { 70 case 1: 71 out_8((u8 *) cfg_addr, val); 72 break; 73 case 2: 74 out_le16((u16 *) cfg_addr, val); 75 break; 76 default: 77 out_le32((u32 *) cfg_addr, val); 78 break; 79 } 80 81 return PCIBIOS_SUCCESSFUL; 82 } 83 84 void tsi108_clear_pci_error(u32 pci_cfg_base) 85 { 86 u32 err_stat, err_addr, pci_stat; 87 88 /* 89 * Quietly clear PB and PCI error flags set as result 90 * of PCI/X configuration read requests. 91 */ 92 93 /* Read PB Error Log Registers */ 94 95 err_stat = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS); 96 err_addr = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_AERR); 97 98 if (err_stat & TSI108_PB_ERRCS_ES) { 99 /* Clear error flag */ 100 tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS, 101 TSI108_PB_ERRCS_ES); 102 103 /* Clear read error reported in PB_ISR */ 104 tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ISR, 105 TSI108_PB_ISR_PBS_RD_ERR); 106 107 /* Clear PCI/X bus cfg errors if applicable */ 108 if ((err_addr & 0xFF000000) == pci_cfg_base) { 109 pci_stat = 110 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR); 111 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR, 112 pci_stat); 113 } 114 } 115 116 return; 117 } 118 119 #define __tsi108_read_pci_config(x, addr, op) \ 120 __asm__ __volatile__( \ 121 " "op" %0,0,%1\n" \ 122 "1: eieio\n" \ 123 "2:\n" \ 124 ".section .fixup,\"ax\"\n" \ 125 "3: li %0,-1\n" \ 126 " b 2b\n" \ 127 ".previous\n" \ 128 EX_TABLE(1b, 3b) \ 129 : "=r"(x) : "r"(addr)) 130 131 int 132 tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 133 int len, u32 * val) 134 { 135 volatile unsigned char *cfg_addr; 136 struct pci_controller *hose = pci_bus_to_host(bus); 137 u32 temp; 138 139 if (ppc_md.pci_exclude_device) 140 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 141 return PCIBIOS_DEVICE_NOT_FOUND; 142 143 cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number, 144 devfn, 145 offset) | (offset & 146 0x03)); 147 148 switch (len) { 149 case 1: 150 __tsi108_read_pci_config(temp, cfg_addr, "lbzx"); 151 break; 152 case 2: 153 __tsi108_read_pci_config(temp, cfg_addr, "lhbrx"); 154 break; 155 default: 156 __tsi108_read_pci_config(temp, cfg_addr, "lwbrx"); 157 break; 158 } 159 160 *val = temp; 161 162 #ifdef DEBUG 163 if ((0xFFFFFFFF != temp) && (0xFFFF != temp) && (0xFF != temp)) { 164 printk("PCI CFG read : "); 165 printk("%d:0x%x:0x%x ", bus->number, devfn, offset); 166 printk("%d ADDR=0x%08x ", len, (uint) cfg_addr); 167 printk("data = 0x%x\n", *val); 168 } 169 #endif 170 return PCIBIOS_SUCCESSFUL; 171 } 172 173 void tsi108_clear_pci_cfg_error(void) 174 { 175 tsi108_clear_pci_error(tsi108_pci_cfg_phys); 176 } 177 178 static struct pci_ops tsi108_direct_pci_ops = { 179 .read = tsi108_direct_read_config, 180 .write = tsi108_direct_write_config, 181 }; 182 183 int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary) 184 { 185 int len; 186 struct pci_controller *hose; 187 struct resource rsrc; 188 const int *bus_range; 189 int has_address = 0; 190 191 /* PCI Config mapping */ 192 tsi108_pci_cfg_base = (u32)ioremap(cfg_phys, TSI108_PCI_CFG_SIZE); 193 tsi108_pci_cfg_phys = cfg_phys; 194 DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __func__, 195 tsi108_pci_cfg_base); 196 197 /* Fetch host bridge registers address */ 198 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); 199 200 /* Get bus range if any */ 201 bus_range = of_get_property(dev, "bus-range", &len); 202 if (bus_range == NULL || len < 2 * sizeof(int)) { 203 printk(KERN_WARNING "Can't get bus-range for %pOF, assume" 204 " bus 0\n", dev); 205 } 206 207 hose = pcibios_alloc_controller(dev); 208 209 if (!hose) { 210 printk("PCI Host bridge init failed\n"); 211 return -ENOMEM; 212 } 213 214 hose->first_busno = bus_range ? bus_range[0] : 0; 215 hose->last_busno = bus_range ? bus_range[1] : 0xff; 216 217 (hose)->ops = &tsi108_direct_pci_ops; 218 219 printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. " 220 "Firmware bus number: %d->%d\n", 221 rsrc.start, hose->first_busno, hose->last_busno); 222 223 /* Interpret the "ranges" property */ 224 /* This also maps the I/O region and sets isa_io/mem_base */ 225 pci_process_bridge_OF_ranges(hose, dev, primary); 226 return 0; 227 } 228 229 /* 230 * Low level utility functions 231 */ 232 233 static void tsi108_pci_int_mask(u_int irq) 234 { 235 u_int irp_cfg; 236 int int_line = (irq - IRQ_PCI_INTAD_BASE); 237 238 irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL); 239 mb(); 240 irp_cfg |= (1 << int_line); /* INTx_DIR = output */ 241 irp_cfg &= ~(3 << (8 + (int_line * 2))); /* INTx_TYPE = unused */ 242 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg); 243 mb(); 244 irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL); 245 } 246 247 static void tsi108_pci_int_unmask(u_int irq) 248 { 249 u_int irp_cfg; 250 int int_line = (irq - IRQ_PCI_INTAD_BASE); 251 252 irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL); 253 mb(); 254 irp_cfg &= ~(1 << int_line); 255 irp_cfg |= (3 << (8 + (int_line * 2))); 256 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg); 257 mb(); 258 } 259 260 static void init_pci_source(void) 261 { 262 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, 263 0x0000ff00); 264 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE, 265 TSI108_PCI_IRP_ENABLE_P_INT); 266 mb(); 267 } 268 269 static inline unsigned int get_pci_source(void) 270 { 271 u_int temp = 0; 272 int irq = -1; 273 int i; 274 u_int pci_irp_stat; 275 static int mask = 0; 276 277 /* Read PCI/X block interrupt status register */ 278 pci_irp_stat = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT); 279 mb(); 280 281 if (pci_irp_stat & TSI108_PCI_IRP_STAT_P_INT) { 282 /* Process Interrupt from PCI bus INTA# - INTD# lines */ 283 temp = 284 tsi108_read_reg(TSI108_PCI_OFFSET + 285 TSI108_PCI_IRP_INTAD) & 0xf; 286 mb(); 287 for (i = 0; i < 4; i++, mask++) { 288 if (temp & (1 << mask % 4)) { 289 irq = IRQ_PCI_INTA + mask % 4; 290 mask++; 291 break; 292 } 293 } 294 295 /* Disable interrupts from PCI block */ 296 temp = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE); 297 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE, 298 temp & ~TSI108_PCI_IRP_ENABLE_P_INT); 299 mb(); 300 (void)tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE); 301 mb(); 302 } 303 #ifdef DEBUG 304 else { 305 printk("TSI108_PIC: error in TSI108_PCI_IRP_STAT\n"); 306 pci_irp_stat = 307 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT); 308 temp = 309 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_INTAD); 310 mb(); 311 printk(">> stat=0x%08x intad=0x%08x ", pci_irp_stat, temp); 312 temp = 313 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL); 314 mb(); 315 printk("cfg_ctl=0x%08x ", temp); 316 temp = 317 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE); 318 mb(); 319 printk("irp_enable=0x%08x\n", temp); 320 } 321 #endif /* end of DEBUG */ 322 323 return irq; 324 } 325 326 327 /* 328 * Linux descriptor level callbacks 329 */ 330 331 static void tsi108_pci_irq_unmask(struct irq_data *d) 332 { 333 tsi108_pci_int_unmask(d->irq); 334 335 /* Enable interrupts from PCI block */ 336 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE, 337 tsi108_read_reg(TSI108_PCI_OFFSET + 338 TSI108_PCI_IRP_ENABLE) | 339 TSI108_PCI_IRP_ENABLE_P_INT); 340 mb(); 341 } 342 343 static void tsi108_pci_irq_mask(struct irq_data *d) 344 { 345 tsi108_pci_int_mask(d->irq); 346 } 347 348 static void tsi108_pci_irq_ack(struct irq_data *d) 349 { 350 tsi108_pci_int_mask(d->irq); 351 } 352 353 /* 354 * Interrupt controller descriptor for cascaded PCI interrupt controller. 355 */ 356 357 static struct irq_chip tsi108_pci_irq = { 358 .name = "tsi108_PCI_int", 359 .irq_mask = tsi108_pci_irq_mask, 360 .irq_ack = tsi108_pci_irq_ack, 361 .irq_unmask = tsi108_pci_irq_unmask, 362 }; 363 364 static int pci_irq_host_xlate(struct irq_domain *h, struct device_node *ct, 365 const u32 *intspec, unsigned int intsize, 366 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 367 { 368 *out_hwirq = intspec[0]; 369 *out_flags = IRQ_TYPE_LEVEL_HIGH; 370 return 0; 371 } 372 373 static int pci_irq_host_map(struct irq_domain *h, unsigned int virq, 374 irq_hw_number_t hw) 375 { unsigned int irq; 376 DBG("%s(%d, 0x%lx)\n", __func__, virq, hw); 377 if ((virq >= 1) && (virq <= 4)){ 378 irq = virq + IRQ_PCI_INTAD_BASE - 1; 379 irq_set_status_flags(irq, IRQ_LEVEL); 380 irq_set_chip(irq, &tsi108_pci_irq); 381 } 382 return 0; 383 } 384 385 static const struct irq_domain_ops pci_irq_domain_ops = { 386 .map = pci_irq_host_map, 387 .xlate = pci_irq_host_xlate, 388 }; 389 390 /* 391 * Exported functions 392 */ 393 394 /* 395 * The Tsi108 PCI interrupts initialization routine. 396 * 397 * The INTA# - INTD# interrupts on the PCI bus are reported by the PCI block 398 * to the MPIC using single interrupt source (IRQ_TSI108_PCI). Therefore the 399 * PCI block has to be treated as a cascaded interrupt controller connected 400 * to the MPIC. 401 */ 402 403 void __init tsi108_pci_int_init(struct device_node *node) 404 { 405 DBG("Tsi108_pci_int_init: initializing PCI interrupts\n"); 406 407 pci_irq_host = irq_domain_add_legacy(node, NR_IRQS_LEGACY, 0, 0, 408 &pci_irq_domain_ops, NULL); 409 if (pci_irq_host == NULL) { 410 printk(KERN_ERR "pci_irq_host: failed to allocate irq domain!\n"); 411 return; 412 } 413 414 init_pci_source(); 415 } 416 417 void tsi108_irq_cascade(struct irq_desc *desc) 418 { 419 struct irq_chip *chip = irq_desc_get_chip(desc); 420 unsigned int cascade_irq = get_pci_source(); 421 422 if (cascade_irq) 423 generic_handle_irq(cascade_irq); 424 425 chip->irq_eoi(&desc->irq_data); 426 } 427