12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
236ca09beSDongsheng.wang@freescale.com /*
336ca09beSDongsheng.wang@freescale.com * MPIC timer driver
436ca09beSDongsheng.wang@freescale.com *
536ca09beSDongsheng.wang@freescale.com * Copyright 2013 Freescale Semiconductor, Inc.
636ca09beSDongsheng.wang@freescale.com * Author: Dongsheng Wang <Dongsheng.Wang@freescale.com>
736ca09beSDongsheng.wang@freescale.com * Li Yang <leoli@freescale.com>
836ca09beSDongsheng.wang@freescale.com */
936ca09beSDongsheng.wang@freescale.com
1036ca09beSDongsheng.wang@freescale.com #include <linux/kernel.h>
1136ca09beSDongsheng.wang@freescale.com #include <linux/init.h>
1236ca09beSDongsheng.wang@freescale.com #include <linux/module.h>
1336ca09beSDongsheng.wang@freescale.com #include <linux/errno.h>
1436ca09beSDongsheng.wang@freescale.com #include <linux/mm.h>
1536ca09beSDongsheng.wang@freescale.com #include <linux/interrupt.h>
1636ca09beSDongsheng.wang@freescale.com #include <linux/slab.h>
1736ca09beSDongsheng.wang@freescale.com #include <linux/of.h>
1826a2056eSRob Herring #include <linux/of_address.h>
1926a2056eSRob Herring #include <linux/of_irq.h>
2036ca09beSDongsheng.wang@freescale.com #include <linux/syscore_ops.h>
2136ca09beSDongsheng.wang@freescale.com #include <sysdev/fsl_soc.h>
2236ca09beSDongsheng.wang@freescale.com #include <asm/io.h>
2336ca09beSDongsheng.wang@freescale.com
2436ca09beSDongsheng.wang@freescale.com #include <asm/mpic_timer.h>
2536ca09beSDongsheng.wang@freescale.com
2636ca09beSDongsheng.wang@freescale.com #define FSL_GLOBAL_TIMER 0x1
2736ca09beSDongsheng.wang@freescale.com
2836ca09beSDongsheng.wang@freescale.com /* Clock Ratio
2936ca09beSDongsheng.wang@freescale.com * Divide by 64 0x00000300
3036ca09beSDongsheng.wang@freescale.com * Divide by 32 0x00000200
3136ca09beSDongsheng.wang@freescale.com * Divide by 16 0x00000100
3236ca09beSDongsheng.wang@freescale.com * Divide by 8 0x00000000 (Hardware default div)
3336ca09beSDongsheng.wang@freescale.com */
3436ca09beSDongsheng.wang@freescale.com #define MPIC_TIMER_TCR_CLKDIV 0x00000300
3536ca09beSDongsheng.wang@freescale.com
3636ca09beSDongsheng.wang@freescale.com #define MPIC_TIMER_TCR_ROVR_OFFSET 24
3736ca09beSDongsheng.wang@freescale.com
3836ca09beSDongsheng.wang@freescale.com #define TIMER_STOP 0x80000000
390fd79588SWang Dongsheng #define GTCCR_TOG 0x80000000
4036ca09beSDongsheng.wang@freescale.com #define TIMERS_PER_GROUP 4
4136ca09beSDongsheng.wang@freescale.com #define MAX_TICKS (~0U >> 1)
4236ca09beSDongsheng.wang@freescale.com #define MAX_TICKS_CASCADE (~0U)
4336ca09beSDongsheng.wang@freescale.com #define TIMER_OFFSET(num) (1 << (TIMERS_PER_GROUP - 1 - num))
4436ca09beSDongsheng.wang@freescale.com
4536ca09beSDongsheng.wang@freescale.com struct timer_regs {
4636ca09beSDongsheng.wang@freescale.com u32 gtccr;
4736ca09beSDongsheng.wang@freescale.com u32 res0[3];
4836ca09beSDongsheng.wang@freescale.com u32 gtbcr;
4936ca09beSDongsheng.wang@freescale.com u32 res1[3];
5036ca09beSDongsheng.wang@freescale.com u32 gtvpr;
5136ca09beSDongsheng.wang@freescale.com u32 res2[3];
5236ca09beSDongsheng.wang@freescale.com u32 gtdr;
5336ca09beSDongsheng.wang@freescale.com u32 res3[3];
5436ca09beSDongsheng.wang@freescale.com };
5536ca09beSDongsheng.wang@freescale.com
5636ca09beSDongsheng.wang@freescale.com struct cascade_priv {
5736ca09beSDongsheng.wang@freescale.com u32 tcr_value; /* TCR register: CASC & ROVR value */
5836ca09beSDongsheng.wang@freescale.com unsigned int cascade_map; /* cascade map */
5936ca09beSDongsheng.wang@freescale.com unsigned int timer_num; /* cascade control timer */
6036ca09beSDongsheng.wang@freescale.com };
6136ca09beSDongsheng.wang@freescale.com
6236ca09beSDongsheng.wang@freescale.com struct timer_group_priv {
6336ca09beSDongsheng.wang@freescale.com struct timer_regs __iomem *regs;
6436ca09beSDongsheng.wang@freescale.com struct mpic_timer timer[TIMERS_PER_GROUP];
6536ca09beSDongsheng.wang@freescale.com struct list_head node;
6636ca09beSDongsheng.wang@freescale.com unsigned int timerfreq;
6736ca09beSDongsheng.wang@freescale.com unsigned int idle;
6836ca09beSDongsheng.wang@freescale.com unsigned int flags;
6936ca09beSDongsheng.wang@freescale.com spinlock_t lock;
7036ca09beSDongsheng.wang@freescale.com void __iomem *group_tcr;
7136ca09beSDongsheng.wang@freescale.com };
7236ca09beSDongsheng.wang@freescale.com
7336ca09beSDongsheng.wang@freescale.com static struct cascade_priv cascade_timer[] = {
7436ca09beSDongsheng.wang@freescale.com /* cascade timer 0 and 1 */
7536ca09beSDongsheng.wang@freescale.com {0x1, 0xc, 0x1},
7636ca09beSDongsheng.wang@freescale.com /* cascade timer 1 and 2 */
7736ca09beSDongsheng.wang@freescale.com {0x2, 0x6, 0x2},
7836ca09beSDongsheng.wang@freescale.com /* cascade timer 2 and 3 */
7936ca09beSDongsheng.wang@freescale.com {0x4, 0x3, 0x3}
8036ca09beSDongsheng.wang@freescale.com };
8136ca09beSDongsheng.wang@freescale.com
8236ca09beSDongsheng.wang@freescale.com static LIST_HEAD(timer_group_list);
8336ca09beSDongsheng.wang@freescale.com
convert_ticks_to_time(struct timer_group_priv * priv,const u64 ticks,time64_t * time)8436ca09beSDongsheng.wang@freescale.com static void convert_ticks_to_time(struct timer_group_priv *priv,
8511ed8c55SArnd Bergmann const u64 ticks, time64_t *time)
8636ca09beSDongsheng.wang@freescale.com {
8711ed8c55SArnd Bergmann *time = (u64)div_u64(ticks, priv->timerfreq);
8836ca09beSDongsheng.wang@freescale.com }
8936ca09beSDongsheng.wang@freescale.com
9036ca09beSDongsheng.wang@freescale.com /* the time set by the user is converted to "ticks" */
convert_time_to_ticks(struct timer_group_priv * priv,time64_t time,u64 * ticks)9136ca09beSDongsheng.wang@freescale.com static int convert_time_to_ticks(struct timer_group_priv *priv,
9211ed8c55SArnd Bergmann time64_t time, u64 *ticks)
9336ca09beSDongsheng.wang@freescale.com {
9436ca09beSDongsheng.wang@freescale.com u64 max_value; /* prevent u64 overflow */
9536ca09beSDongsheng.wang@freescale.com
9636ca09beSDongsheng.wang@freescale.com max_value = div_u64(ULLONG_MAX, priv->timerfreq);
9736ca09beSDongsheng.wang@freescale.com
9811ed8c55SArnd Bergmann if (time > max_value)
9936ca09beSDongsheng.wang@freescale.com return -EINVAL;
10036ca09beSDongsheng.wang@freescale.com
10111ed8c55SArnd Bergmann *ticks = (u64)time * (u64)priv->timerfreq;
10236ca09beSDongsheng.wang@freescale.com
10336ca09beSDongsheng.wang@freescale.com return 0;
10436ca09beSDongsheng.wang@freescale.com }
10536ca09beSDongsheng.wang@freescale.com
10636ca09beSDongsheng.wang@freescale.com /* detect whether there is a cascade timer available */
detect_idle_cascade_timer(struct timer_group_priv * priv)10736ca09beSDongsheng.wang@freescale.com static struct mpic_timer *detect_idle_cascade_timer(
10836ca09beSDongsheng.wang@freescale.com struct timer_group_priv *priv)
10936ca09beSDongsheng.wang@freescale.com {
11036ca09beSDongsheng.wang@freescale.com struct cascade_priv *casc_priv;
11136ca09beSDongsheng.wang@freescale.com unsigned int map;
11236ca09beSDongsheng.wang@freescale.com unsigned int array_size = ARRAY_SIZE(cascade_timer);
11336ca09beSDongsheng.wang@freescale.com unsigned int num;
11436ca09beSDongsheng.wang@freescale.com unsigned int i;
11536ca09beSDongsheng.wang@freescale.com unsigned long flags;
11636ca09beSDongsheng.wang@freescale.com
11736ca09beSDongsheng.wang@freescale.com casc_priv = cascade_timer;
11836ca09beSDongsheng.wang@freescale.com for (i = 0; i < array_size; i++) {
11936ca09beSDongsheng.wang@freescale.com spin_lock_irqsave(&priv->lock, flags);
12036ca09beSDongsheng.wang@freescale.com map = casc_priv->cascade_map & priv->idle;
12136ca09beSDongsheng.wang@freescale.com if (map == casc_priv->cascade_map) {
12236ca09beSDongsheng.wang@freescale.com num = casc_priv->timer_num;
12336ca09beSDongsheng.wang@freescale.com priv->timer[num].cascade_handle = casc_priv;
12436ca09beSDongsheng.wang@freescale.com
12536ca09beSDongsheng.wang@freescale.com /* set timer busy */
12636ca09beSDongsheng.wang@freescale.com priv->idle &= ~casc_priv->cascade_map;
12736ca09beSDongsheng.wang@freescale.com spin_unlock_irqrestore(&priv->lock, flags);
12836ca09beSDongsheng.wang@freescale.com return &priv->timer[num];
12936ca09beSDongsheng.wang@freescale.com }
13036ca09beSDongsheng.wang@freescale.com spin_unlock_irqrestore(&priv->lock, flags);
13136ca09beSDongsheng.wang@freescale.com casc_priv++;
13236ca09beSDongsheng.wang@freescale.com }
13336ca09beSDongsheng.wang@freescale.com
13436ca09beSDongsheng.wang@freescale.com return NULL;
13536ca09beSDongsheng.wang@freescale.com }
13636ca09beSDongsheng.wang@freescale.com
set_cascade_timer(struct timer_group_priv * priv,u64 ticks,unsigned int num)13736ca09beSDongsheng.wang@freescale.com static int set_cascade_timer(struct timer_group_priv *priv, u64 ticks,
13836ca09beSDongsheng.wang@freescale.com unsigned int num)
13936ca09beSDongsheng.wang@freescale.com {
14036ca09beSDongsheng.wang@freescale.com struct cascade_priv *casc_priv;
14136ca09beSDongsheng.wang@freescale.com u32 tcr;
14236ca09beSDongsheng.wang@freescale.com u32 tmp_ticks;
14336ca09beSDongsheng.wang@freescale.com u32 rem_ticks;
14436ca09beSDongsheng.wang@freescale.com
14536ca09beSDongsheng.wang@freescale.com /* set group tcr reg for cascade */
14636ca09beSDongsheng.wang@freescale.com casc_priv = priv->timer[num].cascade_handle;
14736ca09beSDongsheng.wang@freescale.com if (!casc_priv)
14836ca09beSDongsheng.wang@freescale.com return -EINVAL;
14936ca09beSDongsheng.wang@freescale.com
15036ca09beSDongsheng.wang@freescale.com tcr = casc_priv->tcr_value |
15136ca09beSDongsheng.wang@freescale.com (casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET);
15236ca09beSDongsheng.wang@freescale.com setbits32(priv->group_tcr, tcr);
15336ca09beSDongsheng.wang@freescale.com
15436ca09beSDongsheng.wang@freescale.com tmp_ticks = div_u64_rem(ticks, MAX_TICKS_CASCADE, &rem_ticks);
15536ca09beSDongsheng.wang@freescale.com
15636ca09beSDongsheng.wang@freescale.com out_be32(&priv->regs[num].gtccr, 0);
15736ca09beSDongsheng.wang@freescale.com out_be32(&priv->regs[num].gtbcr, tmp_ticks | TIMER_STOP);
15836ca09beSDongsheng.wang@freescale.com
15936ca09beSDongsheng.wang@freescale.com out_be32(&priv->regs[num - 1].gtccr, 0);
16036ca09beSDongsheng.wang@freescale.com out_be32(&priv->regs[num - 1].gtbcr, rem_ticks);
16136ca09beSDongsheng.wang@freescale.com
16236ca09beSDongsheng.wang@freescale.com return 0;
16336ca09beSDongsheng.wang@freescale.com }
16436ca09beSDongsheng.wang@freescale.com
get_cascade_timer(struct timer_group_priv * priv,u64 ticks)16536ca09beSDongsheng.wang@freescale.com static struct mpic_timer *get_cascade_timer(struct timer_group_priv *priv,
16636ca09beSDongsheng.wang@freescale.com u64 ticks)
16736ca09beSDongsheng.wang@freescale.com {
16836ca09beSDongsheng.wang@freescale.com struct mpic_timer *allocated_timer;
16936ca09beSDongsheng.wang@freescale.com
17036ca09beSDongsheng.wang@freescale.com /* Two cascade timers: Support the maximum time */
17136ca09beSDongsheng.wang@freescale.com const u64 max_ticks = (u64)MAX_TICKS * (u64)MAX_TICKS_CASCADE;
17236ca09beSDongsheng.wang@freescale.com int ret;
17336ca09beSDongsheng.wang@freescale.com
17436ca09beSDongsheng.wang@freescale.com if (ticks > max_ticks)
17536ca09beSDongsheng.wang@freescale.com return NULL;
17636ca09beSDongsheng.wang@freescale.com
17736ca09beSDongsheng.wang@freescale.com /* detect idle timer */
17836ca09beSDongsheng.wang@freescale.com allocated_timer = detect_idle_cascade_timer(priv);
17936ca09beSDongsheng.wang@freescale.com if (!allocated_timer)
18036ca09beSDongsheng.wang@freescale.com return NULL;
18136ca09beSDongsheng.wang@freescale.com
18236ca09beSDongsheng.wang@freescale.com /* set ticks to timer */
18336ca09beSDongsheng.wang@freescale.com ret = set_cascade_timer(priv, ticks, allocated_timer->num);
18436ca09beSDongsheng.wang@freescale.com if (ret < 0)
18536ca09beSDongsheng.wang@freescale.com return NULL;
18636ca09beSDongsheng.wang@freescale.com
18736ca09beSDongsheng.wang@freescale.com return allocated_timer;
18836ca09beSDongsheng.wang@freescale.com }
18936ca09beSDongsheng.wang@freescale.com
get_timer(time64_t time)19011ed8c55SArnd Bergmann static struct mpic_timer *get_timer(time64_t time)
19136ca09beSDongsheng.wang@freescale.com {
19236ca09beSDongsheng.wang@freescale.com struct timer_group_priv *priv;
19336ca09beSDongsheng.wang@freescale.com struct mpic_timer *timer;
19436ca09beSDongsheng.wang@freescale.com
19536ca09beSDongsheng.wang@freescale.com u64 ticks;
19636ca09beSDongsheng.wang@freescale.com unsigned int num;
19736ca09beSDongsheng.wang@freescale.com unsigned int i;
19836ca09beSDongsheng.wang@freescale.com unsigned long flags;
19936ca09beSDongsheng.wang@freescale.com int ret;
20036ca09beSDongsheng.wang@freescale.com
20136ca09beSDongsheng.wang@freescale.com list_for_each_entry(priv, &timer_group_list, node) {
20236ca09beSDongsheng.wang@freescale.com ret = convert_time_to_ticks(priv, time, &ticks);
20336ca09beSDongsheng.wang@freescale.com if (ret < 0)
20436ca09beSDongsheng.wang@freescale.com return NULL;
20536ca09beSDongsheng.wang@freescale.com
20636ca09beSDongsheng.wang@freescale.com if (ticks > MAX_TICKS) {
20736ca09beSDongsheng.wang@freescale.com if (!(priv->flags & FSL_GLOBAL_TIMER))
20836ca09beSDongsheng.wang@freescale.com return NULL;
20936ca09beSDongsheng.wang@freescale.com
21036ca09beSDongsheng.wang@freescale.com timer = get_cascade_timer(priv, ticks);
21136ca09beSDongsheng.wang@freescale.com if (!timer)
21236ca09beSDongsheng.wang@freescale.com continue;
21336ca09beSDongsheng.wang@freescale.com
21436ca09beSDongsheng.wang@freescale.com return timer;
21536ca09beSDongsheng.wang@freescale.com }
21636ca09beSDongsheng.wang@freescale.com
21736ca09beSDongsheng.wang@freescale.com for (i = 0; i < TIMERS_PER_GROUP; i++) {
21836ca09beSDongsheng.wang@freescale.com /* one timer: Reverse allocation */
21936ca09beSDongsheng.wang@freescale.com num = TIMERS_PER_GROUP - 1 - i;
22036ca09beSDongsheng.wang@freescale.com spin_lock_irqsave(&priv->lock, flags);
22136ca09beSDongsheng.wang@freescale.com if (priv->idle & (1 << i)) {
22236ca09beSDongsheng.wang@freescale.com /* set timer busy */
22336ca09beSDongsheng.wang@freescale.com priv->idle &= ~(1 << i);
22436ca09beSDongsheng.wang@freescale.com /* set ticks & stop timer */
22536ca09beSDongsheng.wang@freescale.com out_be32(&priv->regs[num].gtbcr,
22636ca09beSDongsheng.wang@freescale.com ticks | TIMER_STOP);
22736ca09beSDongsheng.wang@freescale.com out_be32(&priv->regs[num].gtccr, 0);
22836ca09beSDongsheng.wang@freescale.com priv->timer[num].cascade_handle = NULL;
22936ca09beSDongsheng.wang@freescale.com spin_unlock_irqrestore(&priv->lock, flags);
23036ca09beSDongsheng.wang@freescale.com return &priv->timer[num];
23136ca09beSDongsheng.wang@freescale.com }
23236ca09beSDongsheng.wang@freescale.com spin_unlock_irqrestore(&priv->lock, flags);
23336ca09beSDongsheng.wang@freescale.com }
23436ca09beSDongsheng.wang@freescale.com }
23536ca09beSDongsheng.wang@freescale.com
23636ca09beSDongsheng.wang@freescale.com return NULL;
23736ca09beSDongsheng.wang@freescale.com }
23836ca09beSDongsheng.wang@freescale.com
23936ca09beSDongsheng.wang@freescale.com /**
24036ca09beSDongsheng.wang@freescale.com * mpic_start_timer - start hardware timer
24136ca09beSDongsheng.wang@freescale.com * @handle: the timer to be started.
24236ca09beSDongsheng.wang@freescale.com *
24336ca09beSDongsheng.wang@freescale.com * It will do ->fn(->dev) callback from the hardware interrupt at
24411ed8c55SArnd Bergmann * the 'time64_t' point in the future.
24536ca09beSDongsheng.wang@freescale.com */
mpic_start_timer(struct mpic_timer * handle)24636ca09beSDongsheng.wang@freescale.com void mpic_start_timer(struct mpic_timer *handle)
24736ca09beSDongsheng.wang@freescale.com {
24836ca09beSDongsheng.wang@freescale.com struct timer_group_priv *priv = container_of(handle,
24936ca09beSDongsheng.wang@freescale.com struct timer_group_priv, timer[handle->num]);
25036ca09beSDongsheng.wang@freescale.com
25136ca09beSDongsheng.wang@freescale.com clrbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
25236ca09beSDongsheng.wang@freescale.com }
25336ca09beSDongsheng.wang@freescale.com EXPORT_SYMBOL(mpic_start_timer);
25436ca09beSDongsheng.wang@freescale.com
25536ca09beSDongsheng.wang@freescale.com /**
25636ca09beSDongsheng.wang@freescale.com * mpic_stop_timer - stop hardware timer
257*1fd02f66SJulia Lawall * @handle: the timer to be stopped
25836ca09beSDongsheng.wang@freescale.com *
25936ca09beSDongsheng.wang@freescale.com * The timer periodically generates an interrupt. Unless user stops the timer.
26036ca09beSDongsheng.wang@freescale.com */
mpic_stop_timer(struct mpic_timer * handle)26136ca09beSDongsheng.wang@freescale.com void mpic_stop_timer(struct mpic_timer *handle)
26236ca09beSDongsheng.wang@freescale.com {
26336ca09beSDongsheng.wang@freescale.com struct timer_group_priv *priv = container_of(handle,
26436ca09beSDongsheng.wang@freescale.com struct timer_group_priv, timer[handle->num]);
26536ca09beSDongsheng.wang@freescale.com struct cascade_priv *casc_priv;
26636ca09beSDongsheng.wang@freescale.com
26736ca09beSDongsheng.wang@freescale.com setbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
26836ca09beSDongsheng.wang@freescale.com
26936ca09beSDongsheng.wang@freescale.com casc_priv = priv->timer[handle->num].cascade_handle;
27036ca09beSDongsheng.wang@freescale.com if (casc_priv) {
27136ca09beSDongsheng.wang@freescale.com out_be32(&priv->regs[handle->num].gtccr, 0);
27236ca09beSDongsheng.wang@freescale.com out_be32(&priv->regs[handle->num - 1].gtccr, 0);
27336ca09beSDongsheng.wang@freescale.com } else {
27436ca09beSDongsheng.wang@freescale.com out_be32(&priv->regs[handle->num].gtccr, 0);
27536ca09beSDongsheng.wang@freescale.com }
27636ca09beSDongsheng.wang@freescale.com }
27736ca09beSDongsheng.wang@freescale.com EXPORT_SYMBOL(mpic_stop_timer);
27836ca09beSDongsheng.wang@freescale.com
27936ca09beSDongsheng.wang@freescale.com /**
28036ca09beSDongsheng.wang@freescale.com * mpic_get_remain_time - get timer time
28136ca09beSDongsheng.wang@freescale.com * @handle: the timer to be selected.
28236ca09beSDongsheng.wang@freescale.com * @time: time for timer
28336ca09beSDongsheng.wang@freescale.com *
28436ca09beSDongsheng.wang@freescale.com * Query timer remaining time.
28536ca09beSDongsheng.wang@freescale.com */
mpic_get_remain_time(struct mpic_timer * handle,time64_t * time)28611ed8c55SArnd Bergmann void mpic_get_remain_time(struct mpic_timer *handle, time64_t *time)
28736ca09beSDongsheng.wang@freescale.com {
28836ca09beSDongsheng.wang@freescale.com struct timer_group_priv *priv = container_of(handle,
28936ca09beSDongsheng.wang@freescale.com struct timer_group_priv, timer[handle->num]);
29036ca09beSDongsheng.wang@freescale.com struct cascade_priv *casc_priv;
29136ca09beSDongsheng.wang@freescale.com
29236ca09beSDongsheng.wang@freescale.com u64 ticks;
29336ca09beSDongsheng.wang@freescale.com u32 tmp_ticks;
29436ca09beSDongsheng.wang@freescale.com
29536ca09beSDongsheng.wang@freescale.com casc_priv = priv->timer[handle->num].cascade_handle;
29636ca09beSDongsheng.wang@freescale.com if (casc_priv) {
29736ca09beSDongsheng.wang@freescale.com tmp_ticks = in_be32(&priv->regs[handle->num].gtccr);
2980fd79588SWang Dongsheng tmp_ticks &= ~GTCCR_TOG;
29936ca09beSDongsheng.wang@freescale.com ticks = ((u64)tmp_ticks & UINT_MAX) * (u64)MAX_TICKS_CASCADE;
30036ca09beSDongsheng.wang@freescale.com tmp_ticks = in_be32(&priv->regs[handle->num - 1].gtccr);
30136ca09beSDongsheng.wang@freescale.com ticks += tmp_ticks;
30236ca09beSDongsheng.wang@freescale.com } else {
30336ca09beSDongsheng.wang@freescale.com ticks = in_be32(&priv->regs[handle->num].gtccr);
3040fd79588SWang Dongsheng ticks &= ~GTCCR_TOG;
30536ca09beSDongsheng.wang@freescale.com }
30636ca09beSDongsheng.wang@freescale.com
30736ca09beSDongsheng.wang@freescale.com convert_ticks_to_time(priv, ticks, time);
30836ca09beSDongsheng.wang@freescale.com }
30936ca09beSDongsheng.wang@freescale.com EXPORT_SYMBOL(mpic_get_remain_time);
31036ca09beSDongsheng.wang@freescale.com
31136ca09beSDongsheng.wang@freescale.com /**
31236ca09beSDongsheng.wang@freescale.com * mpic_free_timer - free hardware timer
31336ca09beSDongsheng.wang@freescale.com * @handle: the timer to be removed.
31436ca09beSDongsheng.wang@freescale.com *
31536ca09beSDongsheng.wang@freescale.com * Free the timer.
31636ca09beSDongsheng.wang@freescale.com *
31736ca09beSDongsheng.wang@freescale.com * Note: can not be used in interrupt context.
31836ca09beSDongsheng.wang@freescale.com */
mpic_free_timer(struct mpic_timer * handle)31936ca09beSDongsheng.wang@freescale.com void mpic_free_timer(struct mpic_timer *handle)
32036ca09beSDongsheng.wang@freescale.com {
32136ca09beSDongsheng.wang@freescale.com struct timer_group_priv *priv = container_of(handle,
32236ca09beSDongsheng.wang@freescale.com struct timer_group_priv, timer[handle->num]);
32336ca09beSDongsheng.wang@freescale.com
32436ca09beSDongsheng.wang@freescale.com struct cascade_priv *casc_priv;
32536ca09beSDongsheng.wang@freescale.com unsigned long flags;
32636ca09beSDongsheng.wang@freescale.com
32736ca09beSDongsheng.wang@freescale.com mpic_stop_timer(handle);
32836ca09beSDongsheng.wang@freescale.com
32936ca09beSDongsheng.wang@freescale.com casc_priv = priv->timer[handle->num].cascade_handle;
33036ca09beSDongsheng.wang@freescale.com
33136ca09beSDongsheng.wang@freescale.com free_irq(priv->timer[handle->num].irq, priv->timer[handle->num].dev);
33236ca09beSDongsheng.wang@freescale.com
33336ca09beSDongsheng.wang@freescale.com spin_lock_irqsave(&priv->lock, flags);
33436ca09beSDongsheng.wang@freescale.com if (casc_priv) {
33536ca09beSDongsheng.wang@freescale.com u32 tcr;
33636ca09beSDongsheng.wang@freescale.com tcr = casc_priv->tcr_value | (casc_priv->tcr_value <<
33736ca09beSDongsheng.wang@freescale.com MPIC_TIMER_TCR_ROVR_OFFSET);
33836ca09beSDongsheng.wang@freescale.com clrbits32(priv->group_tcr, tcr);
33936ca09beSDongsheng.wang@freescale.com priv->idle |= casc_priv->cascade_map;
34036ca09beSDongsheng.wang@freescale.com priv->timer[handle->num].cascade_handle = NULL;
34136ca09beSDongsheng.wang@freescale.com } else {
34236ca09beSDongsheng.wang@freescale.com priv->idle |= TIMER_OFFSET(handle->num);
34336ca09beSDongsheng.wang@freescale.com }
34436ca09beSDongsheng.wang@freescale.com spin_unlock_irqrestore(&priv->lock, flags);
34536ca09beSDongsheng.wang@freescale.com }
34636ca09beSDongsheng.wang@freescale.com EXPORT_SYMBOL(mpic_free_timer);
34736ca09beSDongsheng.wang@freescale.com
34836ca09beSDongsheng.wang@freescale.com /**
34936ca09beSDongsheng.wang@freescale.com * mpic_request_timer - get a hardware timer
35036ca09beSDongsheng.wang@freescale.com * @fn: interrupt handler function
35136ca09beSDongsheng.wang@freescale.com * @dev: callback function of the data
35236ca09beSDongsheng.wang@freescale.com * @time: time for timer
35336ca09beSDongsheng.wang@freescale.com *
35436ca09beSDongsheng.wang@freescale.com * This executes the "request_irq", returning NULL
35536ca09beSDongsheng.wang@freescale.com * else "handle" on success.
35636ca09beSDongsheng.wang@freescale.com */
mpic_request_timer(irq_handler_t fn,void * dev,time64_t time)35736ca09beSDongsheng.wang@freescale.com struct mpic_timer *mpic_request_timer(irq_handler_t fn, void *dev,
35811ed8c55SArnd Bergmann time64_t time)
35936ca09beSDongsheng.wang@freescale.com {
36036ca09beSDongsheng.wang@freescale.com struct mpic_timer *allocated_timer;
36136ca09beSDongsheng.wang@freescale.com int ret;
36236ca09beSDongsheng.wang@freescale.com
36336ca09beSDongsheng.wang@freescale.com if (list_empty(&timer_group_list))
36436ca09beSDongsheng.wang@freescale.com return NULL;
36536ca09beSDongsheng.wang@freescale.com
36611ed8c55SArnd Bergmann if (time < 0)
36736ca09beSDongsheng.wang@freescale.com return NULL;
36836ca09beSDongsheng.wang@freescale.com
36936ca09beSDongsheng.wang@freescale.com allocated_timer = get_timer(time);
37036ca09beSDongsheng.wang@freescale.com if (!allocated_timer)
37136ca09beSDongsheng.wang@freescale.com return NULL;
37236ca09beSDongsheng.wang@freescale.com
37336ca09beSDongsheng.wang@freescale.com ret = request_irq(allocated_timer->irq, fn,
37436ca09beSDongsheng.wang@freescale.com IRQF_TRIGGER_LOW, "global-timer", dev);
37536ca09beSDongsheng.wang@freescale.com if (ret) {
37636ca09beSDongsheng.wang@freescale.com mpic_free_timer(allocated_timer);
37736ca09beSDongsheng.wang@freescale.com return NULL;
37836ca09beSDongsheng.wang@freescale.com }
37936ca09beSDongsheng.wang@freescale.com
38036ca09beSDongsheng.wang@freescale.com allocated_timer->dev = dev;
38136ca09beSDongsheng.wang@freescale.com
38236ca09beSDongsheng.wang@freescale.com return allocated_timer;
38336ca09beSDongsheng.wang@freescale.com }
38436ca09beSDongsheng.wang@freescale.com EXPORT_SYMBOL(mpic_request_timer);
38536ca09beSDongsheng.wang@freescale.com
timer_group_get_freq(struct device_node * np,struct timer_group_priv * priv)3866c552983SNick Child static int __init timer_group_get_freq(struct device_node *np,
38736ca09beSDongsheng.wang@freescale.com struct timer_group_priv *priv)
38836ca09beSDongsheng.wang@freescale.com {
38936ca09beSDongsheng.wang@freescale.com u32 div;
39036ca09beSDongsheng.wang@freescale.com
39136ca09beSDongsheng.wang@freescale.com if (priv->flags & FSL_GLOBAL_TIMER) {
39236ca09beSDongsheng.wang@freescale.com struct device_node *dn;
39336ca09beSDongsheng.wang@freescale.com
39436ca09beSDongsheng.wang@freescale.com dn = of_find_compatible_node(NULL, NULL, "fsl,mpic");
39536ca09beSDongsheng.wang@freescale.com if (dn) {
39636ca09beSDongsheng.wang@freescale.com of_property_read_u32(dn, "clock-frequency",
39736ca09beSDongsheng.wang@freescale.com &priv->timerfreq);
39836ca09beSDongsheng.wang@freescale.com of_node_put(dn);
39936ca09beSDongsheng.wang@freescale.com }
40036ca09beSDongsheng.wang@freescale.com }
40136ca09beSDongsheng.wang@freescale.com
40236ca09beSDongsheng.wang@freescale.com if (priv->timerfreq <= 0)
40336ca09beSDongsheng.wang@freescale.com return -EINVAL;
40436ca09beSDongsheng.wang@freescale.com
40536ca09beSDongsheng.wang@freescale.com if (priv->flags & FSL_GLOBAL_TIMER) {
40636ca09beSDongsheng.wang@freescale.com div = (1 << (MPIC_TIMER_TCR_CLKDIV >> 8)) * 8;
40736ca09beSDongsheng.wang@freescale.com priv->timerfreq /= div;
40836ca09beSDongsheng.wang@freescale.com }
40936ca09beSDongsheng.wang@freescale.com
41036ca09beSDongsheng.wang@freescale.com return 0;
41136ca09beSDongsheng.wang@freescale.com }
41236ca09beSDongsheng.wang@freescale.com
timer_group_get_irq(struct device_node * np,struct timer_group_priv * priv)4136c552983SNick Child static int __init timer_group_get_irq(struct device_node *np,
41436ca09beSDongsheng.wang@freescale.com struct timer_group_priv *priv)
41536ca09beSDongsheng.wang@freescale.com {
41636ca09beSDongsheng.wang@freescale.com const u32 all_timer[] = { 0, TIMERS_PER_GROUP };
41736ca09beSDongsheng.wang@freescale.com const u32 *p;
41836ca09beSDongsheng.wang@freescale.com u32 offset;
41936ca09beSDongsheng.wang@freescale.com u32 count;
42036ca09beSDongsheng.wang@freescale.com
42136ca09beSDongsheng.wang@freescale.com unsigned int i;
42236ca09beSDongsheng.wang@freescale.com unsigned int j;
42336ca09beSDongsheng.wang@freescale.com unsigned int irq_index = 0;
42436ca09beSDongsheng.wang@freescale.com unsigned int irq;
42536ca09beSDongsheng.wang@freescale.com int len;
42636ca09beSDongsheng.wang@freescale.com
42736ca09beSDongsheng.wang@freescale.com p = of_get_property(np, "fsl,available-ranges", &len);
42836ca09beSDongsheng.wang@freescale.com if (p && len % (2 * sizeof(u32)) != 0) {
429b7c670d6SRob Herring pr_err("%pOF: malformed available-ranges property.\n", np);
43036ca09beSDongsheng.wang@freescale.com return -EINVAL;
43136ca09beSDongsheng.wang@freescale.com }
43236ca09beSDongsheng.wang@freescale.com
43336ca09beSDongsheng.wang@freescale.com if (!p) {
43436ca09beSDongsheng.wang@freescale.com p = all_timer;
43536ca09beSDongsheng.wang@freescale.com len = sizeof(all_timer);
43636ca09beSDongsheng.wang@freescale.com }
43736ca09beSDongsheng.wang@freescale.com
43836ca09beSDongsheng.wang@freescale.com len /= 2 * sizeof(u32);
43936ca09beSDongsheng.wang@freescale.com
44036ca09beSDongsheng.wang@freescale.com for (i = 0; i < len; i++) {
44136ca09beSDongsheng.wang@freescale.com offset = p[i * 2];
44236ca09beSDongsheng.wang@freescale.com count = p[i * 2 + 1];
44336ca09beSDongsheng.wang@freescale.com for (j = 0; j < count; j++) {
44436ca09beSDongsheng.wang@freescale.com irq = irq_of_parse_and_map(np, irq_index);
44536ca09beSDongsheng.wang@freescale.com if (!irq) {
446b7c670d6SRob Herring pr_err("%pOF: irq parse and map failed.\n", np);
44736ca09beSDongsheng.wang@freescale.com return -EINVAL;
44836ca09beSDongsheng.wang@freescale.com }
44936ca09beSDongsheng.wang@freescale.com
45036ca09beSDongsheng.wang@freescale.com /* Set timer idle */
45136ca09beSDongsheng.wang@freescale.com priv->idle |= TIMER_OFFSET((offset + j));
45236ca09beSDongsheng.wang@freescale.com priv->timer[offset + j].irq = irq;
45336ca09beSDongsheng.wang@freescale.com priv->timer[offset + j].num = offset + j;
45436ca09beSDongsheng.wang@freescale.com irq_index++;
45536ca09beSDongsheng.wang@freescale.com }
45636ca09beSDongsheng.wang@freescale.com }
45736ca09beSDongsheng.wang@freescale.com
45836ca09beSDongsheng.wang@freescale.com return 0;
45936ca09beSDongsheng.wang@freescale.com }
46036ca09beSDongsheng.wang@freescale.com
timer_group_init(struct device_node * np)4616c552983SNick Child static void __init timer_group_init(struct device_node *np)
46236ca09beSDongsheng.wang@freescale.com {
46336ca09beSDongsheng.wang@freescale.com struct timer_group_priv *priv;
46436ca09beSDongsheng.wang@freescale.com unsigned int i = 0;
46536ca09beSDongsheng.wang@freescale.com int ret;
46636ca09beSDongsheng.wang@freescale.com
46736ca09beSDongsheng.wang@freescale.com priv = kzalloc(sizeof(struct timer_group_priv), GFP_KERNEL);
46836ca09beSDongsheng.wang@freescale.com if (!priv) {
469b7c670d6SRob Herring pr_err("%pOF: cannot allocate memory for group.\n", np);
47036ca09beSDongsheng.wang@freescale.com return;
47136ca09beSDongsheng.wang@freescale.com }
47236ca09beSDongsheng.wang@freescale.com
47336ca09beSDongsheng.wang@freescale.com if (of_device_is_compatible(np, "fsl,mpic-global-timer"))
47436ca09beSDongsheng.wang@freescale.com priv->flags |= FSL_GLOBAL_TIMER;
47536ca09beSDongsheng.wang@freescale.com
47636ca09beSDongsheng.wang@freescale.com priv->regs = of_iomap(np, i++);
47736ca09beSDongsheng.wang@freescale.com if (!priv->regs) {
478b7c670d6SRob Herring pr_err("%pOF: cannot ioremap timer register address.\n", np);
47936ca09beSDongsheng.wang@freescale.com goto out;
48036ca09beSDongsheng.wang@freescale.com }
48136ca09beSDongsheng.wang@freescale.com
48236ca09beSDongsheng.wang@freescale.com if (priv->flags & FSL_GLOBAL_TIMER) {
48336ca09beSDongsheng.wang@freescale.com priv->group_tcr = of_iomap(np, i++);
48436ca09beSDongsheng.wang@freescale.com if (!priv->group_tcr) {
485b7c670d6SRob Herring pr_err("%pOF: cannot ioremap tcr address.\n", np);
48636ca09beSDongsheng.wang@freescale.com goto out;
48736ca09beSDongsheng.wang@freescale.com }
48836ca09beSDongsheng.wang@freescale.com }
48936ca09beSDongsheng.wang@freescale.com
49036ca09beSDongsheng.wang@freescale.com ret = timer_group_get_freq(np, priv);
49136ca09beSDongsheng.wang@freescale.com if (ret < 0) {
492b7c670d6SRob Herring pr_err("%pOF: cannot get timer frequency.\n", np);
49336ca09beSDongsheng.wang@freescale.com goto out;
49436ca09beSDongsheng.wang@freescale.com }
49536ca09beSDongsheng.wang@freescale.com
49636ca09beSDongsheng.wang@freescale.com ret = timer_group_get_irq(np, priv);
49736ca09beSDongsheng.wang@freescale.com if (ret < 0) {
498b7c670d6SRob Herring pr_err("%pOF: cannot get timer irqs.\n", np);
49936ca09beSDongsheng.wang@freescale.com goto out;
50036ca09beSDongsheng.wang@freescale.com }
50136ca09beSDongsheng.wang@freescale.com
50236ca09beSDongsheng.wang@freescale.com spin_lock_init(&priv->lock);
50336ca09beSDongsheng.wang@freescale.com
50436ca09beSDongsheng.wang@freescale.com /* Init FSL timer hardware */
50536ca09beSDongsheng.wang@freescale.com if (priv->flags & FSL_GLOBAL_TIMER)
50636ca09beSDongsheng.wang@freescale.com setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
50736ca09beSDongsheng.wang@freescale.com
50836ca09beSDongsheng.wang@freescale.com list_add_tail(&priv->node, &timer_group_list);
50936ca09beSDongsheng.wang@freescale.com
51036ca09beSDongsheng.wang@freescale.com return;
51136ca09beSDongsheng.wang@freescale.com
51236ca09beSDongsheng.wang@freescale.com out:
51336ca09beSDongsheng.wang@freescale.com if (priv->regs)
51436ca09beSDongsheng.wang@freescale.com iounmap(priv->regs);
51536ca09beSDongsheng.wang@freescale.com
51636ca09beSDongsheng.wang@freescale.com if (priv->group_tcr)
51736ca09beSDongsheng.wang@freescale.com iounmap(priv->group_tcr);
51836ca09beSDongsheng.wang@freescale.com
51936ca09beSDongsheng.wang@freescale.com kfree(priv);
52036ca09beSDongsheng.wang@freescale.com }
52136ca09beSDongsheng.wang@freescale.com
mpic_timer_resume(void)52236ca09beSDongsheng.wang@freescale.com static void mpic_timer_resume(void)
52336ca09beSDongsheng.wang@freescale.com {
52436ca09beSDongsheng.wang@freescale.com struct timer_group_priv *priv;
52536ca09beSDongsheng.wang@freescale.com
52636ca09beSDongsheng.wang@freescale.com list_for_each_entry(priv, &timer_group_list, node) {
52736ca09beSDongsheng.wang@freescale.com /* Init FSL timer hardware */
52836ca09beSDongsheng.wang@freescale.com if (priv->flags & FSL_GLOBAL_TIMER)
52936ca09beSDongsheng.wang@freescale.com setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
53036ca09beSDongsheng.wang@freescale.com }
53136ca09beSDongsheng.wang@freescale.com }
53236ca09beSDongsheng.wang@freescale.com
53336ca09beSDongsheng.wang@freescale.com static const struct of_device_id mpic_timer_ids[] = {
53436ca09beSDongsheng.wang@freescale.com { .compatible = "fsl,mpic-global-timer", },
53536ca09beSDongsheng.wang@freescale.com {},
53636ca09beSDongsheng.wang@freescale.com };
53736ca09beSDongsheng.wang@freescale.com
53836ca09beSDongsheng.wang@freescale.com static struct syscore_ops mpic_timer_syscore_ops = {
53936ca09beSDongsheng.wang@freescale.com .resume = mpic_timer_resume,
54036ca09beSDongsheng.wang@freescale.com };
54136ca09beSDongsheng.wang@freescale.com
mpic_timer_init(void)54236ca09beSDongsheng.wang@freescale.com static int __init mpic_timer_init(void)
54336ca09beSDongsheng.wang@freescale.com {
54436ca09beSDongsheng.wang@freescale.com struct device_node *np = NULL;
54536ca09beSDongsheng.wang@freescale.com
54636ca09beSDongsheng.wang@freescale.com for_each_matching_node(np, mpic_timer_ids)
54736ca09beSDongsheng.wang@freescale.com timer_group_init(np);
54836ca09beSDongsheng.wang@freescale.com
54936ca09beSDongsheng.wang@freescale.com register_syscore_ops(&mpic_timer_syscore_ops);
55036ca09beSDongsheng.wang@freescale.com
55136ca09beSDongsheng.wang@freescale.com if (list_empty(&timer_group_list))
55236ca09beSDongsheng.wang@freescale.com return -ENODEV;
55336ca09beSDongsheng.wang@freescale.com
55436ca09beSDongsheng.wang@freescale.com return 0;
55536ca09beSDongsheng.wang@freescale.com }
55636ca09beSDongsheng.wang@freescale.com subsys_initcall(mpic_timer_init);
557