1 /* 2 * arch/powerpc/kernel/mpic.c 3 * 4 * Driver for interrupt controllers following the OpenPIC standard, the 5 * common implementation beeing IBM's MPIC. This driver also can deal 6 * with various broken implementations of this HW. 7 * 8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file COPYING in the main directory of this archive 12 * for more details. 13 */ 14 15 #undef DEBUG 16 #undef DEBUG_IPI 17 #undef DEBUG_IRQ 18 #undef DEBUG_LOW 19 20 #include <linux/types.h> 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/irq.h> 24 #include <linux/smp.h> 25 #include <linux/interrupt.h> 26 #include <linux/bootmem.h> 27 #include <linux/spinlock.h> 28 #include <linux/pci.h> 29 #include <linux/slab.h> 30 31 #include <asm/ptrace.h> 32 #include <asm/signal.h> 33 #include <asm/io.h> 34 #include <asm/pgtable.h> 35 #include <asm/irq.h> 36 #include <asm/machdep.h> 37 #include <asm/mpic.h> 38 #include <asm/smp.h> 39 40 #include "mpic.h" 41 42 #ifdef DEBUG 43 #define DBG(fmt...) printk(fmt) 44 #else 45 #define DBG(fmt...) 46 #endif 47 48 static struct mpic *mpics; 49 static struct mpic *mpic_primary; 50 static DEFINE_RAW_SPINLOCK(mpic_lock); 51 52 #ifdef CONFIG_PPC32 /* XXX for now */ 53 #ifdef CONFIG_IRQ_ALL_CPUS 54 #define distribute_irqs (1) 55 #else 56 #define distribute_irqs (0) 57 #endif 58 #endif 59 60 #ifdef CONFIG_MPIC_WEIRD 61 static u32 mpic_infos[][MPIC_IDX_END] = { 62 [0] = { /* Original OpenPIC compatible MPIC */ 63 MPIC_GREG_BASE, 64 MPIC_GREG_FEATURE_0, 65 MPIC_GREG_GLOBAL_CONF_0, 66 MPIC_GREG_VENDOR_ID, 67 MPIC_GREG_IPI_VECTOR_PRI_0, 68 MPIC_GREG_IPI_STRIDE, 69 MPIC_GREG_SPURIOUS, 70 MPIC_GREG_TIMER_FREQ, 71 72 MPIC_TIMER_BASE, 73 MPIC_TIMER_STRIDE, 74 MPIC_TIMER_CURRENT_CNT, 75 MPIC_TIMER_BASE_CNT, 76 MPIC_TIMER_VECTOR_PRI, 77 MPIC_TIMER_DESTINATION, 78 79 MPIC_CPU_BASE, 80 MPIC_CPU_STRIDE, 81 MPIC_CPU_IPI_DISPATCH_0, 82 MPIC_CPU_IPI_DISPATCH_STRIDE, 83 MPIC_CPU_CURRENT_TASK_PRI, 84 MPIC_CPU_WHOAMI, 85 MPIC_CPU_INTACK, 86 MPIC_CPU_EOI, 87 MPIC_CPU_MCACK, 88 89 MPIC_IRQ_BASE, 90 MPIC_IRQ_STRIDE, 91 MPIC_IRQ_VECTOR_PRI, 92 MPIC_VECPRI_VECTOR_MASK, 93 MPIC_VECPRI_POLARITY_POSITIVE, 94 MPIC_VECPRI_POLARITY_NEGATIVE, 95 MPIC_VECPRI_SENSE_LEVEL, 96 MPIC_VECPRI_SENSE_EDGE, 97 MPIC_VECPRI_POLARITY_MASK, 98 MPIC_VECPRI_SENSE_MASK, 99 MPIC_IRQ_DESTINATION 100 }, 101 [1] = { /* Tsi108/109 PIC */ 102 TSI108_GREG_BASE, 103 TSI108_GREG_FEATURE_0, 104 TSI108_GREG_GLOBAL_CONF_0, 105 TSI108_GREG_VENDOR_ID, 106 TSI108_GREG_IPI_VECTOR_PRI_0, 107 TSI108_GREG_IPI_STRIDE, 108 TSI108_GREG_SPURIOUS, 109 TSI108_GREG_TIMER_FREQ, 110 111 TSI108_TIMER_BASE, 112 TSI108_TIMER_STRIDE, 113 TSI108_TIMER_CURRENT_CNT, 114 TSI108_TIMER_BASE_CNT, 115 TSI108_TIMER_VECTOR_PRI, 116 TSI108_TIMER_DESTINATION, 117 118 TSI108_CPU_BASE, 119 TSI108_CPU_STRIDE, 120 TSI108_CPU_IPI_DISPATCH_0, 121 TSI108_CPU_IPI_DISPATCH_STRIDE, 122 TSI108_CPU_CURRENT_TASK_PRI, 123 TSI108_CPU_WHOAMI, 124 TSI108_CPU_INTACK, 125 TSI108_CPU_EOI, 126 TSI108_CPU_MCACK, 127 128 TSI108_IRQ_BASE, 129 TSI108_IRQ_STRIDE, 130 TSI108_IRQ_VECTOR_PRI, 131 TSI108_VECPRI_VECTOR_MASK, 132 TSI108_VECPRI_POLARITY_POSITIVE, 133 TSI108_VECPRI_POLARITY_NEGATIVE, 134 TSI108_VECPRI_SENSE_LEVEL, 135 TSI108_VECPRI_SENSE_EDGE, 136 TSI108_VECPRI_POLARITY_MASK, 137 TSI108_VECPRI_SENSE_MASK, 138 TSI108_IRQ_DESTINATION 139 }, 140 }; 141 142 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] 143 144 #else /* CONFIG_MPIC_WEIRD */ 145 146 #define MPIC_INFO(name) MPIC_##name 147 148 #endif /* CONFIG_MPIC_WEIRD */ 149 150 /* 151 * Register accessor functions 152 */ 153 154 155 static inline u32 _mpic_read(enum mpic_reg_type type, 156 struct mpic_reg_bank *rb, 157 unsigned int reg) 158 { 159 switch(type) { 160 #ifdef CONFIG_PPC_DCR 161 case mpic_access_dcr: 162 return dcr_read(rb->dhost, reg); 163 #endif 164 case mpic_access_mmio_be: 165 return in_be32(rb->base + (reg >> 2)); 166 case mpic_access_mmio_le: 167 default: 168 return in_le32(rb->base + (reg >> 2)); 169 } 170 } 171 172 static inline void _mpic_write(enum mpic_reg_type type, 173 struct mpic_reg_bank *rb, 174 unsigned int reg, u32 value) 175 { 176 switch(type) { 177 #ifdef CONFIG_PPC_DCR 178 case mpic_access_dcr: 179 dcr_write(rb->dhost, reg, value); 180 break; 181 #endif 182 case mpic_access_mmio_be: 183 out_be32(rb->base + (reg >> 2), value); 184 break; 185 case mpic_access_mmio_le: 186 default: 187 out_le32(rb->base + (reg >> 2), value); 188 break; 189 } 190 } 191 192 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) 193 { 194 enum mpic_reg_type type = mpic->reg_type; 195 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 196 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 197 198 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) 199 type = mpic_access_mmio_be; 200 return _mpic_read(type, &mpic->gregs, offset); 201 } 202 203 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) 204 { 205 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 206 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 207 208 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); 209 } 210 211 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) 212 { 213 unsigned int cpu = 0; 214 215 if (mpic->flags & MPIC_PRIMARY) 216 cpu = hard_smp_processor_id(); 217 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); 218 } 219 220 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) 221 { 222 unsigned int cpu = 0; 223 224 if (mpic->flags & MPIC_PRIMARY) 225 cpu = hard_smp_processor_id(); 226 227 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); 228 } 229 230 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) 231 { 232 unsigned int isu = src_no >> mpic->isu_shift; 233 unsigned int idx = src_no & mpic->isu_mask; 234 unsigned int val; 235 236 val = _mpic_read(mpic->reg_type, &mpic->isus[isu], 237 reg + (idx * MPIC_INFO(IRQ_STRIDE))); 238 #ifdef CONFIG_MPIC_BROKEN_REGREAD 239 if (reg == 0) 240 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) | 241 mpic->isu_reg0_shadow[src_no]; 242 #endif 243 return val; 244 } 245 246 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, 247 unsigned int reg, u32 value) 248 { 249 unsigned int isu = src_no >> mpic->isu_shift; 250 unsigned int idx = src_no & mpic->isu_mask; 251 252 _mpic_write(mpic->reg_type, &mpic->isus[isu], 253 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); 254 255 #ifdef CONFIG_MPIC_BROKEN_REGREAD 256 if (reg == 0) 257 mpic->isu_reg0_shadow[src_no] = 258 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY); 259 #endif 260 } 261 262 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) 263 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) 264 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) 265 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) 266 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) 267 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) 268 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) 269 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) 270 271 272 /* 273 * Low level utility functions 274 */ 275 276 277 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, 278 struct mpic_reg_bank *rb, unsigned int offset, 279 unsigned int size) 280 { 281 rb->base = ioremap(phys_addr + offset, size); 282 BUG_ON(rb->base == NULL); 283 } 284 285 #ifdef CONFIG_PPC_DCR 286 static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node, 287 struct mpic_reg_bank *rb, 288 unsigned int offset, unsigned int size) 289 { 290 const u32 *dbasep; 291 292 dbasep = of_get_property(node, "dcr-reg", NULL); 293 294 rb->dhost = dcr_map(node, *dbasep + offset, size); 295 BUG_ON(!DCR_MAP_OK(rb->dhost)); 296 } 297 298 static inline void mpic_map(struct mpic *mpic, struct device_node *node, 299 phys_addr_t phys_addr, struct mpic_reg_bank *rb, 300 unsigned int offset, unsigned int size) 301 { 302 if (mpic->flags & MPIC_USES_DCR) 303 _mpic_map_dcr(mpic, node, rb, offset, size); 304 else 305 _mpic_map_mmio(mpic, phys_addr, rb, offset, size); 306 } 307 #else /* CONFIG_PPC_DCR */ 308 #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) 309 #endif /* !CONFIG_PPC_DCR */ 310 311 312 313 /* Check if we have one of those nice broken MPICs with a flipped endian on 314 * reads from IPI registers 315 */ 316 static void __init mpic_test_broken_ipi(struct mpic *mpic) 317 { 318 u32 r; 319 320 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); 321 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); 322 323 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { 324 printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); 325 mpic->flags |= MPIC_BROKEN_IPI; 326 } 327 } 328 329 #ifdef CONFIG_MPIC_U3_HT_IRQS 330 331 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) 332 * to force the edge setting on the MPIC and do the ack workaround. 333 */ 334 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 335 { 336 if (source >= 128 || !mpic->fixups) 337 return 0; 338 return mpic->fixups[source].base != NULL; 339 } 340 341 342 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) 343 { 344 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 345 346 if (fixup->applebase) { 347 unsigned int soff = (fixup->index >> 3) & ~3; 348 unsigned int mask = 1U << (fixup->index & 0x1f); 349 writel(mask, fixup->applebase + soff); 350 } else { 351 raw_spin_lock(&mpic->fixup_lock); 352 writeb(0x11 + 2 * fixup->index, fixup->base + 2); 353 writel(fixup->data, fixup->base + 4); 354 raw_spin_unlock(&mpic->fixup_lock); 355 } 356 } 357 358 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, 359 unsigned int irqflags) 360 { 361 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 362 unsigned long flags; 363 u32 tmp; 364 365 if (fixup->base == NULL) 366 return; 367 368 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n", 369 source, irqflags, fixup->index); 370 raw_spin_lock_irqsave(&mpic->fixup_lock, flags); 371 /* Enable and configure */ 372 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 373 tmp = readl(fixup->base + 4); 374 tmp &= ~(0x23U); 375 if (irqflags & IRQ_LEVEL) 376 tmp |= 0x22; 377 writel(tmp, fixup->base + 4); 378 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); 379 380 #ifdef CONFIG_PM 381 /* use the lowest bit inverted to the actual HW, 382 * set if this fixup was enabled, clear otherwise */ 383 mpic->save_data[source].fixup_data = tmp | 1; 384 #endif 385 } 386 387 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, 388 unsigned int irqflags) 389 { 390 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 391 unsigned long flags; 392 u32 tmp; 393 394 if (fixup->base == NULL) 395 return; 396 397 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags); 398 399 /* Disable */ 400 raw_spin_lock_irqsave(&mpic->fixup_lock, flags); 401 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 402 tmp = readl(fixup->base + 4); 403 tmp |= 1; 404 writel(tmp, fixup->base + 4); 405 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); 406 407 #ifdef CONFIG_PM 408 /* use the lowest bit inverted to the actual HW, 409 * set if this fixup was enabled, clear otherwise */ 410 mpic->save_data[source].fixup_data = tmp & ~1; 411 #endif 412 } 413 414 #ifdef CONFIG_PCI_MSI 415 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, 416 unsigned int devfn) 417 { 418 u8 __iomem *base; 419 u8 pos, flags; 420 u64 addr = 0; 421 422 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 423 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 424 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 425 if (id == PCI_CAP_ID_HT) { 426 id = readb(devbase + pos + 3); 427 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) 428 break; 429 } 430 } 431 432 if (pos == 0) 433 return; 434 435 base = devbase + pos; 436 437 flags = readb(base + HT_MSI_FLAGS); 438 if (!(flags & HT_MSI_FLAGS_FIXED)) { 439 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; 440 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); 441 } 442 443 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", 444 PCI_SLOT(devfn), PCI_FUNC(devfn), 445 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); 446 447 if (!(flags & HT_MSI_FLAGS_ENABLE)) 448 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); 449 } 450 #else 451 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, 452 unsigned int devfn) 453 { 454 return; 455 } 456 #endif 457 458 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, 459 unsigned int devfn, u32 vdid) 460 { 461 int i, irq, n; 462 u8 __iomem *base; 463 u32 tmp; 464 u8 pos; 465 466 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 467 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 468 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 469 if (id == PCI_CAP_ID_HT) { 470 id = readb(devbase + pos + 3); 471 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) 472 break; 473 } 474 } 475 if (pos == 0) 476 return; 477 478 base = devbase + pos; 479 writeb(0x01, base + 2); 480 n = (readl(base + 4) >> 16) & 0xff; 481 482 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" 483 " has %d irqs\n", 484 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); 485 486 for (i = 0; i <= n; i++) { 487 writeb(0x10 + 2 * i, base + 2); 488 tmp = readl(base + 4); 489 irq = (tmp >> 16) & 0xff; 490 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); 491 /* mask it , will be unmasked later */ 492 tmp |= 0x1; 493 writel(tmp, base + 4); 494 mpic->fixups[irq].index = i; 495 mpic->fixups[irq].base = base; 496 /* Apple HT PIC has a non-standard way of doing EOIs */ 497 if ((vdid & 0xffff) == 0x106b) 498 mpic->fixups[irq].applebase = devbase + 0x60; 499 else 500 mpic->fixups[irq].applebase = NULL; 501 writeb(0x11 + 2 * i, base + 2); 502 mpic->fixups[irq].data = readl(base + 4) | 0x80000000; 503 } 504 } 505 506 507 static void __init mpic_scan_ht_pics(struct mpic *mpic) 508 { 509 unsigned int devfn; 510 u8 __iomem *cfgspace; 511 512 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); 513 514 /* Allocate fixups array */ 515 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL); 516 BUG_ON(mpic->fixups == NULL); 517 518 /* Init spinlock */ 519 raw_spin_lock_init(&mpic->fixup_lock); 520 521 /* Map U3 config space. We assume all IO-APICs are on the primary bus 522 * so we only need to map 64kB. 523 */ 524 cfgspace = ioremap(0xf2000000, 0x10000); 525 BUG_ON(cfgspace == NULL); 526 527 /* Now we scan all slots. We do a very quick scan, we read the header 528 * type, vendor ID and device ID only, that's plenty enough 529 */ 530 for (devfn = 0; devfn < 0x100; devfn++) { 531 u8 __iomem *devbase = cfgspace + (devfn << 8); 532 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); 533 u32 l = readl(devbase + PCI_VENDOR_ID); 534 u16 s; 535 536 DBG("devfn %x, l: %x\n", devfn, l); 537 538 /* If no device, skip */ 539 if (l == 0xffffffff || l == 0x00000000 || 540 l == 0x0000ffff || l == 0xffff0000) 541 goto next; 542 /* Check if is supports capability lists */ 543 s = readw(devbase + PCI_STATUS); 544 if (!(s & PCI_STATUS_CAP_LIST)) 545 goto next; 546 547 mpic_scan_ht_pic(mpic, devbase, devfn, l); 548 mpic_scan_ht_msi(mpic, devbase, devfn); 549 550 next: 551 /* next device, if function 0 */ 552 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) 553 devfn += 7; 554 } 555 } 556 557 #else /* CONFIG_MPIC_U3_HT_IRQS */ 558 559 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 560 { 561 return 0; 562 } 563 564 static void __init mpic_scan_ht_pics(struct mpic *mpic) 565 { 566 } 567 568 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 569 570 #ifdef CONFIG_SMP 571 static int irq_choose_cpu(const struct cpumask *mask) 572 { 573 int cpuid; 574 575 if (cpumask_equal(mask, cpu_all_mask)) { 576 static int irq_rover = 0; 577 static DEFINE_RAW_SPINLOCK(irq_rover_lock); 578 unsigned long flags; 579 580 /* Round-robin distribution... */ 581 do_round_robin: 582 raw_spin_lock_irqsave(&irq_rover_lock, flags); 583 584 irq_rover = cpumask_next(irq_rover, cpu_online_mask); 585 if (irq_rover >= nr_cpu_ids) 586 irq_rover = cpumask_first(cpu_online_mask); 587 588 cpuid = irq_rover; 589 590 raw_spin_unlock_irqrestore(&irq_rover_lock, flags); 591 } else { 592 cpuid = cpumask_first_and(mask, cpu_online_mask); 593 if (cpuid >= nr_cpu_ids) 594 goto do_round_robin; 595 } 596 597 return get_hard_smp_processor_id(cpuid); 598 } 599 #else 600 static int irq_choose_cpu(const struct cpumask *mask) 601 { 602 return hard_smp_processor_id(); 603 } 604 #endif 605 606 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) 607 608 /* Find an mpic associated with a given linux interrupt */ 609 static struct mpic *mpic_find(unsigned int irq) 610 { 611 if (irq < NUM_ISA_INTERRUPTS) 612 return NULL; 613 614 return irq_to_desc(irq)->chip_data; 615 } 616 617 /* Determine if the linux irq is an IPI */ 618 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq) 619 { 620 unsigned int src = mpic_irq_to_hw(irq); 621 622 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); 623 } 624 625 626 /* Convert a cpu mask from logical to physical cpu numbers. */ 627 static inline u32 mpic_physmask(u32 cpumask) 628 { 629 int i; 630 u32 mask = 0; 631 632 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1) 633 mask |= (cpumask & 1) << get_hard_smp_processor_id(i); 634 return mask; 635 } 636 637 #ifdef CONFIG_SMP 638 /* Get the mpic structure from the IPI number */ 639 static inline struct mpic * mpic_from_ipi(unsigned int ipi) 640 { 641 return irq_to_desc(ipi)->chip_data; 642 } 643 #endif 644 645 /* Get the mpic structure from the irq number */ 646 static inline struct mpic * mpic_from_irq(unsigned int irq) 647 { 648 return irq_to_desc(irq)->chip_data; 649 } 650 651 /* Send an EOI */ 652 static inline void mpic_eoi(struct mpic *mpic) 653 { 654 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); 655 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); 656 } 657 658 /* 659 * Linux descriptor level callbacks 660 */ 661 662 663 void mpic_unmask_irq(unsigned int irq) 664 { 665 unsigned int loops = 100000; 666 struct mpic *mpic = mpic_from_irq(irq); 667 unsigned int src = mpic_irq_to_hw(irq); 668 669 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src); 670 671 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 672 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & 673 ~MPIC_VECPRI_MASK); 674 /* make sure mask gets to controller before we return to user */ 675 do { 676 if (!loops--) { 677 printk(KERN_ERR "mpic_enable_irq timeout\n"); 678 break; 679 } 680 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); 681 } 682 683 void mpic_mask_irq(unsigned int irq) 684 { 685 unsigned int loops = 100000; 686 struct mpic *mpic = mpic_from_irq(irq); 687 unsigned int src = mpic_irq_to_hw(irq); 688 689 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); 690 691 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 692 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | 693 MPIC_VECPRI_MASK); 694 695 /* make sure mask gets to controller before we return to user */ 696 do { 697 if (!loops--) { 698 printk(KERN_ERR "mpic_enable_irq timeout\n"); 699 break; 700 } 701 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); 702 } 703 704 void mpic_end_irq(unsigned int irq) 705 { 706 struct mpic *mpic = mpic_from_irq(irq); 707 708 #ifdef DEBUG_IRQ 709 DBG("%s: end_irq: %d\n", mpic->name, irq); 710 #endif 711 /* We always EOI on end_irq() even for edge interrupts since that 712 * should only lower the priority, the MPIC should have properly 713 * latched another edge interrupt coming in anyway 714 */ 715 716 mpic_eoi(mpic); 717 } 718 719 #ifdef CONFIG_MPIC_U3_HT_IRQS 720 721 static void mpic_unmask_ht_irq(unsigned int irq) 722 { 723 struct mpic *mpic = mpic_from_irq(irq); 724 unsigned int src = mpic_irq_to_hw(irq); 725 726 mpic_unmask_irq(irq); 727 728 if (irq_to_desc(irq)->status & IRQ_LEVEL) 729 mpic_ht_end_irq(mpic, src); 730 } 731 732 static unsigned int mpic_startup_ht_irq(unsigned int irq) 733 { 734 struct mpic *mpic = mpic_from_irq(irq); 735 unsigned int src = mpic_irq_to_hw(irq); 736 737 mpic_unmask_irq(irq); 738 mpic_startup_ht_interrupt(mpic, src, irq_to_desc(irq)->status); 739 740 return 0; 741 } 742 743 static void mpic_shutdown_ht_irq(unsigned int irq) 744 { 745 struct mpic *mpic = mpic_from_irq(irq); 746 unsigned int src = mpic_irq_to_hw(irq); 747 748 mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(irq)->status); 749 mpic_mask_irq(irq); 750 } 751 752 static void mpic_end_ht_irq(unsigned int irq) 753 { 754 struct mpic *mpic = mpic_from_irq(irq); 755 unsigned int src = mpic_irq_to_hw(irq); 756 757 #ifdef DEBUG_IRQ 758 DBG("%s: end_irq: %d\n", mpic->name, irq); 759 #endif 760 /* We always EOI on end_irq() even for edge interrupts since that 761 * should only lower the priority, the MPIC should have properly 762 * latched another edge interrupt coming in anyway 763 */ 764 765 if (irq_to_desc(irq)->status & IRQ_LEVEL) 766 mpic_ht_end_irq(mpic, src); 767 mpic_eoi(mpic); 768 } 769 #endif /* !CONFIG_MPIC_U3_HT_IRQS */ 770 771 #ifdef CONFIG_SMP 772 773 static void mpic_unmask_ipi(unsigned int irq) 774 { 775 struct mpic *mpic = mpic_from_ipi(irq); 776 unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]; 777 778 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src); 779 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); 780 } 781 782 static void mpic_mask_ipi(unsigned int irq) 783 { 784 /* NEVER disable an IPI... that's just plain wrong! */ 785 } 786 787 static void mpic_end_ipi(unsigned int irq) 788 { 789 struct mpic *mpic = mpic_from_ipi(irq); 790 791 /* 792 * IPIs are marked IRQ_PER_CPU. This has the side effect of 793 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from 794 * applying to them. We EOI them late to avoid re-entering. 795 * We mark IPI's with IRQF_DISABLED as they must run with 796 * irqs disabled. 797 */ 798 mpic_eoi(mpic); 799 } 800 801 #endif /* CONFIG_SMP */ 802 803 int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask) 804 { 805 struct mpic *mpic = mpic_from_irq(irq); 806 unsigned int src = mpic_irq_to_hw(irq); 807 808 if (mpic->flags & MPIC_SINGLE_DEST_CPU) { 809 int cpuid = irq_choose_cpu(cpumask); 810 811 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); 812 } else { 813 cpumask_var_t tmp; 814 815 alloc_cpumask_var(&tmp, GFP_KERNEL); 816 817 cpumask_and(tmp, cpumask, cpu_online_mask); 818 819 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 820 mpic_physmask(cpumask_bits(tmp)[0])); 821 822 free_cpumask_var(tmp); 823 } 824 825 return 0; 826 } 827 828 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) 829 { 830 /* Now convert sense value */ 831 switch(type & IRQ_TYPE_SENSE_MASK) { 832 case IRQ_TYPE_EDGE_RISING: 833 return MPIC_INFO(VECPRI_SENSE_EDGE) | 834 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 835 case IRQ_TYPE_EDGE_FALLING: 836 case IRQ_TYPE_EDGE_BOTH: 837 return MPIC_INFO(VECPRI_SENSE_EDGE) | 838 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 839 case IRQ_TYPE_LEVEL_HIGH: 840 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 841 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 842 case IRQ_TYPE_LEVEL_LOW: 843 default: 844 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 845 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 846 } 847 } 848 849 int mpic_set_irq_type(unsigned int virq, unsigned int flow_type) 850 { 851 struct mpic *mpic = mpic_from_irq(virq); 852 unsigned int src = mpic_irq_to_hw(virq); 853 struct irq_desc *desc = irq_to_desc(virq); 854 unsigned int vecpri, vold, vnew; 855 856 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", 857 mpic, virq, src, flow_type); 858 859 if (src >= mpic->irq_count) 860 return -EINVAL; 861 862 if (flow_type == IRQ_TYPE_NONE) 863 if (mpic->senses && src < mpic->senses_count) 864 flow_type = mpic->senses[src]; 865 if (flow_type == IRQ_TYPE_NONE) 866 flow_type = IRQ_TYPE_LEVEL_LOW; 867 868 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 869 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; 870 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 871 desc->status |= IRQ_LEVEL; 872 873 if (mpic_is_ht_interrupt(mpic, src)) 874 vecpri = MPIC_VECPRI_POLARITY_POSITIVE | 875 MPIC_VECPRI_SENSE_EDGE; 876 else 877 vecpri = mpic_type_to_vecpri(mpic, flow_type); 878 879 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 880 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | 881 MPIC_INFO(VECPRI_SENSE_MASK)); 882 vnew |= vecpri; 883 if (vold != vnew) 884 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); 885 886 return 0; 887 } 888 889 void mpic_set_vector(unsigned int virq, unsigned int vector) 890 { 891 struct mpic *mpic = mpic_from_irq(virq); 892 unsigned int src = mpic_irq_to_hw(virq); 893 unsigned int vecpri; 894 895 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", 896 mpic, virq, src, vector); 897 898 if (src >= mpic->irq_count) 899 return; 900 901 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 902 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK); 903 vecpri |= vector; 904 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 905 } 906 907 static struct irq_chip mpic_irq_chip = { 908 .mask = mpic_mask_irq, 909 .unmask = mpic_unmask_irq, 910 .eoi = mpic_end_irq, 911 .set_type = mpic_set_irq_type, 912 }; 913 914 #ifdef CONFIG_SMP 915 static struct irq_chip mpic_ipi_chip = { 916 .mask = mpic_mask_ipi, 917 .unmask = mpic_unmask_ipi, 918 .eoi = mpic_end_ipi, 919 }; 920 #endif /* CONFIG_SMP */ 921 922 #ifdef CONFIG_MPIC_U3_HT_IRQS 923 static struct irq_chip mpic_irq_ht_chip = { 924 .startup = mpic_startup_ht_irq, 925 .shutdown = mpic_shutdown_ht_irq, 926 .mask = mpic_mask_irq, 927 .unmask = mpic_unmask_ht_irq, 928 .eoi = mpic_end_ht_irq, 929 .set_type = mpic_set_irq_type, 930 }; 931 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 932 933 934 static int mpic_host_match(struct irq_host *h, struct device_node *node) 935 { 936 /* Exact match, unless mpic node is NULL */ 937 return h->of_node == NULL || h->of_node == node; 938 } 939 940 static int mpic_host_map(struct irq_host *h, unsigned int virq, 941 irq_hw_number_t hw) 942 { 943 struct mpic *mpic = h->host_data; 944 struct irq_chip *chip; 945 946 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); 947 948 if (hw == mpic->spurious_vec) 949 return -EINVAL; 950 if (mpic->protected && test_bit(hw, mpic->protected)) 951 return -EINVAL; 952 953 #ifdef CONFIG_SMP 954 else if (hw >= mpic->ipi_vecs[0]) { 955 WARN_ON(!(mpic->flags & MPIC_PRIMARY)); 956 957 DBG("mpic: mapping as IPI\n"); 958 set_irq_chip_data(virq, mpic); 959 set_irq_chip_and_handler(virq, &mpic->hc_ipi, 960 handle_percpu_irq); 961 return 0; 962 } 963 #endif /* CONFIG_SMP */ 964 965 if (hw >= mpic->irq_count) 966 return -EINVAL; 967 968 mpic_msi_reserve_hwirq(mpic, hw); 969 970 /* Default chip */ 971 chip = &mpic->hc_irq; 972 973 #ifdef CONFIG_MPIC_U3_HT_IRQS 974 /* Check for HT interrupts, override vecpri */ 975 if (mpic_is_ht_interrupt(mpic, hw)) 976 chip = &mpic->hc_ht_irq; 977 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 978 979 DBG("mpic: mapping to irq chip @%p\n", chip); 980 981 set_irq_chip_data(virq, mpic); 982 set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq); 983 984 /* Set default irq type */ 985 set_irq_type(virq, IRQ_TYPE_NONE); 986 987 return 0; 988 } 989 990 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, 991 const u32 *intspec, unsigned int intsize, 992 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 993 994 { 995 static unsigned char map_mpic_senses[4] = { 996 IRQ_TYPE_EDGE_RISING, 997 IRQ_TYPE_LEVEL_LOW, 998 IRQ_TYPE_LEVEL_HIGH, 999 IRQ_TYPE_EDGE_FALLING, 1000 }; 1001 1002 *out_hwirq = intspec[0]; 1003 if (intsize > 1) { 1004 u32 mask = 0x3; 1005 1006 /* Apple invented a new race of encoding on machines with 1007 * an HT APIC. They encode, among others, the index within 1008 * the HT APIC. We don't care about it here since thankfully, 1009 * it appears that they have the APIC already properly 1010 * configured, and thus our current fixup code that reads the 1011 * APIC config works fine. However, we still need to mask out 1012 * bits in the specifier to make sure we only get bit 0 which 1013 * is the level/edge bit (the only sense bit exposed by Apple), 1014 * as their bit 1 means something else. 1015 */ 1016 if (machine_is(powermac)) 1017 mask = 0x1; 1018 *out_flags = map_mpic_senses[intspec[1] & mask]; 1019 } else 1020 *out_flags = IRQ_TYPE_NONE; 1021 1022 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", 1023 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); 1024 1025 return 0; 1026 } 1027 1028 static struct irq_host_ops mpic_host_ops = { 1029 .match = mpic_host_match, 1030 .map = mpic_host_map, 1031 .xlate = mpic_host_xlate, 1032 }; 1033 1034 /* 1035 * Exported functions 1036 */ 1037 1038 struct mpic * __init mpic_alloc(struct device_node *node, 1039 phys_addr_t phys_addr, 1040 unsigned int flags, 1041 unsigned int isu_size, 1042 unsigned int irq_count, 1043 const char *name) 1044 { 1045 struct mpic *mpic; 1046 u32 greg_feature; 1047 const char *vers; 1048 int i; 1049 int intvec_top; 1050 u64 paddr = phys_addr; 1051 1052 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); 1053 if (mpic == NULL) 1054 return NULL; 1055 1056 mpic->name = name; 1057 1058 mpic->hc_irq = mpic_irq_chip; 1059 mpic->hc_irq.name = name; 1060 if (flags & MPIC_PRIMARY) 1061 mpic->hc_irq.set_affinity = mpic_set_affinity; 1062 #ifdef CONFIG_MPIC_U3_HT_IRQS 1063 mpic->hc_ht_irq = mpic_irq_ht_chip; 1064 mpic->hc_ht_irq.name = name; 1065 if (flags & MPIC_PRIMARY) 1066 mpic->hc_ht_irq.set_affinity = mpic_set_affinity; 1067 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 1068 1069 #ifdef CONFIG_SMP 1070 mpic->hc_ipi = mpic_ipi_chip; 1071 mpic->hc_ipi.name = name; 1072 #endif /* CONFIG_SMP */ 1073 1074 mpic->flags = flags; 1075 mpic->isu_size = isu_size; 1076 mpic->irq_count = irq_count; 1077 mpic->num_sources = 0; /* so far */ 1078 1079 if (flags & MPIC_LARGE_VECTORS) 1080 intvec_top = 2047; 1081 else 1082 intvec_top = 255; 1083 1084 mpic->timer_vecs[0] = intvec_top - 8; 1085 mpic->timer_vecs[1] = intvec_top - 7; 1086 mpic->timer_vecs[2] = intvec_top - 6; 1087 mpic->timer_vecs[3] = intvec_top - 5; 1088 mpic->ipi_vecs[0] = intvec_top - 4; 1089 mpic->ipi_vecs[1] = intvec_top - 3; 1090 mpic->ipi_vecs[2] = intvec_top - 2; 1091 mpic->ipi_vecs[3] = intvec_top - 1; 1092 mpic->spurious_vec = intvec_top; 1093 1094 /* Check for "big-endian" in device-tree */ 1095 if (node && of_get_property(node, "big-endian", NULL) != NULL) 1096 mpic->flags |= MPIC_BIG_ENDIAN; 1097 1098 /* Look for protected sources */ 1099 if (node) { 1100 int psize; 1101 unsigned int bits, mapsize; 1102 const u32 *psrc = 1103 of_get_property(node, "protected-sources", &psize); 1104 if (psrc) { 1105 psize /= 4; 1106 bits = intvec_top + 1; 1107 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long); 1108 mpic->protected = kzalloc(mapsize, GFP_KERNEL); 1109 BUG_ON(mpic->protected == NULL); 1110 for (i = 0; i < psize; i++) { 1111 if (psrc[i] > intvec_top) 1112 continue; 1113 __set_bit(psrc[i], mpic->protected); 1114 } 1115 } 1116 } 1117 1118 #ifdef CONFIG_MPIC_WEIRD 1119 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)]; 1120 #endif 1121 1122 /* default register type */ 1123 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ? 1124 mpic_access_mmio_be : mpic_access_mmio_le; 1125 1126 /* If no physical address is passed in, a device-node is mandatory */ 1127 BUG_ON(paddr == 0 && node == NULL); 1128 1129 /* If no physical address passed in, check if it's dcr based */ 1130 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) { 1131 #ifdef CONFIG_PPC_DCR 1132 mpic->flags |= MPIC_USES_DCR; 1133 mpic->reg_type = mpic_access_dcr; 1134 #else 1135 BUG(); 1136 #endif /* CONFIG_PPC_DCR */ 1137 } 1138 1139 /* If the MPIC is not DCR based, and no physical address was passed 1140 * in, try to obtain one 1141 */ 1142 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) { 1143 const u32 *reg = of_get_property(node, "reg", NULL); 1144 BUG_ON(reg == NULL); 1145 paddr = of_translate_address(node, reg); 1146 BUG_ON(paddr == OF_BAD_ADDR); 1147 } 1148 1149 /* Map the global registers */ 1150 mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); 1151 mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); 1152 1153 /* Reset */ 1154 if (flags & MPIC_WANTS_RESET) { 1155 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1156 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1157 | MPIC_GREG_GCONF_RESET); 1158 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1159 & MPIC_GREG_GCONF_RESET) 1160 mb(); 1161 } 1162 1163 /* CoreInt */ 1164 if (flags & MPIC_ENABLE_COREINT) 1165 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1166 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1167 | MPIC_GREG_GCONF_COREINT); 1168 1169 if (flags & MPIC_ENABLE_MCK) 1170 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1171 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1172 | MPIC_GREG_GCONF_MCK); 1173 1174 /* Read feature register, calculate num CPUs and, for non-ISU 1175 * MPICs, num sources as well. On ISU MPICs, sources are counted 1176 * as ISUs are added 1177 */ 1178 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); 1179 mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK) 1180 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; 1181 if (isu_size == 0) { 1182 if (flags & MPIC_BROKEN_FRR_NIRQS) 1183 mpic->num_sources = mpic->irq_count; 1184 else 1185 mpic->num_sources = 1186 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) 1187 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; 1188 } 1189 1190 /* Map the per-CPU registers */ 1191 for (i = 0; i < mpic->num_cpus; i++) { 1192 mpic_map(mpic, node, paddr, &mpic->cpuregs[i], 1193 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), 1194 0x1000); 1195 } 1196 1197 /* Initialize main ISU if none provided */ 1198 if (mpic->isu_size == 0) { 1199 mpic->isu_size = mpic->num_sources; 1200 mpic_map(mpic, node, paddr, &mpic->isus[0], 1201 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1202 } 1203 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 1204 mpic->isu_mask = (1 << mpic->isu_shift) - 1; 1205 1206 mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 1207 isu_size ? isu_size : mpic->num_sources, 1208 &mpic_host_ops, 1209 flags & MPIC_LARGE_VECTORS ? 2048 : 256); 1210 if (mpic->irqhost == NULL) 1211 return NULL; 1212 1213 mpic->irqhost->host_data = mpic; 1214 1215 /* Display version */ 1216 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) { 1217 case 1: 1218 vers = "1.0"; 1219 break; 1220 case 2: 1221 vers = "1.2"; 1222 break; 1223 case 3: 1224 vers = "1.3"; 1225 break; 1226 default: 1227 vers = "<unknown>"; 1228 break; 1229 } 1230 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," 1231 " max %d CPUs\n", 1232 name, vers, (unsigned long long)paddr, mpic->num_cpus); 1233 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", 1234 mpic->isu_size, mpic->isu_shift, mpic->isu_mask); 1235 1236 mpic->next = mpics; 1237 mpics = mpic; 1238 1239 if (flags & MPIC_PRIMARY) { 1240 mpic_primary = mpic; 1241 irq_set_default_host(mpic->irqhost); 1242 } 1243 1244 return mpic; 1245 } 1246 1247 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, 1248 phys_addr_t paddr) 1249 { 1250 unsigned int isu_first = isu_num * mpic->isu_size; 1251 1252 BUG_ON(isu_num >= MPIC_MAX_ISU); 1253 1254 mpic_map(mpic, mpic->irqhost->of_node, 1255 paddr, &mpic->isus[isu_num], 0, 1256 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1257 1258 if ((isu_first + mpic->isu_size) > mpic->num_sources) 1259 mpic->num_sources = isu_first + mpic->isu_size; 1260 } 1261 1262 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) 1263 { 1264 mpic->senses = senses; 1265 mpic->senses_count = count; 1266 } 1267 1268 void __init mpic_init(struct mpic *mpic) 1269 { 1270 int i; 1271 int cpu; 1272 1273 BUG_ON(mpic->num_sources == 0); 1274 1275 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); 1276 1277 /* Set current processor priority to max */ 1278 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1279 1280 /* Initialize timers: just disable them all */ 1281 for (i = 0; i < 4; i++) { 1282 mpic_write(mpic->tmregs, 1283 i * MPIC_INFO(TIMER_STRIDE) + 1284 MPIC_INFO(TIMER_DESTINATION), 0); 1285 mpic_write(mpic->tmregs, 1286 i * MPIC_INFO(TIMER_STRIDE) + 1287 MPIC_INFO(TIMER_VECTOR_PRI), 1288 MPIC_VECPRI_MASK | 1289 (mpic->timer_vecs[0] + i)); 1290 } 1291 1292 /* Initialize IPIs to our reserved vectors and mark them disabled for now */ 1293 mpic_test_broken_ipi(mpic); 1294 for (i = 0; i < 4; i++) { 1295 mpic_ipi_write(i, 1296 MPIC_VECPRI_MASK | 1297 (10 << MPIC_VECPRI_PRIORITY_SHIFT) | 1298 (mpic->ipi_vecs[0] + i)); 1299 } 1300 1301 /* Initialize interrupt sources */ 1302 if (mpic->irq_count == 0) 1303 mpic->irq_count = mpic->num_sources; 1304 1305 /* Do the HT PIC fixups on U3 broken mpic */ 1306 DBG("MPIC flags: %x\n", mpic->flags); 1307 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) { 1308 mpic_scan_ht_pics(mpic); 1309 mpic_u3msi_init(mpic); 1310 } 1311 1312 mpic_pasemi_msi_init(mpic); 1313 1314 if (mpic->flags & MPIC_PRIMARY) 1315 cpu = hard_smp_processor_id(); 1316 else 1317 cpu = 0; 1318 1319 for (i = 0; i < mpic->num_sources; i++) { 1320 /* start with vector = source number, and masked */ 1321 u32 vecpri = MPIC_VECPRI_MASK | i | 1322 (8 << MPIC_VECPRI_PRIORITY_SHIFT); 1323 1324 /* check if protected */ 1325 if (mpic->protected && test_bit(i, mpic->protected)) 1326 continue; 1327 /* init hw */ 1328 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 1329 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); 1330 } 1331 1332 /* Init spurious vector */ 1333 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); 1334 1335 /* Disable 8259 passthrough, if supported */ 1336 if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) 1337 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1338 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1339 | MPIC_GREG_GCONF_8259_PTHROU_DIS); 1340 1341 if (mpic->flags & MPIC_NO_BIAS) 1342 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1343 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1344 | MPIC_GREG_GCONF_NO_BIAS); 1345 1346 /* Set current processor priority to 0 */ 1347 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 1348 1349 #ifdef CONFIG_PM 1350 /* allocate memory to save mpic state */ 1351 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data), 1352 GFP_KERNEL); 1353 BUG_ON(mpic->save_data == NULL); 1354 #endif 1355 } 1356 1357 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) 1358 { 1359 u32 v; 1360 1361 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1362 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; 1363 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); 1364 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1365 } 1366 1367 void __init mpic_set_serial_int(struct mpic *mpic, int enable) 1368 { 1369 unsigned long flags; 1370 u32 v; 1371 1372 raw_spin_lock_irqsave(&mpic_lock, flags); 1373 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1374 if (enable) 1375 v |= MPIC_GREG_GLOBAL_CONF_1_SIE; 1376 else 1377 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; 1378 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1379 raw_spin_unlock_irqrestore(&mpic_lock, flags); 1380 } 1381 1382 void mpic_irq_set_priority(unsigned int irq, unsigned int pri) 1383 { 1384 struct mpic *mpic = mpic_find(irq); 1385 unsigned int src = mpic_irq_to_hw(irq); 1386 unsigned long flags; 1387 u32 reg; 1388 1389 if (!mpic) 1390 return; 1391 1392 raw_spin_lock_irqsave(&mpic_lock, flags); 1393 if (mpic_is_ipi(mpic, irq)) { 1394 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & 1395 ~MPIC_VECPRI_PRIORITY_MASK; 1396 mpic_ipi_write(src - mpic->ipi_vecs[0], 1397 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1398 } else { 1399 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) 1400 & ~MPIC_VECPRI_PRIORITY_MASK; 1401 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 1402 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1403 } 1404 raw_spin_unlock_irqrestore(&mpic_lock, flags); 1405 } 1406 1407 void mpic_setup_this_cpu(void) 1408 { 1409 #ifdef CONFIG_SMP 1410 struct mpic *mpic = mpic_primary; 1411 unsigned long flags; 1412 u32 msk = 1 << hard_smp_processor_id(); 1413 unsigned int i; 1414 1415 BUG_ON(mpic == NULL); 1416 1417 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1418 1419 raw_spin_lock_irqsave(&mpic_lock, flags); 1420 1421 /* let the mpic know we want intrs. default affinity is 0xffffffff 1422 * until changed via /proc. That's how it's done on x86. If we want 1423 * it differently, then we should make sure we also change the default 1424 * values of irq_desc[].affinity in irq.c. 1425 */ 1426 if (distribute_irqs) { 1427 for (i = 0; i < mpic->num_sources ; i++) 1428 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1429 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); 1430 } 1431 1432 /* Set current processor priority to 0 */ 1433 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 1434 1435 raw_spin_unlock_irqrestore(&mpic_lock, flags); 1436 #endif /* CONFIG_SMP */ 1437 } 1438 1439 int mpic_cpu_get_priority(void) 1440 { 1441 struct mpic *mpic = mpic_primary; 1442 1443 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); 1444 } 1445 1446 void mpic_cpu_set_priority(int prio) 1447 { 1448 struct mpic *mpic = mpic_primary; 1449 1450 prio &= MPIC_CPU_TASKPRI_MASK; 1451 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); 1452 } 1453 1454 void mpic_teardown_this_cpu(int secondary) 1455 { 1456 struct mpic *mpic = mpic_primary; 1457 unsigned long flags; 1458 u32 msk = 1 << hard_smp_processor_id(); 1459 unsigned int i; 1460 1461 BUG_ON(mpic == NULL); 1462 1463 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1464 raw_spin_lock_irqsave(&mpic_lock, flags); 1465 1466 /* let the mpic know we don't want intrs. */ 1467 for (i = 0; i < mpic->num_sources ; i++) 1468 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1469 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); 1470 1471 /* Set current processor priority to max */ 1472 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1473 /* We need to EOI the IPI since not all platforms reset the MPIC 1474 * on boot and new interrupts wouldn't get delivered otherwise. 1475 */ 1476 mpic_eoi(mpic); 1477 1478 raw_spin_unlock_irqrestore(&mpic_lock, flags); 1479 } 1480 1481 1482 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) 1483 { 1484 u32 src; 1485 1486 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); 1487 #ifdef DEBUG_LOW 1488 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); 1489 #endif 1490 if (unlikely(src == mpic->spurious_vec)) { 1491 if (mpic->flags & MPIC_SPV_EOI) 1492 mpic_eoi(mpic); 1493 return NO_IRQ; 1494 } 1495 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { 1496 if (printk_ratelimit()) 1497 printk(KERN_WARNING "%s: Got protected source %d !\n", 1498 mpic->name, (int)src); 1499 mpic_eoi(mpic); 1500 return NO_IRQ; 1501 } 1502 1503 return irq_linear_revmap(mpic->irqhost, src); 1504 } 1505 1506 unsigned int mpic_get_one_irq(struct mpic *mpic) 1507 { 1508 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); 1509 } 1510 1511 unsigned int mpic_get_irq(void) 1512 { 1513 struct mpic *mpic = mpic_primary; 1514 1515 BUG_ON(mpic == NULL); 1516 1517 return mpic_get_one_irq(mpic); 1518 } 1519 1520 unsigned int mpic_get_coreint_irq(void) 1521 { 1522 #ifdef CONFIG_BOOKE 1523 struct mpic *mpic = mpic_primary; 1524 u32 src; 1525 1526 BUG_ON(mpic == NULL); 1527 1528 src = mfspr(SPRN_EPR); 1529 1530 if (unlikely(src == mpic->spurious_vec)) { 1531 if (mpic->flags & MPIC_SPV_EOI) 1532 mpic_eoi(mpic); 1533 return NO_IRQ; 1534 } 1535 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { 1536 if (printk_ratelimit()) 1537 printk(KERN_WARNING "%s: Got protected source %d !\n", 1538 mpic->name, (int)src); 1539 return NO_IRQ; 1540 } 1541 1542 return irq_linear_revmap(mpic->irqhost, src); 1543 #else 1544 return NO_IRQ; 1545 #endif 1546 } 1547 1548 unsigned int mpic_get_mcirq(void) 1549 { 1550 struct mpic *mpic = mpic_primary; 1551 1552 BUG_ON(mpic == NULL); 1553 1554 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); 1555 } 1556 1557 #ifdef CONFIG_SMP 1558 void mpic_request_ipis(void) 1559 { 1560 struct mpic *mpic = mpic_primary; 1561 int i; 1562 BUG_ON(mpic == NULL); 1563 1564 printk(KERN_INFO "mpic: requesting IPIs...\n"); 1565 1566 for (i = 0; i < 4; i++) { 1567 unsigned int vipi = irq_create_mapping(mpic->irqhost, 1568 mpic->ipi_vecs[0] + i); 1569 if (vipi == NO_IRQ) { 1570 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]); 1571 continue; 1572 } 1573 smp_request_message_ipi(vipi, i); 1574 } 1575 } 1576 1577 static void mpic_send_ipi(unsigned int ipi_no, const struct cpumask *cpu_mask) 1578 { 1579 struct mpic *mpic = mpic_primary; 1580 1581 BUG_ON(mpic == NULL); 1582 1583 #ifdef DEBUG_IPI 1584 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); 1585 #endif 1586 1587 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + 1588 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), 1589 mpic_physmask(cpumask_bits(cpu_mask)[0])); 1590 } 1591 1592 void smp_mpic_message_pass(int target, int msg) 1593 { 1594 cpumask_var_t tmp; 1595 1596 /* make sure we're sending something that translates to an IPI */ 1597 if ((unsigned int)msg > 3) { 1598 printk("SMP %d: smp_message_pass: unknown msg %d\n", 1599 smp_processor_id(), msg); 1600 return; 1601 } 1602 switch (target) { 1603 case MSG_ALL: 1604 mpic_send_ipi(msg, cpu_online_mask); 1605 break; 1606 case MSG_ALL_BUT_SELF: 1607 alloc_cpumask_var(&tmp, GFP_NOWAIT); 1608 cpumask_andnot(tmp, cpu_online_mask, 1609 cpumask_of(smp_processor_id())); 1610 mpic_send_ipi(msg, tmp); 1611 free_cpumask_var(tmp); 1612 break; 1613 default: 1614 mpic_send_ipi(msg, cpumask_of(target)); 1615 break; 1616 } 1617 } 1618 1619 int __init smp_mpic_probe(void) 1620 { 1621 int nr_cpus; 1622 1623 DBG("smp_mpic_probe()...\n"); 1624 1625 nr_cpus = cpumask_weight(cpu_possible_mask); 1626 1627 DBG("nr_cpus: %d\n", nr_cpus); 1628 1629 if (nr_cpus > 1) 1630 mpic_request_ipis(); 1631 1632 return nr_cpus; 1633 } 1634 1635 void __devinit smp_mpic_setup_cpu(int cpu) 1636 { 1637 mpic_setup_this_cpu(); 1638 } 1639 #endif /* CONFIG_SMP */ 1640 1641 #ifdef CONFIG_PM 1642 static int mpic_suspend(struct sys_device *dev, pm_message_t state) 1643 { 1644 struct mpic *mpic = container_of(dev, struct mpic, sysdev); 1645 int i; 1646 1647 for (i = 0; i < mpic->num_sources; i++) { 1648 mpic->save_data[i].vecprio = 1649 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); 1650 mpic->save_data[i].dest = 1651 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); 1652 } 1653 1654 return 0; 1655 } 1656 1657 static int mpic_resume(struct sys_device *dev) 1658 { 1659 struct mpic *mpic = container_of(dev, struct mpic, sysdev); 1660 int i; 1661 1662 for (i = 0; i < mpic->num_sources; i++) { 1663 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), 1664 mpic->save_data[i].vecprio); 1665 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1666 mpic->save_data[i].dest); 1667 1668 #ifdef CONFIG_MPIC_U3_HT_IRQS 1669 if (mpic->fixups) { 1670 struct mpic_irq_fixup *fixup = &mpic->fixups[i]; 1671 1672 if (fixup->base) { 1673 /* we use the lowest bit in an inverted meaning */ 1674 if ((mpic->save_data[i].fixup_data & 1) == 0) 1675 continue; 1676 1677 /* Enable and configure */ 1678 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 1679 1680 writel(mpic->save_data[i].fixup_data & ~1, 1681 fixup->base + 4); 1682 } 1683 } 1684 #endif 1685 } /* end for loop */ 1686 1687 return 0; 1688 } 1689 #endif 1690 1691 static struct sysdev_class mpic_sysclass = { 1692 #ifdef CONFIG_PM 1693 .resume = mpic_resume, 1694 .suspend = mpic_suspend, 1695 #endif 1696 .name = "mpic", 1697 }; 1698 1699 static int mpic_init_sys(void) 1700 { 1701 struct mpic *mpic = mpics; 1702 int error, id = 0; 1703 1704 error = sysdev_class_register(&mpic_sysclass); 1705 1706 while (mpic && !error) { 1707 mpic->sysdev.cls = &mpic_sysclass; 1708 mpic->sysdev.id = id++; 1709 error = sysdev_register(&mpic->sysdev); 1710 mpic = mpic->next; 1711 } 1712 return error; 1713 } 1714 1715 device_initcall(mpic_init_sys); 1716