1 /* 2 * arch/powerpc/kernel/mpic.c 3 * 4 * Driver for interrupt controllers following the OpenPIC standard, the 5 * common implementation beeing IBM's MPIC. This driver also can deal 6 * with various broken implementations of this HW. 7 * 8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. 9 * Copyright 2010-2012 Freescale Semiconductor, Inc. 10 * 11 * This file is subject to the terms and conditions of the GNU General Public 12 * License. See the file COPYING in the main directory of this archive 13 * for more details. 14 */ 15 16 #undef DEBUG 17 #undef DEBUG_IPI 18 #undef DEBUG_IRQ 19 #undef DEBUG_LOW 20 21 #include <linux/types.h> 22 #include <linux/kernel.h> 23 #include <linux/init.h> 24 #include <linux/irq.h> 25 #include <linux/smp.h> 26 #include <linux/interrupt.h> 27 #include <linux/spinlock.h> 28 #include <linux/pci.h> 29 #include <linux/slab.h> 30 #include <linux/syscore_ops.h> 31 #include <linux/ratelimit.h> 32 33 #include <asm/ptrace.h> 34 #include <asm/signal.h> 35 #include <asm/io.h> 36 #include <asm/pgtable.h> 37 #include <asm/irq.h> 38 #include <asm/machdep.h> 39 #include <asm/mpic.h> 40 #include <asm/smp.h> 41 42 #include "mpic.h" 43 44 #ifdef DEBUG 45 #define DBG(fmt...) printk(fmt) 46 #else 47 #define DBG(fmt...) 48 #endif 49 50 struct bus_type mpic_subsys = { 51 .name = "mpic", 52 .dev_name = "mpic", 53 }; 54 EXPORT_SYMBOL_GPL(mpic_subsys); 55 56 static struct mpic *mpics; 57 static struct mpic *mpic_primary; 58 static DEFINE_RAW_SPINLOCK(mpic_lock); 59 60 #ifdef CONFIG_PPC32 /* XXX for now */ 61 #ifdef CONFIG_IRQ_ALL_CPUS 62 #define distribute_irqs (1) 63 #else 64 #define distribute_irqs (0) 65 #endif 66 #endif 67 68 #ifdef CONFIG_MPIC_WEIRD 69 static u32 mpic_infos[][MPIC_IDX_END] = { 70 [0] = { /* Original OpenPIC compatible MPIC */ 71 MPIC_GREG_BASE, 72 MPIC_GREG_FEATURE_0, 73 MPIC_GREG_GLOBAL_CONF_0, 74 MPIC_GREG_VENDOR_ID, 75 MPIC_GREG_IPI_VECTOR_PRI_0, 76 MPIC_GREG_IPI_STRIDE, 77 MPIC_GREG_SPURIOUS, 78 MPIC_GREG_TIMER_FREQ, 79 80 MPIC_TIMER_BASE, 81 MPIC_TIMER_STRIDE, 82 MPIC_TIMER_CURRENT_CNT, 83 MPIC_TIMER_BASE_CNT, 84 MPIC_TIMER_VECTOR_PRI, 85 MPIC_TIMER_DESTINATION, 86 87 MPIC_CPU_BASE, 88 MPIC_CPU_STRIDE, 89 MPIC_CPU_IPI_DISPATCH_0, 90 MPIC_CPU_IPI_DISPATCH_STRIDE, 91 MPIC_CPU_CURRENT_TASK_PRI, 92 MPIC_CPU_WHOAMI, 93 MPIC_CPU_INTACK, 94 MPIC_CPU_EOI, 95 MPIC_CPU_MCACK, 96 97 MPIC_IRQ_BASE, 98 MPIC_IRQ_STRIDE, 99 MPIC_IRQ_VECTOR_PRI, 100 MPIC_VECPRI_VECTOR_MASK, 101 MPIC_VECPRI_POLARITY_POSITIVE, 102 MPIC_VECPRI_POLARITY_NEGATIVE, 103 MPIC_VECPRI_SENSE_LEVEL, 104 MPIC_VECPRI_SENSE_EDGE, 105 MPIC_VECPRI_POLARITY_MASK, 106 MPIC_VECPRI_SENSE_MASK, 107 MPIC_IRQ_DESTINATION 108 }, 109 [1] = { /* Tsi108/109 PIC */ 110 TSI108_GREG_BASE, 111 TSI108_GREG_FEATURE_0, 112 TSI108_GREG_GLOBAL_CONF_0, 113 TSI108_GREG_VENDOR_ID, 114 TSI108_GREG_IPI_VECTOR_PRI_0, 115 TSI108_GREG_IPI_STRIDE, 116 TSI108_GREG_SPURIOUS, 117 TSI108_GREG_TIMER_FREQ, 118 119 TSI108_TIMER_BASE, 120 TSI108_TIMER_STRIDE, 121 TSI108_TIMER_CURRENT_CNT, 122 TSI108_TIMER_BASE_CNT, 123 TSI108_TIMER_VECTOR_PRI, 124 TSI108_TIMER_DESTINATION, 125 126 TSI108_CPU_BASE, 127 TSI108_CPU_STRIDE, 128 TSI108_CPU_IPI_DISPATCH_0, 129 TSI108_CPU_IPI_DISPATCH_STRIDE, 130 TSI108_CPU_CURRENT_TASK_PRI, 131 TSI108_CPU_WHOAMI, 132 TSI108_CPU_INTACK, 133 TSI108_CPU_EOI, 134 TSI108_CPU_MCACK, 135 136 TSI108_IRQ_BASE, 137 TSI108_IRQ_STRIDE, 138 TSI108_IRQ_VECTOR_PRI, 139 TSI108_VECPRI_VECTOR_MASK, 140 TSI108_VECPRI_POLARITY_POSITIVE, 141 TSI108_VECPRI_POLARITY_NEGATIVE, 142 TSI108_VECPRI_SENSE_LEVEL, 143 TSI108_VECPRI_SENSE_EDGE, 144 TSI108_VECPRI_POLARITY_MASK, 145 TSI108_VECPRI_SENSE_MASK, 146 TSI108_IRQ_DESTINATION 147 }, 148 }; 149 150 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] 151 152 #else /* CONFIG_MPIC_WEIRD */ 153 154 #define MPIC_INFO(name) MPIC_##name 155 156 #endif /* CONFIG_MPIC_WEIRD */ 157 158 static inline unsigned int mpic_processor_id(struct mpic *mpic) 159 { 160 unsigned int cpu = 0; 161 162 if (!(mpic->flags & MPIC_SECONDARY)) 163 cpu = hard_smp_processor_id(); 164 165 return cpu; 166 } 167 168 /* 169 * Register accessor functions 170 */ 171 172 173 static inline u32 _mpic_read(enum mpic_reg_type type, 174 struct mpic_reg_bank *rb, 175 unsigned int reg) 176 { 177 switch(type) { 178 #ifdef CONFIG_PPC_DCR 179 case mpic_access_dcr: 180 return dcr_read(rb->dhost, reg); 181 #endif 182 case mpic_access_mmio_be: 183 return in_be32(rb->base + (reg >> 2)); 184 case mpic_access_mmio_le: 185 default: 186 return in_le32(rb->base + (reg >> 2)); 187 } 188 } 189 190 static inline void _mpic_write(enum mpic_reg_type type, 191 struct mpic_reg_bank *rb, 192 unsigned int reg, u32 value) 193 { 194 switch(type) { 195 #ifdef CONFIG_PPC_DCR 196 case mpic_access_dcr: 197 dcr_write(rb->dhost, reg, value); 198 break; 199 #endif 200 case mpic_access_mmio_be: 201 out_be32(rb->base + (reg >> 2), value); 202 break; 203 case mpic_access_mmio_le: 204 default: 205 out_le32(rb->base + (reg >> 2), value); 206 break; 207 } 208 } 209 210 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) 211 { 212 enum mpic_reg_type type = mpic->reg_type; 213 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 214 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 215 216 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) 217 type = mpic_access_mmio_be; 218 return _mpic_read(type, &mpic->gregs, offset); 219 } 220 221 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) 222 { 223 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 224 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 225 226 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); 227 } 228 229 static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned int tm) 230 { 231 return (tm >> 2) * MPIC_TIMER_GROUP_STRIDE + 232 (tm & 3) * MPIC_INFO(TIMER_STRIDE); 233 } 234 235 static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm) 236 { 237 unsigned int offset = mpic_tm_offset(mpic, tm) + 238 MPIC_INFO(TIMER_VECTOR_PRI); 239 240 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset); 241 } 242 243 static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value) 244 { 245 unsigned int offset = mpic_tm_offset(mpic, tm) + 246 MPIC_INFO(TIMER_VECTOR_PRI); 247 248 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value); 249 } 250 251 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) 252 { 253 unsigned int cpu = mpic_processor_id(mpic); 254 255 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); 256 } 257 258 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) 259 { 260 unsigned int cpu = mpic_processor_id(mpic); 261 262 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); 263 } 264 265 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) 266 { 267 unsigned int isu = src_no >> mpic->isu_shift; 268 unsigned int idx = src_no & mpic->isu_mask; 269 unsigned int val; 270 271 val = _mpic_read(mpic->reg_type, &mpic->isus[isu], 272 reg + (idx * MPIC_INFO(IRQ_STRIDE))); 273 #ifdef CONFIG_MPIC_BROKEN_REGREAD 274 if (reg == 0) 275 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) | 276 mpic->isu_reg0_shadow[src_no]; 277 #endif 278 return val; 279 } 280 281 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, 282 unsigned int reg, u32 value) 283 { 284 unsigned int isu = src_no >> mpic->isu_shift; 285 unsigned int idx = src_no & mpic->isu_mask; 286 287 _mpic_write(mpic->reg_type, &mpic->isus[isu], 288 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); 289 290 #ifdef CONFIG_MPIC_BROKEN_REGREAD 291 if (reg == 0) 292 mpic->isu_reg0_shadow[src_no] = 293 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY); 294 #endif 295 } 296 297 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) 298 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) 299 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) 300 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) 301 #define mpic_tm_read(i) _mpic_tm_read(mpic,(i)) 302 #define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v)) 303 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) 304 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) 305 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) 306 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) 307 308 309 /* 310 * Low level utility functions 311 */ 312 313 314 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, 315 struct mpic_reg_bank *rb, unsigned int offset, 316 unsigned int size) 317 { 318 rb->base = ioremap(phys_addr + offset, size); 319 BUG_ON(rb->base == NULL); 320 } 321 322 #ifdef CONFIG_PPC_DCR 323 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, 324 unsigned int offset, unsigned int size) 325 { 326 phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0); 327 rb->dhost = dcr_map(mpic->node, phys_addr + offset, size); 328 BUG_ON(!DCR_MAP_OK(rb->dhost)); 329 } 330 331 static inline void mpic_map(struct mpic *mpic, 332 phys_addr_t phys_addr, struct mpic_reg_bank *rb, 333 unsigned int offset, unsigned int size) 334 { 335 if (mpic->flags & MPIC_USES_DCR) 336 _mpic_map_dcr(mpic, rb, offset, size); 337 else 338 _mpic_map_mmio(mpic, phys_addr, rb, offset, size); 339 } 340 #else /* CONFIG_PPC_DCR */ 341 #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) 342 #endif /* !CONFIG_PPC_DCR */ 343 344 345 346 /* Check if we have one of those nice broken MPICs with a flipped endian on 347 * reads from IPI registers 348 */ 349 static void __init mpic_test_broken_ipi(struct mpic *mpic) 350 { 351 u32 r; 352 353 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); 354 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); 355 356 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { 357 printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); 358 mpic->flags |= MPIC_BROKEN_IPI; 359 } 360 } 361 362 #ifdef CONFIG_MPIC_U3_HT_IRQS 363 364 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) 365 * to force the edge setting on the MPIC and do the ack workaround. 366 */ 367 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 368 { 369 if (source >= 128 || !mpic->fixups) 370 return 0; 371 return mpic->fixups[source].base != NULL; 372 } 373 374 375 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) 376 { 377 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 378 379 if (fixup->applebase) { 380 unsigned int soff = (fixup->index >> 3) & ~3; 381 unsigned int mask = 1U << (fixup->index & 0x1f); 382 writel(mask, fixup->applebase + soff); 383 } else { 384 raw_spin_lock(&mpic->fixup_lock); 385 writeb(0x11 + 2 * fixup->index, fixup->base + 2); 386 writel(fixup->data, fixup->base + 4); 387 raw_spin_unlock(&mpic->fixup_lock); 388 } 389 } 390 391 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, 392 bool level) 393 { 394 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 395 unsigned long flags; 396 u32 tmp; 397 398 if (fixup->base == NULL) 399 return; 400 401 DBG("startup_ht_interrupt(0x%x) index: %d\n", 402 source, fixup->index); 403 raw_spin_lock_irqsave(&mpic->fixup_lock, flags); 404 /* Enable and configure */ 405 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 406 tmp = readl(fixup->base + 4); 407 tmp &= ~(0x23U); 408 if (level) 409 tmp |= 0x22; 410 writel(tmp, fixup->base + 4); 411 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); 412 413 #ifdef CONFIG_PM 414 /* use the lowest bit inverted to the actual HW, 415 * set if this fixup was enabled, clear otherwise */ 416 mpic->save_data[source].fixup_data = tmp | 1; 417 #endif 418 } 419 420 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source) 421 { 422 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 423 unsigned long flags; 424 u32 tmp; 425 426 if (fixup->base == NULL) 427 return; 428 429 DBG("shutdown_ht_interrupt(0x%x)\n", source); 430 431 /* Disable */ 432 raw_spin_lock_irqsave(&mpic->fixup_lock, flags); 433 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 434 tmp = readl(fixup->base + 4); 435 tmp |= 1; 436 writel(tmp, fixup->base + 4); 437 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); 438 439 #ifdef CONFIG_PM 440 /* use the lowest bit inverted to the actual HW, 441 * set if this fixup was enabled, clear otherwise */ 442 mpic->save_data[source].fixup_data = tmp & ~1; 443 #endif 444 } 445 446 #ifdef CONFIG_PCI_MSI 447 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, 448 unsigned int devfn) 449 { 450 u8 __iomem *base; 451 u8 pos, flags; 452 u64 addr = 0; 453 454 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 455 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 456 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 457 if (id == PCI_CAP_ID_HT) { 458 id = readb(devbase + pos + 3); 459 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) 460 break; 461 } 462 } 463 464 if (pos == 0) 465 return; 466 467 base = devbase + pos; 468 469 flags = readb(base + HT_MSI_FLAGS); 470 if (!(flags & HT_MSI_FLAGS_FIXED)) { 471 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; 472 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); 473 } 474 475 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", 476 PCI_SLOT(devfn), PCI_FUNC(devfn), 477 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); 478 479 if (!(flags & HT_MSI_FLAGS_ENABLE)) 480 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); 481 } 482 #else 483 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, 484 unsigned int devfn) 485 { 486 return; 487 } 488 #endif 489 490 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, 491 unsigned int devfn, u32 vdid) 492 { 493 int i, irq, n; 494 u8 __iomem *base; 495 u32 tmp; 496 u8 pos; 497 498 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 499 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 500 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 501 if (id == PCI_CAP_ID_HT) { 502 id = readb(devbase + pos + 3); 503 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) 504 break; 505 } 506 } 507 if (pos == 0) 508 return; 509 510 base = devbase + pos; 511 writeb(0x01, base + 2); 512 n = (readl(base + 4) >> 16) & 0xff; 513 514 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" 515 " has %d irqs\n", 516 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); 517 518 for (i = 0; i <= n; i++) { 519 writeb(0x10 + 2 * i, base + 2); 520 tmp = readl(base + 4); 521 irq = (tmp >> 16) & 0xff; 522 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); 523 /* mask it , will be unmasked later */ 524 tmp |= 0x1; 525 writel(tmp, base + 4); 526 mpic->fixups[irq].index = i; 527 mpic->fixups[irq].base = base; 528 /* Apple HT PIC has a non-standard way of doing EOIs */ 529 if ((vdid & 0xffff) == 0x106b) 530 mpic->fixups[irq].applebase = devbase + 0x60; 531 else 532 mpic->fixups[irq].applebase = NULL; 533 writeb(0x11 + 2 * i, base + 2); 534 mpic->fixups[irq].data = readl(base + 4) | 0x80000000; 535 } 536 } 537 538 539 static void __init mpic_scan_ht_pics(struct mpic *mpic) 540 { 541 unsigned int devfn; 542 u8 __iomem *cfgspace; 543 544 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); 545 546 /* Allocate fixups array */ 547 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL); 548 BUG_ON(mpic->fixups == NULL); 549 550 /* Init spinlock */ 551 raw_spin_lock_init(&mpic->fixup_lock); 552 553 /* Map U3 config space. We assume all IO-APICs are on the primary bus 554 * so we only need to map 64kB. 555 */ 556 cfgspace = ioremap(0xf2000000, 0x10000); 557 BUG_ON(cfgspace == NULL); 558 559 /* Now we scan all slots. We do a very quick scan, we read the header 560 * type, vendor ID and device ID only, that's plenty enough 561 */ 562 for (devfn = 0; devfn < 0x100; devfn++) { 563 u8 __iomem *devbase = cfgspace + (devfn << 8); 564 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); 565 u32 l = readl(devbase + PCI_VENDOR_ID); 566 u16 s; 567 568 DBG("devfn %x, l: %x\n", devfn, l); 569 570 /* If no device, skip */ 571 if (l == 0xffffffff || l == 0x00000000 || 572 l == 0x0000ffff || l == 0xffff0000) 573 goto next; 574 /* Check if is supports capability lists */ 575 s = readw(devbase + PCI_STATUS); 576 if (!(s & PCI_STATUS_CAP_LIST)) 577 goto next; 578 579 mpic_scan_ht_pic(mpic, devbase, devfn, l); 580 mpic_scan_ht_msi(mpic, devbase, devfn); 581 582 next: 583 /* next device, if function 0 */ 584 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) 585 devfn += 7; 586 } 587 } 588 589 #else /* CONFIG_MPIC_U3_HT_IRQS */ 590 591 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 592 { 593 return 0; 594 } 595 596 static void __init mpic_scan_ht_pics(struct mpic *mpic) 597 { 598 } 599 600 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 601 602 /* Find an mpic associated with a given linux interrupt */ 603 static struct mpic *mpic_find(unsigned int irq) 604 { 605 if (irq < NUM_ISA_INTERRUPTS) 606 return NULL; 607 608 return irq_get_chip_data(irq); 609 } 610 611 /* Determine if the linux irq is an IPI */ 612 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src) 613 { 614 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); 615 } 616 617 /* Determine if the linux irq is a timer */ 618 static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src) 619 { 620 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]); 621 } 622 623 /* Convert a cpu mask from logical to physical cpu numbers. */ 624 static inline u32 mpic_physmask(u32 cpumask) 625 { 626 int i; 627 u32 mask = 0; 628 629 for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1) 630 mask |= (cpumask & 1) << get_hard_smp_processor_id(i); 631 return mask; 632 } 633 634 #ifdef CONFIG_SMP 635 /* Get the mpic structure from the IPI number */ 636 static inline struct mpic * mpic_from_ipi(struct irq_data *d) 637 { 638 return irq_data_get_irq_chip_data(d); 639 } 640 #endif 641 642 /* Get the mpic structure from the irq number */ 643 static inline struct mpic * mpic_from_irq(unsigned int irq) 644 { 645 return irq_get_chip_data(irq); 646 } 647 648 /* Get the mpic structure from the irq data */ 649 static inline struct mpic * mpic_from_irq_data(struct irq_data *d) 650 { 651 return irq_data_get_irq_chip_data(d); 652 } 653 654 /* Send an EOI */ 655 static inline void mpic_eoi(struct mpic *mpic) 656 { 657 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); 658 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); 659 } 660 661 /* 662 * Linux descriptor level callbacks 663 */ 664 665 666 void mpic_unmask_irq(struct irq_data *d) 667 { 668 unsigned int loops = 100000; 669 struct mpic *mpic = mpic_from_irq_data(d); 670 unsigned int src = irqd_to_hwirq(d); 671 672 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src); 673 674 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 675 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & 676 ~MPIC_VECPRI_MASK); 677 /* make sure mask gets to controller before we return to user */ 678 do { 679 if (!loops--) { 680 printk(KERN_ERR "%s: timeout on hwirq %u\n", 681 __func__, src); 682 break; 683 } 684 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); 685 } 686 687 void mpic_mask_irq(struct irq_data *d) 688 { 689 unsigned int loops = 100000; 690 struct mpic *mpic = mpic_from_irq_data(d); 691 unsigned int src = irqd_to_hwirq(d); 692 693 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src); 694 695 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 696 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | 697 MPIC_VECPRI_MASK); 698 699 /* make sure mask gets to controller before we return to user */ 700 do { 701 if (!loops--) { 702 printk(KERN_ERR "%s: timeout on hwirq %u\n", 703 __func__, src); 704 break; 705 } 706 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); 707 } 708 709 void mpic_end_irq(struct irq_data *d) 710 { 711 struct mpic *mpic = mpic_from_irq_data(d); 712 713 #ifdef DEBUG_IRQ 714 DBG("%s: end_irq: %d\n", mpic->name, d->irq); 715 #endif 716 /* We always EOI on end_irq() even for edge interrupts since that 717 * should only lower the priority, the MPIC should have properly 718 * latched another edge interrupt coming in anyway 719 */ 720 721 mpic_eoi(mpic); 722 } 723 724 #ifdef CONFIG_MPIC_U3_HT_IRQS 725 726 static void mpic_unmask_ht_irq(struct irq_data *d) 727 { 728 struct mpic *mpic = mpic_from_irq_data(d); 729 unsigned int src = irqd_to_hwirq(d); 730 731 mpic_unmask_irq(d); 732 733 if (irqd_is_level_type(d)) 734 mpic_ht_end_irq(mpic, src); 735 } 736 737 static unsigned int mpic_startup_ht_irq(struct irq_data *d) 738 { 739 struct mpic *mpic = mpic_from_irq_data(d); 740 unsigned int src = irqd_to_hwirq(d); 741 742 mpic_unmask_irq(d); 743 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d)); 744 745 return 0; 746 } 747 748 static void mpic_shutdown_ht_irq(struct irq_data *d) 749 { 750 struct mpic *mpic = mpic_from_irq_data(d); 751 unsigned int src = irqd_to_hwirq(d); 752 753 mpic_shutdown_ht_interrupt(mpic, src); 754 mpic_mask_irq(d); 755 } 756 757 static void mpic_end_ht_irq(struct irq_data *d) 758 { 759 struct mpic *mpic = mpic_from_irq_data(d); 760 unsigned int src = irqd_to_hwirq(d); 761 762 #ifdef DEBUG_IRQ 763 DBG("%s: end_irq: %d\n", mpic->name, d->irq); 764 #endif 765 /* We always EOI on end_irq() even for edge interrupts since that 766 * should only lower the priority, the MPIC should have properly 767 * latched another edge interrupt coming in anyway 768 */ 769 770 if (irqd_is_level_type(d)) 771 mpic_ht_end_irq(mpic, src); 772 mpic_eoi(mpic); 773 } 774 #endif /* !CONFIG_MPIC_U3_HT_IRQS */ 775 776 #ifdef CONFIG_SMP 777 778 static void mpic_unmask_ipi(struct irq_data *d) 779 { 780 struct mpic *mpic = mpic_from_ipi(d); 781 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0]; 782 783 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src); 784 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); 785 } 786 787 static void mpic_mask_ipi(struct irq_data *d) 788 { 789 /* NEVER disable an IPI... that's just plain wrong! */ 790 } 791 792 static void mpic_end_ipi(struct irq_data *d) 793 { 794 struct mpic *mpic = mpic_from_ipi(d); 795 796 /* 797 * IPIs are marked IRQ_PER_CPU. This has the side effect of 798 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from 799 * applying to them. We EOI them late to avoid re-entering. 800 */ 801 mpic_eoi(mpic); 802 } 803 804 #endif /* CONFIG_SMP */ 805 806 static void mpic_unmask_tm(struct irq_data *d) 807 { 808 struct mpic *mpic = mpic_from_irq_data(d); 809 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; 810 811 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src); 812 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK); 813 mpic_tm_read(src); 814 } 815 816 static void mpic_mask_tm(struct irq_data *d) 817 { 818 struct mpic *mpic = mpic_from_irq_data(d); 819 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; 820 821 mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK); 822 mpic_tm_read(src); 823 } 824 825 int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, 826 bool force) 827 { 828 struct mpic *mpic = mpic_from_irq_data(d); 829 unsigned int src = irqd_to_hwirq(d); 830 831 if (mpic->flags & MPIC_SINGLE_DEST_CPU) { 832 int cpuid = irq_choose_cpu(cpumask); 833 834 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); 835 } else { 836 u32 mask = cpumask_bits(cpumask)[0]; 837 838 mask &= cpumask_bits(cpu_online_mask)[0]; 839 840 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 841 mpic_physmask(mask)); 842 } 843 844 return IRQ_SET_MASK_OK; 845 } 846 847 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) 848 { 849 /* Now convert sense value */ 850 switch(type & IRQ_TYPE_SENSE_MASK) { 851 case IRQ_TYPE_EDGE_RISING: 852 return MPIC_INFO(VECPRI_SENSE_EDGE) | 853 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 854 case IRQ_TYPE_EDGE_FALLING: 855 case IRQ_TYPE_EDGE_BOTH: 856 return MPIC_INFO(VECPRI_SENSE_EDGE) | 857 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 858 case IRQ_TYPE_LEVEL_HIGH: 859 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 860 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 861 case IRQ_TYPE_LEVEL_LOW: 862 default: 863 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 864 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 865 } 866 } 867 868 int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) 869 { 870 struct mpic *mpic = mpic_from_irq_data(d); 871 unsigned int src = irqd_to_hwirq(d); 872 unsigned int vecpri, vold, vnew; 873 874 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", 875 mpic, d->irq, src, flow_type); 876 877 if (src >= mpic->num_sources) 878 return -EINVAL; 879 880 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 881 882 /* We don't support "none" type */ 883 if (flow_type == IRQ_TYPE_NONE) 884 flow_type = IRQ_TYPE_DEFAULT; 885 886 /* Default: read HW settings */ 887 if (flow_type == IRQ_TYPE_DEFAULT) { 888 int vold_ps; 889 890 vold_ps = vold & (MPIC_INFO(VECPRI_POLARITY_MASK) | 891 MPIC_INFO(VECPRI_SENSE_MASK)); 892 893 if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) | 894 MPIC_INFO(VECPRI_POLARITY_POSITIVE))) 895 flow_type = IRQ_TYPE_EDGE_RISING; 896 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) | 897 MPIC_INFO(VECPRI_POLARITY_NEGATIVE))) 898 flow_type = IRQ_TYPE_EDGE_FALLING; 899 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) | 900 MPIC_INFO(VECPRI_POLARITY_POSITIVE))) 901 flow_type = IRQ_TYPE_LEVEL_HIGH; 902 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) | 903 MPIC_INFO(VECPRI_POLARITY_NEGATIVE))) 904 flow_type = IRQ_TYPE_LEVEL_LOW; 905 else 906 WARN_ONCE(1, "mpic: unknown IRQ type %d\n", vold); 907 } 908 909 /* Apply to irq desc */ 910 irqd_set_trigger_type(d, flow_type); 911 912 /* Apply to HW */ 913 if (mpic_is_ht_interrupt(mpic, src)) 914 vecpri = MPIC_VECPRI_POLARITY_POSITIVE | 915 MPIC_VECPRI_SENSE_EDGE; 916 else 917 vecpri = mpic_type_to_vecpri(mpic, flow_type); 918 919 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | 920 MPIC_INFO(VECPRI_SENSE_MASK)); 921 vnew |= vecpri; 922 if (vold != vnew) 923 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); 924 925 return IRQ_SET_MASK_OK_NOCOPY; 926 } 927 928 static int mpic_irq_set_wake(struct irq_data *d, unsigned int on) 929 { 930 struct irq_desc *desc = container_of(d, struct irq_desc, irq_data); 931 struct mpic *mpic = mpic_from_irq_data(d); 932 933 if (!(mpic->flags & MPIC_FSL)) 934 return -ENXIO; 935 936 if (on) 937 desc->action->flags |= IRQF_NO_SUSPEND; 938 else 939 desc->action->flags &= ~IRQF_NO_SUSPEND; 940 941 return 0; 942 } 943 944 void mpic_set_vector(unsigned int virq, unsigned int vector) 945 { 946 struct mpic *mpic = mpic_from_irq(virq); 947 unsigned int src = virq_to_hw(virq); 948 unsigned int vecpri; 949 950 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", 951 mpic, virq, src, vector); 952 953 if (src >= mpic->num_sources) 954 return; 955 956 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 957 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK); 958 vecpri |= vector; 959 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 960 } 961 962 static void mpic_set_destination(unsigned int virq, unsigned int cpuid) 963 { 964 struct mpic *mpic = mpic_from_irq(virq); 965 unsigned int src = virq_to_hw(virq); 966 967 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n", 968 mpic, virq, src, cpuid); 969 970 if (src >= mpic->num_sources) 971 return; 972 973 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); 974 } 975 976 static struct irq_chip mpic_irq_chip = { 977 .irq_mask = mpic_mask_irq, 978 .irq_unmask = mpic_unmask_irq, 979 .irq_eoi = mpic_end_irq, 980 .irq_set_type = mpic_set_irq_type, 981 .irq_set_wake = mpic_irq_set_wake, 982 }; 983 984 #ifdef CONFIG_SMP 985 static struct irq_chip mpic_ipi_chip = { 986 .irq_mask = mpic_mask_ipi, 987 .irq_unmask = mpic_unmask_ipi, 988 .irq_eoi = mpic_end_ipi, 989 }; 990 #endif /* CONFIG_SMP */ 991 992 static struct irq_chip mpic_tm_chip = { 993 .irq_mask = mpic_mask_tm, 994 .irq_unmask = mpic_unmask_tm, 995 .irq_eoi = mpic_end_irq, 996 .irq_set_wake = mpic_irq_set_wake, 997 }; 998 999 #ifdef CONFIG_MPIC_U3_HT_IRQS 1000 static struct irq_chip mpic_irq_ht_chip = { 1001 .irq_startup = mpic_startup_ht_irq, 1002 .irq_shutdown = mpic_shutdown_ht_irq, 1003 .irq_mask = mpic_mask_irq, 1004 .irq_unmask = mpic_unmask_ht_irq, 1005 .irq_eoi = mpic_end_ht_irq, 1006 .irq_set_type = mpic_set_irq_type, 1007 }; 1008 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 1009 1010 1011 static int mpic_host_match(struct irq_domain *h, struct device_node *node) 1012 { 1013 /* Exact match, unless mpic node is NULL */ 1014 return h->of_node == NULL || h->of_node == node; 1015 } 1016 1017 static int mpic_host_map(struct irq_domain *h, unsigned int virq, 1018 irq_hw_number_t hw) 1019 { 1020 struct mpic *mpic = h->host_data; 1021 struct irq_chip *chip; 1022 1023 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); 1024 1025 if (hw == mpic->spurious_vec) 1026 return -EINVAL; 1027 if (mpic->protected && test_bit(hw, mpic->protected)) { 1028 pr_warning("mpic: Mapping of source 0x%x failed, " 1029 "source protected by firmware !\n",\ 1030 (unsigned int)hw); 1031 return -EPERM; 1032 } 1033 1034 #ifdef CONFIG_SMP 1035 else if (hw >= mpic->ipi_vecs[0]) { 1036 WARN_ON(mpic->flags & MPIC_SECONDARY); 1037 1038 DBG("mpic: mapping as IPI\n"); 1039 irq_set_chip_data(virq, mpic); 1040 irq_set_chip_and_handler(virq, &mpic->hc_ipi, 1041 handle_percpu_irq); 1042 return 0; 1043 } 1044 #endif /* CONFIG_SMP */ 1045 1046 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) { 1047 WARN_ON(mpic->flags & MPIC_SECONDARY); 1048 1049 DBG("mpic: mapping as timer\n"); 1050 irq_set_chip_data(virq, mpic); 1051 irq_set_chip_and_handler(virq, &mpic->hc_tm, 1052 handle_fasteoi_irq); 1053 return 0; 1054 } 1055 1056 if (mpic_map_error_int(mpic, virq, hw)) 1057 return 0; 1058 1059 if (hw >= mpic->num_sources) { 1060 pr_warning("mpic: Mapping of source 0x%x failed, " 1061 "source out of range !\n",\ 1062 (unsigned int)hw); 1063 return -EINVAL; 1064 } 1065 1066 mpic_msi_reserve_hwirq(mpic, hw); 1067 1068 /* Default chip */ 1069 chip = &mpic->hc_irq; 1070 1071 #ifdef CONFIG_MPIC_U3_HT_IRQS 1072 /* Check for HT interrupts, override vecpri */ 1073 if (mpic_is_ht_interrupt(mpic, hw)) 1074 chip = &mpic->hc_ht_irq; 1075 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 1076 1077 DBG("mpic: mapping to irq chip @%p\n", chip); 1078 1079 irq_set_chip_data(virq, mpic); 1080 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq); 1081 1082 /* Set default irq type */ 1083 irq_set_irq_type(virq, IRQ_TYPE_DEFAULT); 1084 1085 /* If the MPIC was reset, then all vectors have already been 1086 * initialized. Otherwise, a per source lazy initialization 1087 * is done here. 1088 */ 1089 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) { 1090 int cpu; 1091 1092 preempt_disable(); 1093 cpu = mpic_processor_id(mpic); 1094 preempt_enable(); 1095 1096 mpic_set_vector(virq, hw); 1097 mpic_set_destination(virq, cpu); 1098 mpic_irq_set_priority(virq, 8); 1099 } 1100 1101 return 0; 1102 } 1103 1104 static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct, 1105 const u32 *intspec, unsigned int intsize, 1106 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 1107 1108 { 1109 struct mpic *mpic = h->host_data; 1110 static unsigned char map_mpic_senses[4] = { 1111 IRQ_TYPE_EDGE_RISING, 1112 IRQ_TYPE_LEVEL_LOW, 1113 IRQ_TYPE_LEVEL_HIGH, 1114 IRQ_TYPE_EDGE_FALLING, 1115 }; 1116 1117 *out_hwirq = intspec[0]; 1118 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) { 1119 /* 1120 * Freescale MPIC with extended intspec: 1121 * First two cells are as usual. Third specifies 1122 * an "interrupt type". Fourth is type-specific data. 1123 * 1124 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt 1125 */ 1126 switch (intspec[2]) { 1127 case 0: 1128 break; 1129 case 1: 1130 if (!(mpic->flags & MPIC_FSL_HAS_EIMR)) 1131 break; 1132 1133 if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs)) 1134 return -EINVAL; 1135 1136 *out_hwirq = mpic->err_int_vecs[intspec[3]]; 1137 1138 break; 1139 case 2: 1140 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs)) 1141 return -EINVAL; 1142 1143 *out_hwirq = mpic->ipi_vecs[intspec[0]]; 1144 break; 1145 case 3: 1146 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs)) 1147 return -EINVAL; 1148 1149 *out_hwirq = mpic->timer_vecs[intspec[0]]; 1150 break; 1151 default: 1152 pr_debug("%s: unknown irq type %u\n", 1153 __func__, intspec[2]); 1154 return -EINVAL; 1155 } 1156 1157 *out_flags = map_mpic_senses[intspec[1] & 3]; 1158 } else if (intsize > 1) { 1159 u32 mask = 0x3; 1160 1161 /* Apple invented a new race of encoding on machines with 1162 * an HT APIC. They encode, among others, the index within 1163 * the HT APIC. We don't care about it here since thankfully, 1164 * it appears that they have the APIC already properly 1165 * configured, and thus our current fixup code that reads the 1166 * APIC config works fine. However, we still need to mask out 1167 * bits in the specifier to make sure we only get bit 0 which 1168 * is the level/edge bit (the only sense bit exposed by Apple), 1169 * as their bit 1 means something else. 1170 */ 1171 if (machine_is(powermac)) 1172 mask = 0x1; 1173 *out_flags = map_mpic_senses[intspec[1] & mask]; 1174 } else 1175 *out_flags = IRQ_TYPE_NONE; 1176 1177 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", 1178 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); 1179 1180 return 0; 1181 } 1182 1183 /* IRQ handler for a secondary MPIC cascaded from another IRQ controller */ 1184 static void mpic_cascade(unsigned int irq, struct irq_desc *desc) 1185 { 1186 struct irq_chip *chip = irq_desc_get_chip(desc); 1187 struct mpic *mpic = irq_desc_get_handler_data(desc); 1188 unsigned int virq; 1189 1190 BUG_ON(!(mpic->flags & MPIC_SECONDARY)); 1191 1192 virq = mpic_get_one_irq(mpic); 1193 if (virq) 1194 generic_handle_irq(virq); 1195 1196 chip->irq_eoi(&desc->irq_data); 1197 } 1198 1199 static struct irq_domain_ops mpic_host_ops = { 1200 .match = mpic_host_match, 1201 .map = mpic_host_map, 1202 .xlate = mpic_host_xlate, 1203 }; 1204 1205 static u32 fsl_mpic_get_version(struct mpic *mpic) 1206 { 1207 u32 brr1; 1208 1209 if (!(mpic->flags & MPIC_FSL)) 1210 return 0; 1211 1212 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs, 1213 MPIC_FSL_BRR1); 1214 1215 return brr1 & MPIC_FSL_BRR1_VER; 1216 } 1217 1218 /* 1219 * Exported functions 1220 */ 1221 1222 u32 fsl_mpic_primary_get_version(void) 1223 { 1224 struct mpic *mpic = mpic_primary; 1225 1226 if (mpic) 1227 return fsl_mpic_get_version(mpic); 1228 1229 return 0; 1230 } 1231 1232 struct mpic * __init mpic_alloc(struct device_node *node, 1233 phys_addr_t phys_addr, 1234 unsigned int flags, 1235 unsigned int isu_size, 1236 unsigned int irq_count, 1237 const char *name) 1238 { 1239 int i, psize, intvec_top; 1240 struct mpic *mpic; 1241 u32 greg_feature; 1242 const char *vers; 1243 const u32 *psrc; 1244 u32 last_irq; 1245 u32 fsl_version = 0; 1246 1247 /* Default MPIC search parameters */ 1248 static const struct of_device_id __initconst mpic_device_id[] = { 1249 { .type = "open-pic", }, 1250 { .compatible = "open-pic", }, 1251 {}, 1252 }; 1253 1254 /* 1255 * If we were not passed a device-tree node, then perform the default 1256 * search for standardized a standardized OpenPIC. 1257 */ 1258 if (node) { 1259 node = of_node_get(node); 1260 } else { 1261 node = of_find_matching_node(NULL, mpic_device_id); 1262 if (!node) 1263 return NULL; 1264 } 1265 1266 /* Pick the physical address from the device tree if unspecified */ 1267 if (!phys_addr) { 1268 /* Check if it is DCR-based */ 1269 if (of_get_property(node, "dcr-reg", NULL)) { 1270 flags |= MPIC_USES_DCR; 1271 } else { 1272 struct resource r; 1273 if (of_address_to_resource(node, 0, &r)) 1274 goto err_of_node_put; 1275 phys_addr = r.start; 1276 } 1277 } 1278 1279 /* Read extra device-tree properties into the flags variable */ 1280 if (of_get_property(node, "big-endian", NULL)) 1281 flags |= MPIC_BIG_ENDIAN; 1282 if (of_get_property(node, "pic-no-reset", NULL)) 1283 flags |= MPIC_NO_RESET; 1284 if (of_get_property(node, "single-cpu-affinity", NULL)) 1285 flags |= MPIC_SINGLE_DEST_CPU; 1286 if (of_device_is_compatible(node, "fsl,mpic")) 1287 flags |= MPIC_FSL | MPIC_LARGE_VECTORS; 1288 1289 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); 1290 if (mpic == NULL) 1291 goto err_of_node_put; 1292 1293 mpic->name = name; 1294 mpic->node = node; 1295 mpic->paddr = phys_addr; 1296 mpic->flags = flags; 1297 1298 mpic->hc_irq = mpic_irq_chip; 1299 mpic->hc_irq.name = name; 1300 if (!(mpic->flags & MPIC_SECONDARY)) 1301 mpic->hc_irq.irq_set_affinity = mpic_set_affinity; 1302 #ifdef CONFIG_MPIC_U3_HT_IRQS 1303 mpic->hc_ht_irq = mpic_irq_ht_chip; 1304 mpic->hc_ht_irq.name = name; 1305 if (!(mpic->flags & MPIC_SECONDARY)) 1306 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity; 1307 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 1308 1309 #ifdef CONFIG_SMP 1310 mpic->hc_ipi = mpic_ipi_chip; 1311 mpic->hc_ipi.name = name; 1312 #endif /* CONFIG_SMP */ 1313 1314 mpic->hc_tm = mpic_tm_chip; 1315 mpic->hc_tm.name = name; 1316 1317 mpic->num_sources = 0; /* so far */ 1318 1319 if (mpic->flags & MPIC_LARGE_VECTORS) 1320 intvec_top = 2047; 1321 else 1322 intvec_top = 255; 1323 1324 mpic->timer_vecs[0] = intvec_top - 12; 1325 mpic->timer_vecs[1] = intvec_top - 11; 1326 mpic->timer_vecs[2] = intvec_top - 10; 1327 mpic->timer_vecs[3] = intvec_top - 9; 1328 mpic->timer_vecs[4] = intvec_top - 8; 1329 mpic->timer_vecs[5] = intvec_top - 7; 1330 mpic->timer_vecs[6] = intvec_top - 6; 1331 mpic->timer_vecs[7] = intvec_top - 5; 1332 mpic->ipi_vecs[0] = intvec_top - 4; 1333 mpic->ipi_vecs[1] = intvec_top - 3; 1334 mpic->ipi_vecs[2] = intvec_top - 2; 1335 mpic->ipi_vecs[3] = intvec_top - 1; 1336 mpic->spurious_vec = intvec_top; 1337 1338 /* Look for protected sources */ 1339 psrc = of_get_property(mpic->node, "protected-sources", &psize); 1340 if (psrc) { 1341 /* Allocate a bitmap with one bit per interrupt */ 1342 unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1); 1343 mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL); 1344 BUG_ON(mpic->protected == NULL); 1345 for (i = 0; i < psize/sizeof(u32); i++) { 1346 if (psrc[i] > intvec_top) 1347 continue; 1348 __set_bit(psrc[i], mpic->protected); 1349 } 1350 } 1351 1352 #ifdef CONFIG_MPIC_WEIRD 1353 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)]; 1354 #endif 1355 1356 /* default register type */ 1357 if (mpic->flags & MPIC_BIG_ENDIAN) 1358 mpic->reg_type = mpic_access_mmio_be; 1359 else 1360 mpic->reg_type = mpic_access_mmio_le; 1361 1362 /* 1363 * An MPIC with a "dcr-reg" property must be accessed that way, but 1364 * only if the kernel includes DCR support. 1365 */ 1366 #ifdef CONFIG_PPC_DCR 1367 if (mpic->flags & MPIC_USES_DCR) 1368 mpic->reg_type = mpic_access_dcr; 1369 #else 1370 BUG_ON(mpic->flags & MPIC_USES_DCR); 1371 #endif 1372 1373 /* Map the global registers */ 1374 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); 1375 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); 1376 1377 if (mpic->flags & MPIC_FSL) { 1378 int ret; 1379 1380 /* 1381 * Yes, Freescale really did put global registers in the 1382 * magic per-cpu area -- and they don't even show up in the 1383 * non-magic per-cpu copies that this driver normally uses. 1384 */ 1385 mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs, 1386 MPIC_CPU_THISBASE, 0x1000); 1387 1388 fsl_version = fsl_mpic_get_version(mpic); 1389 1390 /* Error interrupt mask register (EIMR) is required for 1391 * handling individual device error interrupts. EIMR 1392 * was added in MPIC version 4.1. 1393 * 1394 * Over here we reserve vector number space for error 1395 * interrupt vectors. This space is stolen from the 1396 * global vector number space, as in case of ipis 1397 * and timer interrupts. 1398 * 1399 * Available vector space = intvec_top - 12, where 12 1400 * is the number of vectors which have been consumed by 1401 * ipis and timer interrupts. 1402 */ 1403 if (fsl_version >= 0x401) { 1404 ret = mpic_setup_error_int(mpic, intvec_top - 12); 1405 if (ret) 1406 return NULL; 1407 } 1408 1409 } 1410 1411 /* 1412 * EPR is only available starting with v4.0. To support 1413 * platforms that don't know the MPIC version at compile-time, 1414 * such as qemu-e500, turn off coreint if this MPIC doesn't 1415 * support it. Note that we never enable it if it wasn't 1416 * requested in the first place. 1417 * 1418 * This is done outside the MPIC_FSL check, so that we 1419 * also disable coreint if the MPIC node doesn't have 1420 * an "fsl,mpic" compatible at all. This will be the case 1421 * with device trees generated by older versions of QEMU. 1422 * fsl_version will be zero if MPIC_FSL is not set. 1423 */ 1424 if (fsl_version < 0x400 && (flags & MPIC_ENABLE_COREINT)) { 1425 WARN_ON(ppc_md.get_irq != mpic_get_coreint_irq); 1426 ppc_md.get_irq = mpic_get_irq; 1427 } 1428 1429 /* Reset */ 1430 1431 /* When using a device-node, reset requests are only honored if the MPIC 1432 * is allowed to reset. 1433 */ 1434 if (!(mpic->flags & MPIC_NO_RESET)) { 1435 printk(KERN_DEBUG "mpic: Resetting\n"); 1436 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1437 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1438 | MPIC_GREG_GCONF_RESET); 1439 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1440 & MPIC_GREG_GCONF_RESET) 1441 mb(); 1442 } 1443 1444 /* CoreInt */ 1445 if (mpic->flags & MPIC_ENABLE_COREINT) 1446 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1447 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1448 | MPIC_GREG_GCONF_COREINT); 1449 1450 if (mpic->flags & MPIC_ENABLE_MCK) 1451 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1452 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1453 | MPIC_GREG_GCONF_MCK); 1454 1455 /* 1456 * The MPIC driver will crash if there are more cores than we 1457 * can initialize, so we may as well catch that problem here. 1458 */ 1459 BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS); 1460 1461 /* Map the per-CPU registers */ 1462 for_each_possible_cpu(i) { 1463 unsigned int cpu = get_hard_smp_processor_id(i); 1464 1465 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu], 1466 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE), 1467 0x1000); 1468 } 1469 1470 /* 1471 * Read feature register. For non-ISU MPICs, num sources as well. On 1472 * ISU MPICs, sources are counted as ISUs are added 1473 */ 1474 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); 1475 1476 /* 1477 * By default, the last source number comes from the MPIC, but the 1478 * device-tree and board support code can override it on buggy hw. 1479 * If we get passed an isu_size (multi-isu MPIC) then we use that 1480 * as a default instead of the value read from the HW. 1481 */ 1482 last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) 1483 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT; 1484 if (isu_size) 1485 last_irq = isu_size * MPIC_MAX_ISU - 1; 1486 of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq); 1487 if (irq_count) 1488 last_irq = irq_count - 1; 1489 1490 /* Initialize main ISU if none provided */ 1491 if (!isu_size) { 1492 isu_size = last_irq + 1; 1493 mpic->num_sources = isu_size; 1494 mpic_map(mpic, mpic->paddr, &mpic->isus[0], 1495 MPIC_INFO(IRQ_BASE), 1496 MPIC_INFO(IRQ_STRIDE) * isu_size); 1497 } 1498 1499 mpic->isu_size = isu_size; 1500 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 1501 mpic->isu_mask = (1 << mpic->isu_shift) - 1; 1502 1503 mpic->irqhost = irq_domain_add_linear(mpic->node, 1504 intvec_top, 1505 &mpic_host_ops, mpic); 1506 1507 /* 1508 * FIXME: The code leaks the MPIC object and mappings here; this 1509 * is very unlikely to fail but it ought to be fixed anyways. 1510 */ 1511 if (mpic->irqhost == NULL) 1512 return NULL; 1513 1514 /* Display version */ 1515 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) { 1516 case 1: 1517 vers = "1.0"; 1518 break; 1519 case 2: 1520 vers = "1.2"; 1521 break; 1522 case 3: 1523 vers = "1.3"; 1524 break; 1525 default: 1526 vers = "<unknown>"; 1527 break; 1528 } 1529 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," 1530 " max %d CPUs\n", 1531 name, vers, (unsigned long long)mpic->paddr, num_possible_cpus()); 1532 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", 1533 mpic->isu_size, mpic->isu_shift, mpic->isu_mask); 1534 1535 mpic->next = mpics; 1536 mpics = mpic; 1537 1538 if (!(mpic->flags & MPIC_SECONDARY)) { 1539 mpic_primary = mpic; 1540 irq_set_default_host(mpic->irqhost); 1541 } 1542 1543 return mpic; 1544 1545 err_of_node_put: 1546 of_node_put(node); 1547 return NULL; 1548 } 1549 1550 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, 1551 phys_addr_t paddr) 1552 { 1553 unsigned int isu_first = isu_num * mpic->isu_size; 1554 1555 BUG_ON(isu_num >= MPIC_MAX_ISU); 1556 1557 mpic_map(mpic, 1558 paddr, &mpic->isus[isu_num], 0, 1559 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1560 1561 if ((isu_first + mpic->isu_size) > mpic->num_sources) 1562 mpic->num_sources = isu_first + mpic->isu_size; 1563 } 1564 1565 void __init mpic_init(struct mpic *mpic) 1566 { 1567 int i, cpu; 1568 int num_timers = 4; 1569 1570 BUG_ON(mpic->num_sources == 0); 1571 1572 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); 1573 1574 /* Set current processor priority to max */ 1575 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1576 1577 if (mpic->flags & MPIC_FSL) { 1578 u32 version = fsl_mpic_get_version(mpic); 1579 1580 /* 1581 * Timer group B is present at the latest in MPIC 3.1 (e.g. 1582 * mpc8536). It is not present in MPIC 2.0 (e.g. mpc8544). 1583 * I don't know about the status of intermediate versions (or 1584 * whether they even exist). 1585 */ 1586 if (version >= 0x0301) 1587 num_timers = 8; 1588 } 1589 1590 /* Initialize timers to our reserved vectors and mask them for now */ 1591 for (i = 0; i < num_timers; i++) { 1592 unsigned int offset = mpic_tm_offset(mpic, i); 1593 1594 mpic_write(mpic->tmregs, 1595 offset + MPIC_INFO(TIMER_DESTINATION), 1596 1 << hard_smp_processor_id()); 1597 mpic_write(mpic->tmregs, 1598 offset + MPIC_INFO(TIMER_VECTOR_PRI), 1599 MPIC_VECPRI_MASK | 1600 (9 << MPIC_VECPRI_PRIORITY_SHIFT) | 1601 (mpic->timer_vecs[0] + i)); 1602 } 1603 1604 /* Initialize IPIs to our reserved vectors and mark them disabled for now */ 1605 mpic_test_broken_ipi(mpic); 1606 for (i = 0; i < 4; i++) { 1607 mpic_ipi_write(i, 1608 MPIC_VECPRI_MASK | 1609 (10 << MPIC_VECPRI_PRIORITY_SHIFT) | 1610 (mpic->ipi_vecs[0] + i)); 1611 } 1612 1613 /* Do the HT PIC fixups on U3 broken mpic */ 1614 DBG("MPIC flags: %x\n", mpic->flags); 1615 if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) { 1616 mpic_scan_ht_pics(mpic); 1617 mpic_u3msi_init(mpic); 1618 } 1619 1620 mpic_pasemi_msi_init(mpic); 1621 1622 cpu = mpic_processor_id(mpic); 1623 1624 if (!(mpic->flags & MPIC_NO_RESET)) { 1625 for (i = 0; i < mpic->num_sources; i++) { 1626 /* start with vector = source number, and masked */ 1627 u32 vecpri = MPIC_VECPRI_MASK | i | 1628 (8 << MPIC_VECPRI_PRIORITY_SHIFT); 1629 1630 /* check if protected */ 1631 if (mpic->protected && test_bit(i, mpic->protected)) 1632 continue; 1633 /* init hw */ 1634 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 1635 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); 1636 } 1637 } 1638 1639 /* Init spurious vector */ 1640 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); 1641 1642 /* Disable 8259 passthrough, if supported */ 1643 if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) 1644 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1645 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1646 | MPIC_GREG_GCONF_8259_PTHROU_DIS); 1647 1648 if (mpic->flags & MPIC_NO_BIAS) 1649 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1650 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1651 | MPIC_GREG_GCONF_NO_BIAS); 1652 1653 /* Set current processor priority to 0 */ 1654 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 1655 1656 #ifdef CONFIG_PM 1657 /* allocate memory to save mpic state */ 1658 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data), 1659 GFP_KERNEL); 1660 BUG_ON(mpic->save_data == NULL); 1661 #endif 1662 1663 /* Check if this MPIC is chained from a parent interrupt controller */ 1664 if (mpic->flags & MPIC_SECONDARY) { 1665 int virq = irq_of_parse_and_map(mpic->node, 0); 1666 if (virq != NO_IRQ) { 1667 printk(KERN_INFO "%s: hooking up to IRQ %d\n", 1668 mpic->node->full_name, virq); 1669 irq_set_handler_data(virq, mpic); 1670 irq_set_chained_handler(virq, &mpic_cascade); 1671 } 1672 } 1673 1674 /* FSL mpic error interrupt intialization */ 1675 if (mpic->flags & MPIC_FSL_HAS_EIMR) 1676 mpic_err_int_init(mpic, MPIC_FSL_ERR_INT); 1677 } 1678 1679 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) 1680 { 1681 u32 v; 1682 1683 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1684 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; 1685 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); 1686 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1687 } 1688 1689 void __init mpic_set_serial_int(struct mpic *mpic, int enable) 1690 { 1691 unsigned long flags; 1692 u32 v; 1693 1694 raw_spin_lock_irqsave(&mpic_lock, flags); 1695 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1696 if (enable) 1697 v |= MPIC_GREG_GLOBAL_CONF_1_SIE; 1698 else 1699 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; 1700 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1701 raw_spin_unlock_irqrestore(&mpic_lock, flags); 1702 } 1703 1704 void mpic_irq_set_priority(unsigned int irq, unsigned int pri) 1705 { 1706 struct mpic *mpic = mpic_find(irq); 1707 unsigned int src = virq_to_hw(irq); 1708 unsigned long flags; 1709 u32 reg; 1710 1711 if (!mpic) 1712 return; 1713 1714 raw_spin_lock_irqsave(&mpic_lock, flags); 1715 if (mpic_is_ipi(mpic, src)) { 1716 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & 1717 ~MPIC_VECPRI_PRIORITY_MASK; 1718 mpic_ipi_write(src - mpic->ipi_vecs[0], 1719 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1720 } else if (mpic_is_tm(mpic, src)) { 1721 reg = mpic_tm_read(src - mpic->timer_vecs[0]) & 1722 ~MPIC_VECPRI_PRIORITY_MASK; 1723 mpic_tm_write(src - mpic->timer_vecs[0], 1724 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1725 } else { 1726 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) 1727 & ~MPIC_VECPRI_PRIORITY_MASK; 1728 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 1729 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1730 } 1731 raw_spin_unlock_irqrestore(&mpic_lock, flags); 1732 } 1733 1734 void mpic_setup_this_cpu(void) 1735 { 1736 #ifdef CONFIG_SMP 1737 struct mpic *mpic = mpic_primary; 1738 unsigned long flags; 1739 u32 msk = 1 << hard_smp_processor_id(); 1740 unsigned int i; 1741 1742 BUG_ON(mpic == NULL); 1743 1744 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1745 1746 raw_spin_lock_irqsave(&mpic_lock, flags); 1747 1748 /* let the mpic know we want intrs. default affinity is 0xffffffff 1749 * until changed via /proc. That's how it's done on x86. If we want 1750 * it differently, then we should make sure we also change the default 1751 * values of irq_desc[].affinity in irq.c. 1752 */ 1753 if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) { 1754 for (i = 0; i < mpic->num_sources ; i++) 1755 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1756 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); 1757 } 1758 1759 /* Set current processor priority to 0 */ 1760 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 1761 1762 raw_spin_unlock_irqrestore(&mpic_lock, flags); 1763 #endif /* CONFIG_SMP */ 1764 } 1765 1766 int mpic_cpu_get_priority(void) 1767 { 1768 struct mpic *mpic = mpic_primary; 1769 1770 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); 1771 } 1772 1773 void mpic_cpu_set_priority(int prio) 1774 { 1775 struct mpic *mpic = mpic_primary; 1776 1777 prio &= MPIC_CPU_TASKPRI_MASK; 1778 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); 1779 } 1780 1781 void mpic_teardown_this_cpu(int secondary) 1782 { 1783 struct mpic *mpic = mpic_primary; 1784 unsigned long flags; 1785 u32 msk = 1 << hard_smp_processor_id(); 1786 unsigned int i; 1787 1788 BUG_ON(mpic == NULL); 1789 1790 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1791 raw_spin_lock_irqsave(&mpic_lock, flags); 1792 1793 /* let the mpic know we don't want intrs. */ 1794 for (i = 0; i < mpic->num_sources ; i++) 1795 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1796 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); 1797 1798 /* Set current processor priority to max */ 1799 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1800 /* We need to EOI the IPI since not all platforms reset the MPIC 1801 * on boot and new interrupts wouldn't get delivered otherwise. 1802 */ 1803 mpic_eoi(mpic); 1804 1805 raw_spin_unlock_irqrestore(&mpic_lock, flags); 1806 } 1807 1808 1809 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) 1810 { 1811 u32 src; 1812 1813 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); 1814 #ifdef DEBUG_LOW 1815 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); 1816 #endif 1817 if (unlikely(src == mpic->spurious_vec)) { 1818 if (mpic->flags & MPIC_SPV_EOI) 1819 mpic_eoi(mpic); 1820 return NO_IRQ; 1821 } 1822 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { 1823 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n", 1824 mpic->name, (int)src); 1825 mpic_eoi(mpic); 1826 return NO_IRQ; 1827 } 1828 1829 return irq_linear_revmap(mpic->irqhost, src); 1830 } 1831 1832 unsigned int mpic_get_one_irq(struct mpic *mpic) 1833 { 1834 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); 1835 } 1836 1837 unsigned int mpic_get_irq(void) 1838 { 1839 struct mpic *mpic = mpic_primary; 1840 1841 BUG_ON(mpic == NULL); 1842 1843 return mpic_get_one_irq(mpic); 1844 } 1845 1846 unsigned int mpic_get_coreint_irq(void) 1847 { 1848 #ifdef CONFIG_BOOKE 1849 struct mpic *mpic = mpic_primary; 1850 u32 src; 1851 1852 BUG_ON(mpic == NULL); 1853 1854 src = mfspr(SPRN_EPR); 1855 1856 if (unlikely(src == mpic->spurious_vec)) { 1857 if (mpic->flags & MPIC_SPV_EOI) 1858 mpic_eoi(mpic); 1859 return NO_IRQ; 1860 } 1861 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { 1862 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n", 1863 mpic->name, (int)src); 1864 return NO_IRQ; 1865 } 1866 1867 return irq_linear_revmap(mpic->irqhost, src); 1868 #else 1869 return NO_IRQ; 1870 #endif 1871 } 1872 1873 unsigned int mpic_get_mcirq(void) 1874 { 1875 struct mpic *mpic = mpic_primary; 1876 1877 BUG_ON(mpic == NULL); 1878 1879 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); 1880 } 1881 1882 #ifdef CONFIG_SMP 1883 void mpic_request_ipis(void) 1884 { 1885 struct mpic *mpic = mpic_primary; 1886 int i; 1887 BUG_ON(mpic == NULL); 1888 1889 printk(KERN_INFO "mpic: requesting IPIs...\n"); 1890 1891 for (i = 0; i < 4; i++) { 1892 unsigned int vipi = irq_create_mapping(mpic->irqhost, 1893 mpic->ipi_vecs[0] + i); 1894 if (vipi == NO_IRQ) { 1895 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]); 1896 continue; 1897 } 1898 smp_request_message_ipi(vipi, i); 1899 } 1900 } 1901 1902 void smp_mpic_message_pass(int cpu, int msg) 1903 { 1904 struct mpic *mpic = mpic_primary; 1905 u32 physmask; 1906 1907 BUG_ON(mpic == NULL); 1908 1909 /* make sure we're sending something that translates to an IPI */ 1910 if ((unsigned int)msg > 3) { 1911 printk("SMP %d: smp_message_pass: unknown msg %d\n", 1912 smp_processor_id(), msg); 1913 return; 1914 } 1915 1916 #ifdef DEBUG_IPI 1917 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg); 1918 #endif 1919 1920 physmask = 1 << get_hard_smp_processor_id(cpu); 1921 1922 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + 1923 msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask); 1924 } 1925 1926 int __init smp_mpic_probe(void) 1927 { 1928 int nr_cpus; 1929 1930 DBG("smp_mpic_probe()...\n"); 1931 1932 nr_cpus = cpumask_weight(cpu_possible_mask); 1933 1934 DBG("nr_cpus: %d\n", nr_cpus); 1935 1936 if (nr_cpus > 1) 1937 mpic_request_ipis(); 1938 1939 return nr_cpus; 1940 } 1941 1942 void smp_mpic_setup_cpu(int cpu) 1943 { 1944 mpic_setup_this_cpu(); 1945 } 1946 1947 void mpic_reset_core(int cpu) 1948 { 1949 struct mpic *mpic = mpic_primary; 1950 u32 pir; 1951 int cpuid = get_hard_smp_processor_id(cpu); 1952 int i; 1953 1954 /* Set target bit for core reset */ 1955 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); 1956 pir |= (1 << cpuid); 1957 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); 1958 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); 1959 1960 /* Restore target bit after reset complete */ 1961 pir &= ~(1 << cpuid); 1962 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); 1963 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); 1964 1965 /* Perform 15 EOI on each reset core to clear pending interrupts. 1966 * This is required for FSL CoreNet based devices */ 1967 if (mpic->flags & MPIC_FSL) { 1968 for (i = 0; i < 15; i++) { 1969 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid], 1970 MPIC_CPU_EOI, 0); 1971 } 1972 } 1973 } 1974 #endif /* CONFIG_SMP */ 1975 1976 #ifdef CONFIG_PM 1977 static void mpic_suspend_one(struct mpic *mpic) 1978 { 1979 int i; 1980 1981 for (i = 0; i < mpic->num_sources; i++) { 1982 mpic->save_data[i].vecprio = 1983 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); 1984 mpic->save_data[i].dest = 1985 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); 1986 } 1987 } 1988 1989 static int mpic_suspend(void) 1990 { 1991 struct mpic *mpic = mpics; 1992 1993 while (mpic) { 1994 mpic_suspend_one(mpic); 1995 mpic = mpic->next; 1996 } 1997 1998 return 0; 1999 } 2000 2001 static void mpic_resume_one(struct mpic *mpic) 2002 { 2003 int i; 2004 2005 for (i = 0; i < mpic->num_sources; i++) { 2006 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), 2007 mpic->save_data[i].vecprio); 2008 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 2009 mpic->save_data[i].dest); 2010 2011 #ifdef CONFIG_MPIC_U3_HT_IRQS 2012 if (mpic->fixups) { 2013 struct mpic_irq_fixup *fixup = &mpic->fixups[i]; 2014 2015 if (fixup->base) { 2016 /* we use the lowest bit in an inverted meaning */ 2017 if ((mpic->save_data[i].fixup_data & 1) == 0) 2018 continue; 2019 2020 /* Enable and configure */ 2021 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 2022 2023 writel(mpic->save_data[i].fixup_data & ~1, 2024 fixup->base + 4); 2025 } 2026 } 2027 #endif 2028 } /* end for loop */ 2029 } 2030 2031 static void mpic_resume(void) 2032 { 2033 struct mpic *mpic = mpics; 2034 2035 while (mpic) { 2036 mpic_resume_one(mpic); 2037 mpic = mpic->next; 2038 } 2039 } 2040 2041 static struct syscore_ops mpic_syscore_ops = { 2042 .resume = mpic_resume, 2043 .suspend = mpic_suspend, 2044 }; 2045 2046 static int mpic_init_sys(void) 2047 { 2048 register_syscore_ops(&mpic_syscore_ops); 2049 subsys_system_register(&mpic_subsys, NULL); 2050 2051 return 0; 2052 } 2053 2054 device_initcall(mpic_init_sys); 2055 #endif 2056