1 /* 2 * arch/powerpc/kernel/mpic.c 3 * 4 * Driver for interrupt controllers following the OpenPIC standard, the 5 * common implementation beeing IBM's MPIC. This driver also can deal 6 * with various broken implementations of this HW. 7 * 8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. 9 * Copyright 2010-2011 Freescale Semiconductor, Inc. 10 * 11 * This file is subject to the terms and conditions of the GNU General Public 12 * License. See the file COPYING in the main directory of this archive 13 * for more details. 14 */ 15 16 #undef DEBUG 17 #undef DEBUG_IPI 18 #undef DEBUG_IRQ 19 #undef DEBUG_LOW 20 21 #include <linux/types.h> 22 #include <linux/kernel.h> 23 #include <linux/init.h> 24 #include <linux/irq.h> 25 #include <linux/smp.h> 26 #include <linux/interrupt.h> 27 #include <linux/bootmem.h> 28 #include <linux/spinlock.h> 29 #include <linux/pci.h> 30 #include <linux/slab.h> 31 #include <linux/syscore_ops.h> 32 #include <linux/ratelimit.h> 33 34 #include <asm/ptrace.h> 35 #include <asm/signal.h> 36 #include <asm/io.h> 37 #include <asm/pgtable.h> 38 #include <asm/irq.h> 39 #include <asm/machdep.h> 40 #include <asm/mpic.h> 41 #include <asm/smp.h> 42 43 #include "mpic.h" 44 45 #ifdef DEBUG 46 #define DBG(fmt...) printk(fmt) 47 #else 48 #define DBG(fmt...) 49 #endif 50 51 static struct mpic *mpics; 52 static struct mpic *mpic_primary; 53 static DEFINE_RAW_SPINLOCK(mpic_lock); 54 55 #ifdef CONFIG_PPC32 /* XXX for now */ 56 #ifdef CONFIG_IRQ_ALL_CPUS 57 #define distribute_irqs (1) 58 #else 59 #define distribute_irqs (0) 60 #endif 61 #endif 62 63 #ifdef CONFIG_MPIC_WEIRD 64 static u32 mpic_infos[][MPIC_IDX_END] = { 65 [0] = { /* Original OpenPIC compatible MPIC */ 66 MPIC_GREG_BASE, 67 MPIC_GREG_FEATURE_0, 68 MPIC_GREG_GLOBAL_CONF_0, 69 MPIC_GREG_VENDOR_ID, 70 MPIC_GREG_IPI_VECTOR_PRI_0, 71 MPIC_GREG_IPI_STRIDE, 72 MPIC_GREG_SPURIOUS, 73 MPIC_GREG_TIMER_FREQ, 74 75 MPIC_TIMER_BASE, 76 MPIC_TIMER_STRIDE, 77 MPIC_TIMER_CURRENT_CNT, 78 MPIC_TIMER_BASE_CNT, 79 MPIC_TIMER_VECTOR_PRI, 80 MPIC_TIMER_DESTINATION, 81 82 MPIC_CPU_BASE, 83 MPIC_CPU_STRIDE, 84 MPIC_CPU_IPI_DISPATCH_0, 85 MPIC_CPU_IPI_DISPATCH_STRIDE, 86 MPIC_CPU_CURRENT_TASK_PRI, 87 MPIC_CPU_WHOAMI, 88 MPIC_CPU_INTACK, 89 MPIC_CPU_EOI, 90 MPIC_CPU_MCACK, 91 92 MPIC_IRQ_BASE, 93 MPIC_IRQ_STRIDE, 94 MPIC_IRQ_VECTOR_PRI, 95 MPIC_VECPRI_VECTOR_MASK, 96 MPIC_VECPRI_POLARITY_POSITIVE, 97 MPIC_VECPRI_POLARITY_NEGATIVE, 98 MPIC_VECPRI_SENSE_LEVEL, 99 MPIC_VECPRI_SENSE_EDGE, 100 MPIC_VECPRI_POLARITY_MASK, 101 MPIC_VECPRI_SENSE_MASK, 102 MPIC_IRQ_DESTINATION 103 }, 104 [1] = { /* Tsi108/109 PIC */ 105 TSI108_GREG_BASE, 106 TSI108_GREG_FEATURE_0, 107 TSI108_GREG_GLOBAL_CONF_0, 108 TSI108_GREG_VENDOR_ID, 109 TSI108_GREG_IPI_VECTOR_PRI_0, 110 TSI108_GREG_IPI_STRIDE, 111 TSI108_GREG_SPURIOUS, 112 TSI108_GREG_TIMER_FREQ, 113 114 TSI108_TIMER_BASE, 115 TSI108_TIMER_STRIDE, 116 TSI108_TIMER_CURRENT_CNT, 117 TSI108_TIMER_BASE_CNT, 118 TSI108_TIMER_VECTOR_PRI, 119 TSI108_TIMER_DESTINATION, 120 121 TSI108_CPU_BASE, 122 TSI108_CPU_STRIDE, 123 TSI108_CPU_IPI_DISPATCH_0, 124 TSI108_CPU_IPI_DISPATCH_STRIDE, 125 TSI108_CPU_CURRENT_TASK_PRI, 126 TSI108_CPU_WHOAMI, 127 TSI108_CPU_INTACK, 128 TSI108_CPU_EOI, 129 TSI108_CPU_MCACK, 130 131 TSI108_IRQ_BASE, 132 TSI108_IRQ_STRIDE, 133 TSI108_IRQ_VECTOR_PRI, 134 TSI108_VECPRI_VECTOR_MASK, 135 TSI108_VECPRI_POLARITY_POSITIVE, 136 TSI108_VECPRI_POLARITY_NEGATIVE, 137 TSI108_VECPRI_SENSE_LEVEL, 138 TSI108_VECPRI_SENSE_EDGE, 139 TSI108_VECPRI_POLARITY_MASK, 140 TSI108_VECPRI_SENSE_MASK, 141 TSI108_IRQ_DESTINATION 142 }, 143 }; 144 145 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] 146 147 #else /* CONFIG_MPIC_WEIRD */ 148 149 #define MPIC_INFO(name) MPIC_##name 150 151 #endif /* CONFIG_MPIC_WEIRD */ 152 153 static inline unsigned int mpic_processor_id(struct mpic *mpic) 154 { 155 unsigned int cpu = 0; 156 157 if (!(mpic->flags & MPIC_SECONDARY)) 158 cpu = hard_smp_processor_id(); 159 160 return cpu; 161 } 162 163 /* 164 * Register accessor functions 165 */ 166 167 168 static inline u32 _mpic_read(enum mpic_reg_type type, 169 struct mpic_reg_bank *rb, 170 unsigned int reg) 171 { 172 switch(type) { 173 #ifdef CONFIG_PPC_DCR 174 case mpic_access_dcr: 175 return dcr_read(rb->dhost, reg); 176 #endif 177 case mpic_access_mmio_be: 178 return in_be32(rb->base + (reg >> 2)); 179 case mpic_access_mmio_le: 180 default: 181 return in_le32(rb->base + (reg >> 2)); 182 } 183 } 184 185 static inline void _mpic_write(enum mpic_reg_type type, 186 struct mpic_reg_bank *rb, 187 unsigned int reg, u32 value) 188 { 189 switch(type) { 190 #ifdef CONFIG_PPC_DCR 191 case mpic_access_dcr: 192 dcr_write(rb->dhost, reg, value); 193 break; 194 #endif 195 case mpic_access_mmio_be: 196 out_be32(rb->base + (reg >> 2), value); 197 break; 198 case mpic_access_mmio_le: 199 default: 200 out_le32(rb->base + (reg >> 2), value); 201 break; 202 } 203 } 204 205 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) 206 { 207 enum mpic_reg_type type = mpic->reg_type; 208 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 209 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 210 211 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) 212 type = mpic_access_mmio_be; 213 return _mpic_read(type, &mpic->gregs, offset); 214 } 215 216 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) 217 { 218 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 219 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 220 221 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); 222 } 223 224 static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm) 225 { 226 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) + 227 ((tm & 3) * MPIC_INFO(TIMER_STRIDE)); 228 229 if (tm >= 4) 230 offset += 0x1000 / 4; 231 232 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset); 233 } 234 235 static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value) 236 { 237 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) + 238 ((tm & 3) * MPIC_INFO(TIMER_STRIDE)); 239 240 if (tm >= 4) 241 offset += 0x1000 / 4; 242 243 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value); 244 } 245 246 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) 247 { 248 unsigned int cpu = mpic_processor_id(mpic); 249 250 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); 251 } 252 253 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) 254 { 255 unsigned int cpu = mpic_processor_id(mpic); 256 257 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); 258 } 259 260 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) 261 { 262 unsigned int isu = src_no >> mpic->isu_shift; 263 unsigned int idx = src_no & mpic->isu_mask; 264 unsigned int val; 265 266 val = _mpic_read(mpic->reg_type, &mpic->isus[isu], 267 reg + (idx * MPIC_INFO(IRQ_STRIDE))); 268 #ifdef CONFIG_MPIC_BROKEN_REGREAD 269 if (reg == 0) 270 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) | 271 mpic->isu_reg0_shadow[src_no]; 272 #endif 273 return val; 274 } 275 276 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, 277 unsigned int reg, u32 value) 278 { 279 unsigned int isu = src_no >> mpic->isu_shift; 280 unsigned int idx = src_no & mpic->isu_mask; 281 282 _mpic_write(mpic->reg_type, &mpic->isus[isu], 283 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); 284 285 #ifdef CONFIG_MPIC_BROKEN_REGREAD 286 if (reg == 0) 287 mpic->isu_reg0_shadow[src_no] = 288 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY); 289 #endif 290 } 291 292 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) 293 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) 294 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) 295 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) 296 #define mpic_tm_read(i) _mpic_tm_read(mpic,(i)) 297 #define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v)) 298 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) 299 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) 300 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) 301 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) 302 303 304 /* 305 * Low level utility functions 306 */ 307 308 309 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, 310 struct mpic_reg_bank *rb, unsigned int offset, 311 unsigned int size) 312 { 313 rb->base = ioremap(phys_addr + offset, size); 314 BUG_ON(rb->base == NULL); 315 } 316 317 #ifdef CONFIG_PPC_DCR 318 static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node, 319 struct mpic_reg_bank *rb, 320 unsigned int offset, unsigned int size) 321 { 322 phys_addr_t phys_addr = dcr_resource_start(node, 0); 323 rb->dhost = dcr_map(mpic->node, phys_addr + offset, size); 324 BUG_ON(!DCR_MAP_OK(rb->dhost)); 325 } 326 327 static inline void mpic_map(struct mpic *mpic, struct device_node *node, 328 phys_addr_t phys_addr, struct mpic_reg_bank *rb, 329 unsigned int offset, unsigned int size) 330 { 331 if (mpic->flags & MPIC_USES_DCR) 332 _mpic_map_dcr(mpic, node, rb, offset, size); 333 else 334 _mpic_map_mmio(mpic, phys_addr, rb, offset, size); 335 } 336 #else /* CONFIG_PPC_DCR */ 337 #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) 338 #endif /* !CONFIG_PPC_DCR */ 339 340 341 342 /* Check if we have one of those nice broken MPICs with a flipped endian on 343 * reads from IPI registers 344 */ 345 static void __init mpic_test_broken_ipi(struct mpic *mpic) 346 { 347 u32 r; 348 349 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); 350 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); 351 352 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { 353 printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); 354 mpic->flags |= MPIC_BROKEN_IPI; 355 } 356 } 357 358 #ifdef CONFIG_MPIC_U3_HT_IRQS 359 360 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) 361 * to force the edge setting on the MPIC and do the ack workaround. 362 */ 363 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 364 { 365 if (source >= 128 || !mpic->fixups) 366 return 0; 367 return mpic->fixups[source].base != NULL; 368 } 369 370 371 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) 372 { 373 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 374 375 if (fixup->applebase) { 376 unsigned int soff = (fixup->index >> 3) & ~3; 377 unsigned int mask = 1U << (fixup->index & 0x1f); 378 writel(mask, fixup->applebase + soff); 379 } else { 380 raw_spin_lock(&mpic->fixup_lock); 381 writeb(0x11 + 2 * fixup->index, fixup->base + 2); 382 writel(fixup->data, fixup->base + 4); 383 raw_spin_unlock(&mpic->fixup_lock); 384 } 385 } 386 387 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, 388 bool level) 389 { 390 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 391 unsigned long flags; 392 u32 tmp; 393 394 if (fixup->base == NULL) 395 return; 396 397 DBG("startup_ht_interrupt(0x%x) index: %d\n", 398 source, fixup->index); 399 raw_spin_lock_irqsave(&mpic->fixup_lock, flags); 400 /* Enable and configure */ 401 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 402 tmp = readl(fixup->base + 4); 403 tmp &= ~(0x23U); 404 if (level) 405 tmp |= 0x22; 406 writel(tmp, fixup->base + 4); 407 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); 408 409 #ifdef CONFIG_PM 410 /* use the lowest bit inverted to the actual HW, 411 * set if this fixup was enabled, clear otherwise */ 412 mpic->save_data[source].fixup_data = tmp | 1; 413 #endif 414 } 415 416 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source) 417 { 418 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 419 unsigned long flags; 420 u32 tmp; 421 422 if (fixup->base == NULL) 423 return; 424 425 DBG("shutdown_ht_interrupt(0x%x)\n", source); 426 427 /* Disable */ 428 raw_spin_lock_irqsave(&mpic->fixup_lock, flags); 429 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 430 tmp = readl(fixup->base + 4); 431 tmp |= 1; 432 writel(tmp, fixup->base + 4); 433 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); 434 435 #ifdef CONFIG_PM 436 /* use the lowest bit inverted to the actual HW, 437 * set if this fixup was enabled, clear otherwise */ 438 mpic->save_data[source].fixup_data = tmp & ~1; 439 #endif 440 } 441 442 #ifdef CONFIG_PCI_MSI 443 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, 444 unsigned int devfn) 445 { 446 u8 __iomem *base; 447 u8 pos, flags; 448 u64 addr = 0; 449 450 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 451 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 452 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 453 if (id == PCI_CAP_ID_HT) { 454 id = readb(devbase + pos + 3); 455 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) 456 break; 457 } 458 } 459 460 if (pos == 0) 461 return; 462 463 base = devbase + pos; 464 465 flags = readb(base + HT_MSI_FLAGS); 466 if (!(flags & HT_MSI_FLAGS_FIXED)) { 467 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; 468 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); 469 } 470 471 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", 472 PCI_SLOT(devfn), PCI_FUNC(devfn), 473 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); 474 475 if (!(flags & HT_MSI_FLAGS_ENABLE)) 476 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); 477 } 478 #else 479 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, 480 unsigned int devfn) 481 { 482 return; 483 } 484 #endif 485 486 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, 487 unsigned int devfn, u32 vdid) 488 { 489 int i, irq, n; 490 u8 __iomem *base; 491 u32 tmp; 492 u8 pos; 493 494 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 495 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 496 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 497 if (id == PCI_CAP_ID_HT) { 498 id = readb(devbase + pos + 3); 499 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) 500 break; 501 } 502 } 503 if (pos == 0) 504 return; 505 506 base = devbase + pos; 507 writeb(0x01, base + 2); 508 n = (readl(base + 4) >> 16) & 0xff; 509 510 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" 511 " has %d irqs\n", 512 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); 513 514 for (i = 0; i <= n; i++) { 515 writeb(0x10 + 2 * i, base + 2); 516 tmp = readl(base + 4); 517 irq = (tmp >> 16) & 0xff; 518 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); 519 /* mask it , will be unmasked later */ 520 tmp |= 0x1; 521 writel(tmp, base + 4); 522 mpic->fixups[irq].index = i; 523 mpic->fixups[irq].base = base; 524 /* Apple HT PIC has a non-standard way of doing EOIs */ 525 if ((vdid & 0xffff) == 0x106b) 526 mpic->fixups[irq].applebase = devbase + 0x60; 527 else 528 mpic->fixups[irq].applebase = NULL; 529 writeb(0x11 + 2 * i, base + 2); 530 mpic->fixups[irq].data = readl(base + 4) | 0x80000000; 531 } 532 } 533 534 535 static void __init mpic_scan_ht_pics(struct mpic *mpic) 536 { 537 unsigned int devfn; 538 u8 __iomem *cfgspace; 539 540 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); 541 542 /* Allocate fixups array */ 543 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL); 544 BUG_ON(mpic->fixups == NULL); 545 546 /* Init spinlock */ 547 raw_spin_lock_init(&mpic->fixup_lock); 548 549 /* Map U3 config space. We assume all IO-APICs are on the primary bus 550 * so we only need to map 64kB. 551 */ 552 cfgspace = ioremap(0xf2000000, 0x10000); 553 BUG_ON(cfgspace == NULL); 554 555 /* Now we scan all slots. We do a very quick scan, we read the header 556 * type, vendor ID and device ID only, that's plenty enough 557 */ 558 for (devfn = 0; devfn < 0x100; devfn++) { 559 u8 __iomem *devbase = cfgspace + (devfn << 8); 560 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); 561 u32 l = readl(devbase + PCI_VENDOR_ID); 562 u16 s; 563 564 DBG("devfn %x, l: %x\n", devfn, l); 565 566 /* If no device, skip */ 567 if (l == 0xffffffff || l == 0x00000000 || 568 l == 0x0000ffff || l == 0xffff0000) 569 goto next; 570 /* Check if is supports capability lists */ 571 s = readw(devbase + PCI_STATUS); 572 if (!(s & PCI_STATUS_CAP_LIST)) 573 goto next; 574 575 mpic_scan_ht_pic(mpic, devbase, devfn, l); 576 mpic_scan_ht_msi(mpic, devbase, devfn); 577 578 next: 579 /* next device, if function 0 */ 580 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) 581 devfn += 7; 582 } 583 } 584 585 #else /* CONFIG_MPIC_U3_HT_IRQS */ 586 587 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 588 { 589 return 0; 590 } 591 592 static void __init mpic_scan_ht_pics(struct mpic *mpic) 593 { 594 } 595 596 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 597 598 /* Find an mpic associated with a given linux interrupt */ 599 static struct mpic *mpic_find(unsigned int irq) 600 { 601 if (irq < NUM_ISA_INTERRUPTS) 602 return NULL; 603 604 return irq_get_chip_data(irq); 605 } 606 607 /* Determine if the linux irq is an IPI */ 608 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq) 609 { 610 unsigned int src = virq_to_hw(irq); 611 612 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); 613 } 614 615 /* Determine if the linux irq is a timer */ 616 static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq) 617 { 618 unsigned int src = virq_to_hw(irq); 619 620 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]); 621 } 622 623 /* Convert a cpu mask from logical to physical cpu numbers. */ 624 static inline u32 mpic_physmask(u32 cpumask) 625 { 626 int i; 627 u32 mask = 0; 628 629 for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1) 630 mask |= (cpumask & 1) << get_hard_smp_processor_id(i); 631 return mask; 632 } 633 634 #ifdef CONFIG_SMP 635 /* Get the mpic structure from the IPI number */ 636 static inline struct mpic * mpic_from_ipi(struct irq_data *d) 637 { 638 return irq_data_get_irq_chip_data(d); 639 } 640 #endif 641 642 /* Get the mpic structure from the irq number */ 643 static inline struct mpic * mpic_from_irq(unsigned int irq) 644 { 645 return irq_get_chip_data(irq); 646 } 647 648 /* Get the mpic structure from the irq data */ 649 static inline struct mpic * mpic_from_irq_data(struct irq_data *d) 650 { 651 return irq_data_get_irq_chip_data(d); 652 } 653 654 /* Send an EOI */ 655 static inline void mpic_eoi(struct mpic *mpic) 656 { 657 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); 658 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); 659 } 660 661 /* 662 * Linux descriptor level callbacks 663 */ 664 665 666 void mpic_unmask_irq(struct irq_data *d) 667 { 668 unsigned int loops = 100000; 669 struct mpic *mpic = mpic_from_irq_data(d); 670 unsigned int src = irqd_to_hwirq(d); 671 672 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src); 673 674 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 675 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & 676 ~MPIC_VECPRI_MASK); 677 /* make sure mask gets to controller before we return to user */ 678 do { 679 if (!loops--) { 680 printk(KERN_ERR "%s: timeout on hwirq %u\n", 681 __func__, src); 682 break; 683 } 684 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); 685 } 686 687 void mpic_mask_irq(struct irq_data *d) 688 { 689 unsigned int loops = 100000; 690 struct mpic *mpic = mpic_from_irq_data(d); 691 unsigned int src = irqd_to_hwirq(d); 692 693 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src); 694 695 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 696 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | 697 MPIC_VECPRI_MASK); 698 699 /* make sure mask gets to controller before we return to user */ 700 do { 701 if (!loops--) { 702 printk(KERN_ERR "%s: timeout on hwirq %u\n", 703 __func__, src); 704 break; 705 } 706 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); 707 } 708 709 void mpic_end_irq(struct irq_data *d) 710 { 711 struct mpic *mpic = mpic_from_irq_data(d); 712 713 #ifdef DEBUG_IRQ 714 DBG("%s: end_irq: %d\n", mpic->name, d->irq); 715 #endif 716 /* We always EOI on end_irq() even for edge interrupts since that 717 * should only lower the priority, the MPIC should have properly 718 * latched another edge interrupt coming in anyway 719 */ 720 721 mpic_eoi(mpic); 722 } 723 724 #ifdef CONFIG_MPIC_U3_HT_IRQS 725 726 static void mpic_unmask_ht_irq(struct irq_data *d) 727 { 728 struct mpic *mpic = mpic_from_irq_data(d); 729 unsigned int src = irqd_to_hwirq(d); 730 731 mpic_unmask_irq(d); 732 733 if (irqd_is_level_type(d)) 734 mpic_ht_end_irq(mpic, src); 735 } 736 737 static unsigned int mpic_startup_ht_irq(struct irq_data *d) 738 { 739 struct mpic *mpic = mpic_from_irq_data(d); 740 unsigned int src = irqd_to_hwirq(d); 741 742 mpic_unmask_irq(d); 743 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d)); 744 745 return 0; 746 } 747 748 static void mpic_shutdown_ht_irq(struct irq_data *d) 749 { 750 struct mpic *mpic = mpic_from_irq_data(d); 751 unsigned int src = irqd_to_hwirq(d); 752 753 mpic_shutdown_ht_interrupt(mpic, src); 754 mpic_mask_irq(d); 755 } 756 757 static void mpic_end_ht_irq(struct irq_data *d) 758 { 759 struct mpic *mpic = mpic_from_irq_data(d); 760 unsigned int src = irqd_to_hwirq(d); 761 762 #ifdef DEBUG_IRQ 763 DBG("%s: end_irq: %d\n", mpic->name, d->irq); 764 #endif 765 /* We always EOI on end_irq() even for edge interrupts since that 766 * should only lower the priority, the MPIC should have properly 767 * latched another edge interrupt coming in anyway 768 */ 769 770 if (irqd_is_level_type(d)) 771 mpic_ht_end_irq(mpic, src); 772 mpic_eoi(mpic); 773 } 774 #endif /* !CONFIG_MPIC_U3_HT_IRQS */ 775 776 #ifdef CONFIG_SMP 777 778 static void mpic_unmask_ipi(struct irq_data *d) 779 { 780 struct mpic *mpic = mpic_from_ipi(d); 781 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0]; 782 783 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src); 784 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); 785 } 786 787 static void mpic_mask_ipi(struct irq_data *d) 788 { 789 /* NEVER disable an IPI... that's just plain wrong! */ 790 } 791 792 static void mpic_end_ipi(struct irq_data *d) 793 { 794 struct mpic *mpic = mpic_from_ipi(d); 795 796 /* 797 * IPIs are marked IRQ_PER_CPU. This has the side effect of 798 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from 799 * applying to them. We EOI them late to avoid re-entering. 800 */ 801 mpic_eoi(mpic); 802 } 803 804 #endif /* CONFIG_SMP */ 805 806 static void mpic_unmask_tm(struct irq_data *d) 807 { 808 struct mpic *mpic = mpic_from_irq_data(d); 809 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; 810 811 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src); 812 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK); 813 mpic_tm_read(src); 814 } 815 816 static void mpic_mask_tm(struct irq_data *d) 817 { 818 struct mpic *mpic = mpic_from_irq_data(d); 819 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; 820 821 mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK); 822 mpic_tm_read(src); 823 } 824 825 int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, 826 bool force) 827 { 828 struct mpic *mpic = mpic_from_irq_data(d); 829 unsigned int src = irqd_to_hwirq(d); 830 831 if (mpic->flags & MPIC_SINGLE_DEST_CPU) { 832 int cpuid = irq_choose_cpu(cpumask); 833 834 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); 835 } else { 836 u32 mask = cpumask_bits(cpumask)[0]; 837 838 mask &= cpumask_bits(cpu_online_mask)[0]; 839 840 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 841 mpic_physmask(mask)); 842 } 843 844 return 0; 845 } 846 847 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) 848 { 849 /* Now convert sense value */ 850 switch(type & IRQ_TYPE_SENSE_MASK) { 851 case IRQ_TYPE_EDGE_RISING: 852 return MPIC_INFO(VECPRI_SENSE_EDGE) | 853 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 854 case IRQ_TYPE_EDGE_FALLING: 855 case IRQ_TYPE_EDGE_BOTH: 856 return MPIC_INFO(VECPRI_SENSE_EDGE) | 857 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 858 case IRQ_TYPE_LEVEL_HIGH: 859 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 860 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 861 case IRQ_TYPE_LEVEL_LOW: 862 default: 863 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 864 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 865 } 866 } 867 868 int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) 869 { 870 struct mpic *mpic = mpic_from_irq_data(d); 871 unsigned int src = irqd_to_hwirq(d); 872 unsigned int vecpri, vold, vnew; 873 874 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", 875 mpic, d->irq, src, flow_type); 876 877 if (src >= mpic->irq_count) 878 return -EINVAL; 879 880 if (flow_type == IRQ_TYPE_NONE) 881 if (mpic->senses && src < mpic->senses_count) 882 flow_type = mpic->senses[src]; 883 if (flow_type == IRQ_TYPE_NONE) 884 flow_type = IRQ_TYPE_LEVEL_LOW; 885 886 irqd_set_trigger_type(d, flow_type); 887 888 if (mpic_is_ht_interrupt(mpic, src)) 889 vecpri = MPIC_VECPRI_POLARITY_POSITIVE | 890 MPIC_VECPRI_SENSE_EDGE; 891 else 892 vecpri = mpic_type_to_vecpri(mpic, flow_type); 893 894 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 895 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | 896 MPIC_INFO(VECPRI_SENSE_MASK)); 897 vnew |= vecpri; 898 if (vold != vnew) 899 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); 900 901 return IRQ_SET_MASK_OK_NOCOPY; 902 } 903 904 void mpic_set_vector(unsigned int virq, unsigned int vector) 905 { 906 struct mpic *mpic = mpic_from_irq(virq); 907 unsigned int src = virq_to_hw(virq); 908 unsigned int vecpri; 909 910 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", 911 mpic, virq, src, vector); 912 913 if (src >= mpic->irq_count) 914 return; 915 916 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 917 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK); 918 vecpri |= vector; 919 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 920 } 921 922 void mpic_set_destination(unsigned int virq, unsigned int cpuid) 923 { 924 struct mpic *mpic = mpic_from_irq(virq); 925 unsigned int src = virq_to_hw(virq); 926 927 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n", 928 mpic, virq, src, cpuid); 929 930 if (src >= mpic->irq_count) 931 return; 932 933 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); 934 } 935 936 static struct irq_chip mpic_irq_chip = { 937 .irq_mask = mpic_mask_irq, 938 .irq_unmask = mpic_unmask_irq, 939 .irq_eoi = mpic_end_irq, 940 .irq_set_type = mpic_set_irq_type, 941 }; 942 943 #ifdef CONFIG_SMP 944 static struct irq_chip mpic_ipi_chip = { 945 .irq_mask = mpic_mask_ipi, 946 .irq_unmask = mpic_unmask_ipi, 947 .irq_eoi = mpic_end_ipi, 948 }; 949 #endif /* CONFIG_SMP */ 950 951 static struct irq_chip mpic_tm_chip = { 952 .irq_mask = mpic_mask_tm, 953 .irq_unmask = mpic_unmask_tm, 954 .irq_eoi = mpic_end_irq, 955 }; 956 957 #ifdef CONFIG_MPIC_U3_HT_IRQS 958 static struct irq_chip mpic_irq_ht_chip = { 959 .irq_startup = mpic_startup_ht_irq, 960 .irq_shutdown = mpic_shutdown_ht_irq, 961 .irq_mask = mpic_mask_irq, 962 .irq_unmask = mpic_unmask_ht_irq, 963 .irq_eoi = mpic_end_ht_irq, 964 .irq_set_type = mpic_set_irq_type, 965 }; 966 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 967 968 969 static int mpic_host_match(struct irq_host *h, struct device_node *node) 970 { 971 /* Exact match, unless mpic node is NULL */ 972 return h->of_node == NULL || h->of_node == node; 973 } 974 975 static int mpic_host_map(struct irq_host *h, unsigned int virq, 976 irq_hw_number_t hw) 977 { 978 struct mpic *mpic = h->host_data; 979 struct irq_chip *chip; 980 981 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); 982 983 if (hw == mpic->spurious_vec) 984 return -EINVAL; 985 if (mpic->protected && test_bit(hw, mpic->protected)) 986 return -EINVAL; 987 988 #ifdef CONFIG_SMP 989 else if (hw >= mpic->ipi_vecs[0]) { 990 WARN_ON(mpic->flags & MPIC_SECONDARY); 991 992 DBG("mpic: mapping as IPI\n"); 993 irq_set_chip_data(virq, mpic); 994 irq_set_chip_and_handler(virq, &mpic->hc_ipi, 995 handle_percpu_irq); 996 return 0; 997 } 998 #endif /* CONFIG_SMP */ 999 1000 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) { 1001 WARN_ON(mpic->flags & MPIC_SECONDARY); 1002 1003 DBG("mpic: mapping as timer\n"); 1004 irq_set_chip_data(virq, mpic); 1005 irq_set_chip_and_handler(virq, &mpic->hc_tm, 1006 handle_fasteoi_irq); 1007 return 0; 1008 } 1009 1010 if (hw >= mpic->irq_count) 1011 return -EINVAL; 1012 1013 mpic_msi_reserve_hwirq(mpic, hw); 1014 1015 /* Default chip */ 1016 chip = &mpic->hc_irq; 1017 1018 #ifdef CONFIG_MPIC_U3_HT_IRQS 1019 /* Check for HT interrupts, override vecpri */ 1020 if (mpic_is_ht_interrupt(mpic, hw)) 1021 chip = &mpic->hc_ht_irq; 1022 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 1023 1024 DBG("mpic: mapping to irq chip @%p\n", chip); 1025 1026 irq_set_chip_data(virq, mpic); 1027 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq); 1028 1029 /* Set default irq type */ 1030 irq_set_irq_type(virq, IRQ_TYPE_NONE); 1031 1032 /* If the MPIC was reset, then all vectors have already been 1033 * initialized. Otherwise, a per source lazy initialization 1034 * is done here. 1035 */ 1036 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) { 1037 mpic_set_vector(virq, hw); 1038 mpic_set_destination(virq, mpic_processor_id(mpic)); 1039 mpic_irq_set_priority(virq, 8); 1040 } 1041 1042 return 0; 1043 } 1044 1045 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, 1046 const u32 *intspec, unsigned int intsize, 1047 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 1048 1049 { 1050 struct mpic *mpic = h->host_data; 1051 static unsigned char map_mpic_senses[4] = { 1052 IRQ_TYPE_EDGE_RISING, 1053 IRQ_TYPE_LEVEL_LOW, 1054 IRQ_TYPE_LEVEL_HIGH, 1055 IRQ_TYPE_EDGE_FALLING, 1056 }; 1057 1058 *out_hwirq = intspec[0]; 1059 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) { 1060 /* 1061 * Freescale MPIC with extended intspec: 1062 * First two cells are as usual. Third specifies 1063 * an "interrupt type". Fourth is type-specific data. 1064 * 1065 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt 1066 */ 1067 switch (intspec[2]) { 1068 case 0: 1069 case 1: /* no EISR/EIMR support for now, treat as shared IRQ */ 1070 break; 1071 case 2: 1072 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs)) 1073 return -EINVAL; 1074 1075 *out_hwirq = mpic->ipi_vecs[intspec[0]]; 1076 break; 1077 case 3: 1078 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs)) 1079 return -EINVAL; 1080 1081 *out_hwirq = mpic->timer_vecs[intspec[0]]; 1082 break; 1083 default: 1084 pr_debug("%s: unknown irq type %u\n", 1085 __func__, intspec[2]); 1086 return -EINVAL; 1087 } 1088 1089 *out_flags = map_mpic_senses[intspec[1] & 3]; 1090 } else if (intsize > 1) { 1091 u32 mask = 0x3; 1092 1093 /* Apple invented a new race of encoding on machines with 1094 * an HT APIC. They encode, among others, the index within 1095 * the HT APIC. We don't care about it here since thankfully, 1096 * it appears that they have the APIC already properly 1097 * configured, and thus our current fixup code that reads the 1098 * APIC config works fine. However, we still need to mask out 1099 * bits in the specifier to make sure we only get bit 0 which 1100 * is the level/edge bit (the only sense bit exposed by Apple), 1101 * as their bit 1 means something else. 1102 */ 1103 if (machine_is(powermac)) 1104 mask = 0x1; 1105 *out_flags = map_mpic_senses[intspec[1] & mask]; 1106 } else 1107 *out_flags = IRQ_TYPE_NONE; 1108 1109 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", 1110 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); 1111 1112 return 0; 1113 } 1114 1115 static struct irq_host_ops mpic_host_ops = { 1116 .match = mpic_host_match, 1117 .map = mpic_host_map, 1118 .xlate = mpic_host_xlate, 1119 }; 1120 1121 /* 1122 * Exported functions 1123 */ 1124 1125 struct mpic * __init mpic_alloc(struct device_node *node, 1126 phys_addr_t phys_addr, 1127 unsigned int flags, 1128 unsigned int isu_size, 1129 unsigned int irq_count, 1130 const char *name) 1131 { 1132 int i, psize, intvec_top; 1133 struct mpic *mpic; 1134 u32 greg_feature; 1135 const char *vers; 1136 const u32 *psrc; 1137 1138 /* Default MPIC search parameters */ 1139 static const struct of_device_id __initconst mpic_device_id[] = { 1140 { .type = "open-pic", }, 1141 { .compatible = "open-pic", }, 1142 {}, 1143 }; 1144 1145 /* 1146 * If we were not passed a device-tree node, then perform the default 1147 * search for standardized a standardized OpenPIC. 1148 */ 1149 if (node) { 1150 node = of_node_get(node); 1151 } else { 1152 node = of_find_matching_node(NULL, mpic_device_id); 1153 if (!node) 1154 return NULL; 1155 } 1156 1157 /* Pick the physical address from the device tree if unspecified */ 1158 if (!phys_addr) { 1159 /* Check if it is DCR-based */ 1160 if (of_get_property(node, "dcr-reg", NULL)) { 1161 flags |= MPIC_USES_DCR; 1162 } else { 1163 struct resource r; 1164 if (of_address_to_resource(node, 0, &r)) 1165 goto err_of_node_put; 1166 phys_addr = r.start; 1167 } 1168 } 1169 1170 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); 1171 if (mpic == NULL) 1172 goto err_of_node_put; 1173 1174 mpic->name = name; 1175 mpic->paddr = phys_addr; 1176 1177 mpic->hc_irq = mpic_irq_chip; 1178 mpic->hc_irq.name = name; 1179 if (!(flags & MPIC_SECONDARY)) 1180 mpic->hc_irq.irq_set_affinity = mpic_set_affinity; 1181 #ifdef CONFIG_MPIC_U3_HT_IRQS 1182 mpic->hc_ht_irq = mpic_irq_ht_chip; 1183 mpic->hc_ht_irq.name = name; 1184 if (!(flags & MPIC_SECONDARY)) 1185 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity; 1186 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 1187 1188 #ifdef CONFIG_SMP 1189 mpic->hc_ipi = mpic_ipi_chip; 1190 mpic->hc_ipi.name = name; 1191 #endif /* CONFIG_SMP */ 1192 1193 mpic->hc_tm = mpic_tm_chip; 1194 mpic->hc_tm.name = name; 1195 1196 mpic->flags = flags; 1197 mpic->isu_size = isu_size; 1198 mpic->irq_count = irq_count; 1199 mpic->num_sources = 0; /* so far */ 1200 1201 if (flags & MPIC_LARGE_VECTORS) 1202 intvec_top = 2047; 1203 else 1204 intvec_top = 255; 1205 1206 mpic->timer_vecs[0] = intvec_top - 12; 1207 mpic->timer_vecs[1] = intvec_top - 11; 1208 mpic->timer_vecs[2] = intvec_top - 10; 1209 mpic->timer_vecs[3] = intvec_top - 9; 1210 mpic->timer_vecs[4] = intvec_top - 8; 1211 mpic->timer_vecs[5] = intvec_top - 7; 1212 mpic->timer_vecs[6] = intvec_top - 6; 1213 mpic->timer_vecs[7] = intvec_top - 5; 1214 mpic->ipi_vecs[0] = intvec_top - 4; 1215 mpic->ipi_vecs[1] = intvec_top - 3; 1216 mpic->ipi_vecs[2] = intvec_top - 2; 1217 mpic->ipi_vecs[3] = intvec_top - 1; 1218 mpic->spurious_vec = intvec_top; 1219 1220 /* Check for "big-endian" in device-tree */ 1221 if (of_get_property(node, "big-endian", NULL) != NULL) 1222 mpic->flags |= MPIC_BIG_ENDIAN; 1223 if (of_device_is_compatible(node, "fsl,mpic")) 1224 mpic->flags |= MPIC_FSL; 1225 1226 /* Look for protected sources */ 1227 psrc = of_get_property(node, "protected-sources", &psize); 1228 if (psrc) { 1229 /* Allocate a bitmap with one bit per interrupt */ 1230 unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1); 1231 mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL); 1232 BUG_ON(mpic->protected == NULL); 1233 for (i = 0; i < psize/sizeof(u32); i++) { 1234 if (psrc[i] > intvec_top) 1235 continue; 1236 __set_bit(psrc[i], mpic->protected); 1237 } 1238 } 1239 1240 #ifdef CONFIG_MPIC_WEIRD 1241 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)]; 1242 #endif 1243 1244 /* default register type */ 1245 if (flags & MPIC_BIG_ENDIAN) 1246 mpic->reg_type = mpic_access_mmio_be; 1247 else 1248 mpic->reg_type = mpic_access_mmio_le; 1249 1250 /* 1251 * An MPIC with a "dcr-reg" property must be accessed that way, but 1252 * only if the kernel includes DCR support. 1253 */ 1254 #ifdef CONFIG_PPC_DCR 1255 if (flags & MPIC_USES_DCR) 1256 mpic->reg_type = mpic_access_dcr; 1257 #else 1258 BUG_ON(flags & MPIC_USES_DCR); 1259 #endif 1260 1261 /* Map the global registers */ 1262 mpic_map(mpic, node, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); 1263 mpic_map(mpic, node, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); 1264 1265 /* Reset */ 1266 1267 /* When using a device-node, reset requests are only honored if the MPIC 1268 * is allowed to reset. 1269 */ 1270 if (of_get_property(node, "pic-no-reset", NULL)) 1271 mpic->flags |= MPIC_NO_RESET; 1272 1273 if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) { 1274 printk(KERN_DEBUG "mpic: Resetting\n"); 1275 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1276 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1277 | MPIC_GREG_GCONF_RESET); 1278 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1279 & MPIC_GREG_GCONF_RESET) 1280 mb(); 1281 } 1282 1283 /* CoreInt */ 1284 if (flags & MPIC_ENABLE_COREINT) 1285 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1286 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1287 | MPIC_GREG_GCONF_COREINT); 1288 1289 if (flags & MPIC_ENABLE_MCK) 1290 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1291 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1292 | MPIC_GREG_GCONF_MCK); 1293 1294 /* 1295 * Read feature register. For non-ISU MPICs, num sources as well. On 1296 * ISU MPICs, sources are counted as ISUs are added 1297 */ 1298 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); 1299 if (isu_size == 0) { 1300 if (flags & MPIC_BROKEN_FRR_NIRQS) 1301 mpic->num_sources = mpic->irq_count; 1302 else 1303 mpic->num_sources = 1304 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) 1305 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; 1306 } 1307 1308 /* 1309 * The MPIC driver will crash if there are more cores than we 1310 * can initialize, so we may as well catch that problem here. 1311 */ 1312 BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS); 1313 1314 /* Map the per-CPU registers */ 1315 for_each_possible_cpu(i) { 1316 unsigned int cpu = get_hard_smp_processor_id(i); 1317 1318 mpic_map(mpic, node, mpic->paddr, &mpic->cpuregs[cpu], 1319 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE), 1320 0x1000); 1321 } 1322 1323 /* Initialize main ISU if none provided */ 1324 if (mpic->isu_size == 0) { 1325 mpic->isu_size = mpic->num_sources; 1326 mpic_map(mpic, node, mpic->paddr, &mpic->isus[0], 1327 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1328 } 1329 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 1330 mpic->isu_mask = (1 << mpic->isu_shift) - 1; 1331 1332 mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 1333 isu_size ? isu_size : mpic->num_sources, 1334 &mpic_host_ops, 1335 flags & MPIC_LARGE_VECTORS ? 2048 : 256); 1336 1337 /* 1338 * FIXME: The code leaks the MPIC object and mappings here; this 1339 * is very unlikely to fail but it ought to be fixed anyways. 1340 */ 1341 if (mpic->irqhost == NULL) 1342 return NULL; 1343 1344 mpic->irqhost->host_data = mpic; 1345 1346 /* Display version */ 1347 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) { 1348 case 1: 1349 vers = "1.0"; 1350 break; 1351 case 2: 1352 vers = "1.2"; 1353 break; 1354 case 3: 1355 vers = "1.3"; 1356 break; 1357 default: 1358 vers = "<unknown>"; 1359 break; 1360 } 1361 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," 1362 " max %d CPUs\n", 1363 name, vers, (unsigned long long)mpic->paddr, num_possible_cpus()); 1364 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", 1365 mpic->isu_size, mpic->isu_shift, mpic->isu_mask); 1366 1367 mpic->next = mpics; 1368 mpics = mpic; 1369 1370 if (!(flags & MPIC_SECONDARY)) { 1371 mpic_primary = mpic; 1372 irq_set_default_host(mpic->irqhost); 1373 } 1374 1375 of_node_put(node); 1376 return mpic; 1377 1378 err_of_node_put: 1379 of_node_put(node); 1380 return NULL; 1381 } 1382 1383 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, 1384 phys_addr_t paddr) 1385 { 1386 unsigned int isu_first = isu_num * mpic->isu_size; 1387 1388 BUG_ON(isu_num >= MPIC_MAX_ISU); 1389 1390 mpic_map(mpic, mpic->irqhost->of_node, 1391 paddr, &mpic->isus[isu_num], 0, 1392 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1393 1394 if ((isu_first + mpic->isu_size) > mpic->num_sources) 1395 mpic->num_sources = isu_first + mpic->isu_size; 1396 } 1397 1398 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) 1399 { 1400 mpic->senses = senses; 1401 mpic->senses_count = count; 1402 } 1403 1404 void __init mpic_init(struct mpic *mpic) 1405 { 1406 int i; 1407 int cpu; 1408 1409 BUG_ON(mpic->num_sources == 0); 1410 1411 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); 1412 1413 /* Set current processor priority to max */ 1414 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1415 1416 /* Initialize timers to our reserved vectors and mask them for now */ 1417 for (i = 0; i < 4; i++) { 1418 mpic_write(mpic->tmregs, 1419 i * MPIC_INFO(TIMER_STRIDE) + 1420 MPIC_INFO(TIMER_DESTINATION), 1421 1 << hard_smp_processor_id()); 1422 mpic_write(mpic->tmregs, 1423 i * MPIC_INFO(TIMER_STRIDE) + 1424 MPIC_INFO(TIMER_VECTOR_PRI), 1425 MPIC_VECPRI_MASK | 1426 (9 << MPIC_VECPRI_PRIORITY_SHIFT) | 1427 (mpic->timer_vecs[0] + i)); 1428 } 1429 1430 /* Initialize IPIs to our reserved vectors and mark them disabled for now */ 1431 mpic_test_broken_ipi(mpic); 1432 for (i = 0; i < 4; i++) { 1433 mpic_ipi_write(i, 1434 MPIC_VECPRI_MASK | 1435 (10 << MPIC_VECPRI_PRIORITY_SHIFT) | 1436 (mpic->ipi_vecs[0] + i)); 1437 } 1438 1439 /* Initialize interrupt sources */ 1440 if (mpic->irq_count == 0) 1441 mpic->irq_count = mpic->num_sources; 1442 1443 /* Do the HT PIC fixups on U3 broken mpic */ 1444 DBG("MPIC flags: %x\n", mpic->flags); 1445 if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) { 1446 mpic_scan_ht_pics(mpic); 1447 mpic_u3msi_init(mpic); 1448 } 1449 1450 mpic_pasemi_msi_init(mpic); 1451 1452 cpu = mpic_processor_id(mpic); 1453 1454 if (!(mpic->flags & MPIC_NO_RESET)) { 1455 for (i = 0; i < mpic->num_sources; i++) { 1456 /* start with vector = source number, and masked */ 1457 u32 vecpri = MPIC_VECPRI_MASK | i | 1458 (8 << MPIC_VECPRI_PRIORITY_SHIFT); 1459 1460 /* check if protected */ 1461 if (mpic->protected && test_bit(i, mpic->protected)) 1462 continue; 1463 /* init hw */ 1464 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 1465 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); 1466 } 1467 } 1468 1469 /* Init spurious vector */ 1470 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); 1471 1472 /* Disable 8259 passthrough, if supported */ 1473 if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) 1474 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1475 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1476 | MPIC_GREG_GCONF_8259_PTHROU_DIS); 1477 1478 if (mpic->flags & MPIC_NO_BIAS) 1479 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1480 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1481 | MPIC_GREG_GCONF_NO_BIAS); 1482 1483 /* Set current processor priority to 0 */ 1484 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 1485 1486 #ifdef CONFIG_PM 1487 /* allocate memory to save mpic state */ 1488 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data), 1489 GFP_KERNEL); 1490 BUG_ON(mpic->save_data == NULL); 1491 #endif 1492 } 1493 1494 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) 1495 { 1496 u32 v; 1497 1498 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1499 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; 1500 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); 1501 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1502 } 1503 1504 void __init mpic_set_serial_int(struct mpic *mpic, int enable) 1505 { 1506 unsigned long flags; 1507 u32 v; 1508 1509 raw_spin_lock_irqsave(&mpic_lock, flags); 1510 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1511 if (enable) 1512 v |= MPIC_GREG_GLOBAL_CONF_1_SIE; 1513 else 1514 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; 1515 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1516 raw_spin_unlock_irqrestore(&mpic_lock, flags); 1517 } 1518 1519 void mpic_irq_set_priority(unsigned int irq, unsigned int pri) 1520 { 1521 struct mpic *mpic = mpic_find(irq); 1522 unsigned int src = virq_to_hw(irq); 1523 unsigned long flags; 1524 u32 reg; 1525 1526 if (!mpic) 1527 return; 1528 1529 raw_spin_lock_irqsave(&mpic_lock, flags); 1530 if (mpic_is_ipi(mpic, irq)) { 1531 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & 1532 ~MPIC_VECPRI_PRIORITY_MASK; 1533 mpic_ipi_write(src - mpic->ipi_vecs[0], 1534 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1535 } else if (mpic_is_tm(mpic, irq)) { 1536 reg = mpic_tm_read(src - mpic->timer_vecs[0]) & 1537 ~MPIC_VECPRI_PRIORITY_MASK; 1538 mpic_tm_write(src - mpic->timer_vecs[0], 1539 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1540 } else { 1541 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) 1542 & ~MPIC_VECPRI_PRIORITY_MASK; 1543 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 1544 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1545 } 1546 raw_spin_unlock_irqrestore(&mpic_lock, flags); 1547 } 1548 1549 void mpic_setup_this_cpu(void) 1550 { 1551 #ifdef CONFIG_SMP 1552 struct mpic *mpic = mpic_primary; 1553 unsigned long flags; 1554 u32 msk = 1 << hard_smp_processor_id(); 1555 unsigned int i; 1556 1557 BUG_ON(mpic == NULL); 1558 1559 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1560 1561 raw_spin_lock_irqsave(&mpic_lock, flags); 1562 1563 /* let the mpic know we want intrs. default affinity is 0xffffffff 1564 * until changed via /proc. That's how it's done on x86. If we want 1565 * it differently, then we should make sure we also change the default 1566 * values of irq_desc[].affinity in irq.c. 1567 */ 1568 if (distribute_irqs) { 1569 for (i = 0; i < mpic->num_sources ; i++) 1570 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1571 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); 1572 } 1573 1574 /* Set current processor priority to 0 */ 1575 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 1576 1577 raw_spin_unlock_irqrestore(&mpic_lock, flags); 1578 #endif /* CONFIG_SMP */ 1579 } 1580 1581 int mpic_cpu_get_priority(void) 1582 { 1583 struct mpic *mpic = mpic_primary; 1584 1585 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); 1586 } 1587 1588 void mpic_cpu_set_priority(int prio) 1589 { 1590 struct mpic *mpic = mpic_primary; 1591 1592 prio &= MPIC_CPU_TASKPRI_MASK; 1593 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); 1594 } 1595 1596 void mpic_teardown_this_cpu(int secondary) 1597 { 1598 struct mpic *mpic = mpic_primary; 1599 unsigned long flags; 1600 u32 msk = 1 << hard_smp_processor_id(); 1601 unsigned int i; 1602 1603 BUG_ON(mpic == NULL); 1604 1605 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1606 raw_spin_lock_irqsave(&mpic_lock, flags); 1607 1608 /* let the mpic know we don't want intrs. */ 1609 for (i = 0; i < mpic->num_sources ; i++) 1610 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1611 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); 1612 1613 /* Set current processor priority to max */ 1614 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1615 /* We need to EOI the IPI since not all platforms reset the MPIC 1616 * on boot and new interrupts wouldn't get delivered otherwise. 1617 */ 1618 mpic_eoi(mpic); 1619 1620 raw_spin_unlock_irqrestore(&mpic_lock, flags); 1621 } 1622 1623 1624 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) 1625 { 1626 u32 src; 1627 1628 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); 1629 #ifdef DEBUG_LOW 1630 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); 1631 #endif 1632 if (unlikely(src == mpic->spurious_vec)) { 1633 if (mpic->flags & MPIC_SPV_EOI) 1634 mpic_eoi(mpic); 1635 return NO_IRQ; 1636 } 1637 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { 1638 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n", 1639 mpic->name, (int)src); 1640 mpic_eoi(mpic); 1641 return NO_IRQ; 1642 } 1643 1644 return irq_linear_revmap(mpic->irqhost, src); 1645 } 1646 1647 unsigned int mpic_get_one_irq(struct mpic *mpic) 1648 { 1649 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); 1650 } 1651 1652 unsigned int mpic_get_irq(void) 1653 { 1654 struct mpic *mpic = mpic_primary; 1655 1656 BUG_ON(mpic == NULL); 1657 1658 return mpic_get_one_irq(mpic); 1659 } 1660 1661 unsigned int mpic_get_coreint_irq(void) 1662 { 1663 #ifdef CONFIG_BOOKE 1664 struct mpic *mpic = mpic_primary; 1665 u32 src; 1666 1667 BUG_ON(mpic == NULL); 1668 1669 src = mfspr(SPRN_EPR); 1670 1671 if (unlikely(src == mpic->spurious_vec)) { 1672 if (mpic->flags & MPIC_SPV_EOI) 1673 mpic_eoi(mpic); 1674 return NO_IRQ; 1675 } 1676 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { 1677 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n", 1678 mpic->name, (int)src); 1679 return NO_IRQ; 1680 } 1681 1682 return irq_linear_revmap(mpic->irqhost, src); 1683 #else 1684 return NO_IRQ; 1685 #endif 1686 } 1687 1688 unsigned int mpic_get_mcirq(void) 1689 { 1690 struct mpic *mpic = mpic_primary; 1691 1692 BUG_ON(mpic == NULL); 1693 1694 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); 1695 } 1696 1697 #ifdef CONFIG_SMP 1698 void mpic_request_ipis(void) 1699 { 1700 struct mpic *mpic = mpic_primary; 1701 int i; 1702 BUG_ON(mpic == NULL); 1703 1704 printk(KERN_INFO "mpic: requesting IPIs...\n"); 1705 1706 for (i = 0; i < 4; i++) { 1707 unsigned int vipi = irq_create_mapping(mpic->irqhost, 1708 mpic->ipi_vecs[0] + i); 1709 if (vipi == NO_IRQ) { 1710 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]); 1711 continue; 1712 } 1713 smp_request_message_ipi(vipi, i); 1714 } 1715 } 1716 1717 void smp_mpic_message_pass(int cpu, int msg) 1718 { 1719 struct mpic *mpic = mpic_primary; 1720 u32 physmask; 1721 1722 BUG_ON(mpic == NULL); 1723 1724 /* make sure we're sending something that translates to an IPI */ 1725 if ((unsigned int)msg > 3) { 1726 printk("SMP %d: smp_message_pass: unknown msg %d\n", 1727 smp_processor_id(), msg); 1728 return; 1729 } 1730 1731 #ifdef DEBUG_IPI 1732 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg); 1733 #endif 1734 1735 physmask = 1 << get_hard_smp_processor_id(cpu); 1736 1737 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + 1738 msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask); 1739 } 1740 1741 int __init smp_mpic_probe(void) 1742 { 1743 int nr_cpus; 1744 1745 DBG("smp_mpic_probe()...\n"); 1746 1747 nr_cpus = cpumask_weight(cpu_possible_mask); 1748 1749 DBG("nr_cpus: %d\n", nr_cpus); 1750 1751 if (nr_cpus > 1) 1752 mpic_request_ipis(); 1753 1754 return nr_cpus; 1755 } 1756 1757 void __devinit smp_mpic_setup_cpu(int cpu) 1758 { 1759 mpic_setup_this_cpu(); 1760 } 1761 1762 void mpic_reset_core(int cpu) 1763 { 1764 struct mpic *mpic = mpic_primary; 1765 u32 pir; 1766 int cpuid = get_hard_smp_processor_id(cpu); 1767 int i; 1768 1769 /* Set target bit for core reset */ 1770 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); 1771 pir |= (1 << cpuid); 1772 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); 1773 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); 1774 1775 /* Restore target bit after reset complete */ 1776 pir &= ~(1 << cpuid); 1777 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); 1778 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); 1779 1780 /* Perform 15 EOI on each reset core to clear pending interrupts. 1781 * This is required for FSL CoreNet based devices */ 1782 if (mpic->flags & MPIC_FSL) { 1783 for (i = 0; i < 15; i++) { 1784 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid], 1785 MPIC_CPU_EOI, 0); 1786 } 1787 } 1788 } 1789 #endif /* CONFIG_SMP */ 1790 1791 #ifdef CONFIG_PM 1792 static void mpic_suspend_one(struct mpic *mpic) 1793 { 1794 int i; 1795 1796 for (i = 0; i < mpic->num_sources; i++) { 1797 mpic->save_data[i].vecprio = 1798 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); 1799 mpic->save_data[i].dest = 1800 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); 1801 } 1802 } 1803 1804 static int mpic_suspend(void) 1805 { 1806 struct mpic *mpic = mpics; 1807 1808 while (mpic) { 1809 mpic_suspend_one(mpic); 1810 mpic = mpic->next; 1811 } 1812 1813 return 0; 1814 } 1815 1816 static void mpic_resume_one(struct mpic *mpic) 1817 { 1818 int i; 1819 1820 for (i = 0; i < mpic->num_sources; i++) { 1821 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), 1822 mpic->save_data[i].vecprio); 1823 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1824 mpic->save_data[i].dest); 1825 1826 #ifdef CONFIG_MPIC_U3_HT_IRQS 1827 if (mpic->fixups) { 1828 struct mpic_irq_fixup *fixup = &mpic->fixups[i]; 1829 1830 if (fixup->base) { 1831 /* we use the lowest bit in an inverted meaning */ 1832 if ((mpic->save_data[i].fixup_data & 1) == 0) 1833 continue; 1834 1835 /* Enable and configure */ 1836 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 1837 1838 writel(mpic->save_data[i].fixup_data & ~1, 1839 fixup->base + 4); 1840 } 1841 } 1842 #endif 1843 } /* end for loop */ 1844 } 1845 1846 static void mpic_resume(void) 1847 { 1848 struct mpic *mpic = mpics; 1849 1850 while (mpic) { 1851 mpic_resume_one(mpic); 1852 mpic = mpic->next; 1853 } 1854 } 1855 1856 static struct syscore_ops mpic_syscore_ops = { 1857 .resume = mpic_resume, 1858 .suspend = mpic_suspend, 1859 }; 1860 1861 static int mpic_init_sys(void) 1862 { 1863 register_syscore_ops(&mpic_syscore_ops); 1864 return 0; 1865 } 1866 1867 device_initcall(mpic_init_sys); 1868 #endif 1869