1 /* 2 * arch/powerpc/kernel/mpic.c 3 * 4 * Driver for interrupt controllers following the OpenPIC standard, the 5 * common implementation beeing IBM's MPIC. This driver also can deal 6 * with various broken implementations of this HW. 7 * 8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file COPYING in the main directory of this archive 12 * for more details. 13 */ 14 15 #undef DEBUG 16 #undef DEBUG_IPI 17 #undef DEBUG_IRQ 18 #undef DEBUG_LOW 19 20 #include <linux/types.h> 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/irq.h> 24 #include <linux/smp.h> 25 #include <linux/interrupt.h> 26 #include <linux/bootmem.h> 27 #include <linux/spinlock.h> 28 #include <linux/pci.h> 29 30 #include <asm/ptrace.h> 31 #include <asm/signal.h> 32 #include <asm/io.h> 33 #include <asm/pgtable.h> 34 #include <asm/irq.h> 35 #include <asm/machdep.h> 36 #include <asm/mpic.h> 37 #include <asm/smp.h> 38 39 #ifdef DEBUG 40 #define DBG(fmt...) printk(fmt) 41 #else 42 #define DBG(fmt...) 43 #endif 44 45 static struct mpic *mpics; 46 static struct mpic *mpic_primary; 47 static DEFINE_SPINLOCK(mpic_lock); 48 49 #ifdef CONFIG_PPC32 /* XXX for now */ 50 #ifdef CONFIG_IRQ_ALL_CPUS 51 #define distribute_irqs (1) 52 #else 53 #define distribute_irqs (0) 54 #endif 55 #endif 56 57 #ifdef CONFIG_MPIC_WEIRD 58 static u32 mpic_infos[][MPIC_IDX_END] = { 59 [0] = { /* Original OpenPIC compatible MPIC */ 60 MPIC_GREG_BASE, 61 MPIC_GREG_FEATURE_0, 62 MPIC_GREG_GLOBAL_CONF_0, 63 MPIC_GREG_VENDOR_ID, 64 MPIC_GREG_IPI_VECTOR_PRI_0, 65 MPIC_GREG_IPI_STRIDE, 66 MPIC_GREG_SPURIOUS, 67 MPIC_GREG_TIMER_FREQ, 68 69 MPIC_TIMER_BASE, 70 MPIC_TIMER_STRIDE, 71 MPIC_TIMER_CURRENT_CNT, 72 MPIC_TIMER_BASE_CNT, 73 MPIC_TIMER_VECTOR_PRI, 74 MPIC_TIMER_DESTINATION, 75 76 MPIC_CPU_BASE, 77 MPIC_CPU_STRIDE, 78 MPIC_CPU_IPI_DISPATCH_0, 79 MPIC_CPU_IPI_DISPATCH_STRIDE, 80 MPIC_CPU_CURRENT_TASK_PRI, 81 MPIC_CPU_WHOAMI, 82 MPIC_CPU_INTACK, 83 MPIC_CPU_EOI, 84 85 MPIC_IRQ_BASE, 86 MPIC_IRQ_STRIDE, 87 MPIC_IRQ_VECTOR_PRI, 88 MPIC_VECPRI_VECTOR_MASK, 89 MPIC_VECPRI_POLARITY_POSITIVE, 90 MPIC_VECPRI_POLARITY_NEGATIVE, 91 MPIC_VECPRI_SENSE_LEVEL, 92 MPIC_VECPRI_SENSE_EDGE, 93 MPIC_VECPRI_POLARITY_MASK, 94 MPIC_VECPRI_SENSE_MASK, 95 MPIC_IRQ_DESTINATION 96 }, 97 [1] = { /* Tsi108/109 PIC */ 98 TSI108_GREG_BASE, 99 TSI108_GREG_FEATURE_0, 100 TSI108_GREG_GLOBAL_CONF_0, 101 TSI108_GREG_VENDOR_ID, 102 TSI108_GREG_IPI_VECTOR_PRI_0, 103 TSI108_GREG_IPI_STRIDE, 104 TSI108_GREG_SPURIOUS, 105 TSI108_GREG_TIMER_FREQ, 106 107 TSI108_TIMER_BASE, 108 TSI108_TIMER_STRIDE, 109 TSI108_TIMER_CURRENT_CNT, 110 TSI108_TIMER_BASE_CNT, 111 TSI108_TIMER_VECTOR_PRI, 112 TSI108_TIMER_DESTINATION, 113 114 TSI108_CPU_BASE, 115 TSI108_CPU_STRIDE, 116 TSI108_CPU_IPI_DISPATCH_0, 117 TSI108_CPU_IPI_DISPATCH_STRIDE, 118 TSI108_CPU_CURRENT_TASK_PRI, 119 TSI108_CPU_WHOAMI, 120 TSI108_CPU_INTACK, 121 TSI108_CPU_EOI, 122 123 TSI108_IRQ_BASE, 124 TSI108_IRQ_STRIDE, 125 TSI108_IRQ_VECTOR_PRI, 126 TSI108_VECPRI_VECTOR_MASK, 127 TSI108_VECPRI_POLARITY_POSITIVE, 128 TSI108_VECPRI_POLARITY_NEGATIVE, 129 TSI108_VECPRI_SENSE_LEVEL, 130 TSI108_VECPRI_SENSE_EDGE, 131 TSI108_VECPRI_POLARITY_MASK, 132 TSI108_VECPRI_SENSE_MASK, 133 TSI108_IRQ_DESTINATION 134 }, 135 }; 136 137 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] 138 139 #else /* CONFIG_MPIC_WEIRD */ 140 141 #define MPIC_INFO(name) MPIC_##name 142 143 #endif /* CONFIG_MPIC_WEIRD */ 144 145 /* 146 * Register accessor functions 147 */ 148 149 150 static inline u32 _mpic_read(enum mpic_reg_type type, 151 struct mpic_reg_bank *rb, 152 unsigned int reg) 153 { 154 switch(type) { 155 #ifdef CONFIG_PPC_DCR 156 case mpic_access_dcr: 157 return dcr_read(rb->dhost, 158 rb->dbase + reg + rb->doff); 159 #endif 160 case mpic_access_mmio_be: 161 return in_be32(rb->base + (reg >> 2)); 162 case mpic_access_mmio_le: 163 default: 164 return in_le32(rb->base + (reg >> 2)); 165 } 166 } 167 168 static inline void _mpic_write(enum mpic_reg_type type, 169 struct mpic_reg_bank *rb, 170 unsigned int reg, u32 value) 171 { 172 switch(type) { 173 #ifdef CONFIG_PPC_DCR 174 case mpic_access_dcr: 175 return dcr_write(rb->dhost, 176 rb->dbase + reg + rb->doff, value); 177 #endif 178 case mpic_access_mmio_be: 179 return out_be32(rb->base + (reg >> 2), value); 180 case mpic_access_mmio_le: 181 default: 182 return out_le32(rb->base + (reg >> 2), value); 183 } 184 } 185 186 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) 187 { 188 enum mpic_reg_type type = mpic->reg_type; 189 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 190 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 191 192 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) 193 type = mpic_access_mmio_be; 194 return _mpic_read(type, &mpic->gregs, offset); 195 } 196 197 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) 198 { 199 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 200 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 201 202 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); 203 } 204 205 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) 206 { 207 unsigned int cpu = 0; 208 209 if (mpic->flags & MPIC_PRIMARY) 210 cpu = hard_smp_processor_id(); 211 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); 212 } 213 214 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) 215 { 216 unsigned int cpu = 0; 217 218 if (mpic->flags & MPIC_PRIMARY) 219 cpu = hard_smp_processor_id(); 220 221 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); 222 } 223 224 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) 225 { 226 unsigned int isu = src_no >> mpic->isu_shift; 227 unsigned int idx = src_no & mpic->isu_mask; 228 229 return _mpic_read(mpic->reg_type, &mpic->isus[isu], 230 reg + (idx * MPIC_INFO(IRQ_STRIDE))); 231 } 232 233 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, 234 unsigned int reg, u32 value) 235 { 236 unsigned int isu = src_no >> mpic->isu_shift; 237 unsigned int idx = src_no & mpic->isu_mask; 238 239 _mpic_write(mpic->reg_type, &mpic->isus[isu], 240 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); 241 } 242 243 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) 244 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) 245 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) 246 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) 247 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) 248 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) 249 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) 250 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) 251 252 253 /* 254 * Low level utility functions 255 */ 256 257 258 static void _mpic_map_mmio(struct mpic *mpic, unsigned long phys_addr, 259 struct mpic_reg_bank *rb, unsigned int offset, 260 unsigned int size) 261 { 262 rb->base = ioremap(phys_addr + offset, size); 263 BUG_ON(rb->base == NULL); 264 } 265 266 #ifdef CONFIG_PPC_DCR 267 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, 268 unsigned int offset, unsigned int size) 269 { 270 rb->dbase = mpic->dcr_base; 271 rb->doff = offset; 272 rb->dhost = dcr_map(mpic->of_node, rb->dbase + rb->doff, size); 273 BUG_ON(!DCR_MAP_OK(rb->dhost)); 274 } 275 276 static inline void mpic_map(struct mpic *mpic, unsigned long phys_addr, 277 struct mpic_reg_bank *rb, unsigned int offset, 278 unsigned int size) 279 { 280 if (mpic->flags & MPIC_USES_DCR) 281 _mpic_map_dcr(mpic, rb, offset, size); 282 else 283 _mpic_map_mmio(mpic, phys_addr, rb, offset, size); 284 } 285 #else /* CONFIG_PPC_DCR */ 286 #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) 287 #endif /* !CONFIG_PPC_DCR */ 288 289 290 291 /* Check if we have one of those nice broken MPICs with a flipped endian on 292 * reads from IPI registers 293 */ 294 static void __init mpic_test_broken_ipi(struct mpic *mpic) 295 { 296 u32 r; 297 298 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); 299 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); 300 301 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { 302 printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); 303 mpic->flags |= MPIC_BROKEN_IPI; 304 } 305 } 306 307 #ifdef CONFIG_MPIC_U3_HT_IRQS 308 309 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) 310 * to force the edge setting on the MPIC and do the ack workaround. 311 */ 312 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 313 { 314 if (source >= 128 || !mpic->fixups) 315 return 0; 316 return mpic->fixups[source].base != NULL; 317 } 318 319 320 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) 321 { 322 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 323 324 if (fixup->applebase) { 325 unsigned int soff = (fixup->index >> 3) & ~3; 326 unsigned int mask = 1U << (fixup->index & 0x1f); 327 writel(mask, fixup->applebase + soff); 328 } else { 329 spin_lock(&mpic->fixup_lock); 330 writeb(0x11 + 2 * fixup->index, fixup->base + 2); 331 writel(fixup->data, fixup->base + 4); 332 spin_unlock(&mpic->fixup_lock); 333 } 334 } 335 336 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, 337 unsigned int irqflags) 338 { 339 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 340 unsigned long flags; 341 u32 tmp; 342 343 if (fixup->base == NULL) 344 return; 345 346 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n", 347 source, irqflags, fixup->index); 348 spin_lock_irqsave(&mpic->fixup_lock, flags); 349 /* Enable and configure */ 350 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 351 tmp = readl(fixup->base + 4); 352 tmp &= ~(0x23U); 353 if (irqflags & IRQ_LEVEL) 354 tmp |= 0x22; 355 writel(tmp, fixup->base + 4); 356 spin_unlock_irqrestore(&mpic->fixup_lock, flags); 357 } 358 359 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, 360 unsigned int irqflags) 361 { 362 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 363 unsigned long flags; 364 u32 tmp; 365 366 if (fixup->base == NULL) 367 return; 368 369 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags); 370 371 /* Disable */ 372 spin_lock_irqsave(&mpic->fixup_lock, flags); 373 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 374 tmp = readl(fixup->base + 4); 375 tmp |= 1; 376 writel(tmp, fixup->base + 4); 377 spin_unlock_irqrestore(&mpic->fixup_lock, flags); 378 } 379 380 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, 381 unsigned int devfn, u32 vdid) 382 { 383 int i, irq, n; 384 u8 __iomem *base; 385 u32 tmp; 386 u8 pos; 387 388 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 389 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 390 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 391 if (id == PCI_CAP_ID_HT) { 392 id = readb(devbase + pos + 3); 393 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) 394 break; 395 } 396 } 397 if (pos == 0) 398 return; 399 400 base = devbase + pos; 401 writeb(0x01, base + 2); 402 n = (readl(base + 4) >> 16) & 0xff; 403 404 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" 405 " has %d irqs\n", 406 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); 407 408 for (i = 0; i <= n; i++) { 409 writeb(0x10 + 2 * i, base + 2); 410 tmp = readl(base + 4); 411 irq = (tmp >> 16) & 0xff; 412 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); 413 /* mask it , will be unmasked later */ 414 tmp |= 0x1; 415 writel(tmp, base + 4); 416 mpic->fixups[irq].index = i; 417 mpic->fixups[irq].base = base; 418 /* Apple HT PIC has a non-standard way of doing EOIs */ 419 if ((vdid & 0xffff) == 0x106b) 420 mpic->fixups[irq].applebase = devbase + 0x60; 421 else 422 mpic->fixups[irq].applebase = NULL; 423 writeb(0x11 + 2 * i, base + 2); 424 mpic->fixups[irq].data = readl(base + 4) | 0x80000000; 425 } 426 } 427 428 429 static void __init mpic_scan_ht_pics(struct mpic *mpic) 430 { 431 unsigned int devfn; 432 u8 __iomem *cfgspace; 433 434 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); 435 436 /* Allocate fixups array */ 437 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup)); 438 BUG_ON(mpic->fixups == NULL); 439 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup)); 440 441 /* Init spinlock */ 442 spin_lock_init(&mpic->fixup_lock); 443 444 /* Map U3 config space. We assume all IO-APICs are on the primary bus 445 * so we only need to map 64kB. 446 */ 447 cfgspace = ioremap(0xf2000000, 0x10000); 448 BUG_ON(cfgspace == NULL); 449 450 /* Now we scan all slots. We do a very quick scan, we read the header 451 * type, vendor ID and device ID only, that's plenty enough 452 */ 453 for (devfn = 0; devfn < 0x100; devfn++) { 454 u8 __iomem *devbase = cfgspace + (devfn << 8); 455 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); 456 u32 l = readl(devbase + PCI_VENDOR_ID); 457 u16 s; 458 459 DBG("devfn %x, l: %x\n", devfn, l); 460 461 /* If no device, skip */ 462 if (l == 0xffffffff || l == 0x00000000 || 463 l == 0x0000ffff || l == 0xffff0000) 464 goto next; 465 /* Check if is supports capability lists */ 466 s = readw(devbase + PCI_STATUS); 467 if (!(s & PCI_STATUS_CAP_LIST)) 468 goto next; 469 470 mpic_scan_ht_pic(mpic, devbase, devfn, l); 471 472 next: 473 /* next device, if function 0 */ 474 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) 475 devfn += 7; 476 } 477 } 478 479 #else /* CONFIG_MPIC_U3_HT_IRQS */ 480 481 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 482 { 483 return 0; 484 } 485 486 static void __init mpic_scan_ht_pics(struct mpic *mpic) 487 { 488 } 489 490 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 491 492 493 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) 494 495 /* Find an mpic associated with a given linux interrupt */ 496 static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi) 497 { 498 unsigned int src = mpic_irq_to_hw(irq); 499 struct mpic *mpic; 500 501 if (irq < NUM_ISA_INTERRUPTS) 502 return NULL; 503 504 mpic = irq_desc[irq].chip_data; 505 506 if (is_ipi) 507 *is_ipi = (src >= mpic->ipi_vecs[0] && 508 src <= mpic->ipi_vecs[3]); 509 510 return mpic; 511 } 512 513 /* Convert a cpu mask from logical to physical cpu numbers. */ 514 static inline u32 mpic_physmask(u32 cpumask) 515 { 516 int i; 517 u32 mask = 0; 518 519 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1) 520 mask |= (cpumask & 1) << get_hard_smp_processor_id(i); 521 return mask; 522 } 523 524 #ifdef CONFIG_SMP 525 /* Get the mpic structure from the IPI number */ 526 static inline struct mpic * mpic_from_ipi(unsigned int ipi) 527 { 528 return irq_desc[ipi].chip_data; 529 } 530 #endif 531 532 /* Get the mpic structure from the irq number */ 533 static inline struct mpic * mpic_from_irq(unsigned int irq) 534 { 535 return irq_desc[irq].chip_data; 536 } 537 538 /* Send an EOI */ 539 static inline void mpic_eoi(struct mpic *mpic) 540 { 541 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); 542 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); 543 } 544 545 #ifdef CONFIG_SMP 546 static irqreturn_t mpic_ipi_action(int irq, void *dev_id) 547 { 548 struct mpic *mpic; 549 550 mpic = mpic_find(irq, NULL); 551 smp_message_recv(mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]); 552 553 return IRQ_HANDLED; 554 } 555 #endif /* CONFIG_SMP */ 556 557 /* 558 * Linux descriptor level callbacks 559 */ 560 561 562 static void mpic_unmask_irq(unsigned int irq) 563 { 564 unsigned int loops = 100000; 565 struct mpic *mpic = mpic_from_irq(irq); 566 unsigned int src = mpic_irq_to_hw(irq); 567 568 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src); 569 570 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 571 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & 572 ~MPIC_VECPRI_MASK); 573 /* make sure mask gets to controller before we return to user */ 574 do { 575 if (!loops--) { 576 printk(KERN_ERR "mpic_enable_irq timeout\n"); 577 break; 578 } 579 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); 580 } 581 582 static void mpic_mask_irq(unsigned int irq) 583 { 584 unsigned int loops = 100000; 585 struct mpic *mpic = mpic_from_irq(irq); 586 unsigned int src = mpic_irq_to_hw(irq); 587 588 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); 589 590 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 591 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | 592 MPIC_VECPRI_MASK); 593 594 /* make sure mask gets to controller before we return to user */ 595 do { 596 if (!loops--) { 597 printk(KERN_ERR "mpic_enable_irq timeout\n"); 598 break; 599 } 600 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); 601 } 602 603 static void mpic_end_irq(unsigned int irq) 604 { 605 struct mpic *mpic = mpic_from_irq(irq); 606 607 #ifdef DEBUG_IRQ 608 DBG("%s: end_irq: %d\n", mpic->name, irq); 609 #endif 610 /* We always EOI on end_irq() even for edge interrupts since that 611 * should only lower the priority, the MPIC should have properly 612 * latched another edge interrupt coming in anyway 613 */ 614 615 mpic_eoi(mpic); 616 } 617 618 #ifdef CONFIG_MPIC_U3_HT_IRQS 619 620 static void mpic_unmask_ht_irq(unsigned int irq) 621 { 622 struct mpic *mpic = mpic_from_irq(irq); 623 unsigned int src = mpic_irq_to_hw(irq); 624 625 mpic_unmask_irq(irq); 626 627 if (irq_desc[irq].status & IRQ_LEVEL) 628 mpic_ht_end_irq(mpic, src); 629 } 630 631 static unsigned int mpic_startup_ht_irq(unsigned int irq) 632 { 633 struct mpic *mpic = mpic_from_irq(irq); 634 unsigned int src = mpic_irq_to_hw(irq); 635 636 mpic_unmask_irq(irq); 637 mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status); 638 639 return 0; 640 } 641 642 static void mpic_shutdown_ht_irq(unsigned int irq) 643 { 644 struct mpic *mpic = mpic_from_irq(irq); 645 unsigned int src = mpic_irq_to_hw(irq); 646 647 mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status); 648 mpic_mask_irq(irq); 649 } 650 651 static void mpic_end_ht_irq(unsigned int irq) 652 { 653 struct mpic *mpic = mpic_from_irq(irq); 654 unsigned int src = mpic_irq_to_hw(irq); 655 656 #ifdef DEBUG_IRQ 657 DBG("%s: end_irq: %d\n", mpic->name, irq); 658 #endif 659 /* We always EOI on end_irq() even for edge interrupts since that 660 * should only lower the priority, the MPIC should have properly 661 * latched another edge interrupt coming in anyway 662 */ 663 664 if (irq_desc[irq].status & IRQ_LEVEL) 665 mpic_ht_end_irq(mpic, src); 666 mpic_eoi(mpic); 667 } 668 #endif /* !CONFIG_MPIC_U3_HT_IRQS */ 669 670 #ifdef CONFIG_SMP 671 672 static void mpic_unmask_ipi(unsigned int irq) 673 { 674 struct mpic *mpic = mpic_from_ipi(irq); 675 unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]; 676 677 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src); 678 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); 679 } 680 681 static void mpic_mask_ipi(unsigned int irq) 682 { 683 /* NEVER disable an IPI... that's just plain wrong! */ 684 } 685 686 static void mpic_end_ipi(unsigned int irq) 687 { 688 struct mpic *mpic = mpic_from_ipi(irq); 689 690 /* 691 * IPIs are marked IRQ_PER_CPU. This has the side effect of 692 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from 693 * applying to them. We EOI them late to avoid re-entering. 694 * We mark IPI's with IRQF_DISABLED as they must run with 695 * irqs disabled. 696 */ 697 mpic_eoi(mpic); 698 } 699 700 #endif /* CONFIG_SMP */ 701 702 static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask) 703 { 704 struct mpic *mpic = mpic_from_irq(irq); 705 unsigned int src = mpic_irq_to_hw(irq); 706 707 cpumask_t tmp; 708 709 cpus_and(tmp, cpumask, cpu_online_map); 710 711 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 712 mpic_physmask(cpus_addr(tmp)[0])); 713 } 714 715 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) 716 { 717 /* Now convert sense value */ 718 switch(type & IRQ_TYPE_SENSE_MASK) { 719 case IRQ_TYPE_EDGE_RISING: 720 return MPIC_INFO(VECPRI_SENSE_EDGE) | 721 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 722 case IRQ_TYPE_EDGE_FALLING: 723 case IRQ_TYPE_EDGE_BOTH: 724 return MPIC_INFO(VECPRI_SENSE_EDGE) | 725 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 726 case IRQ_TYPE_LEVEL_HIGH: 727 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 728 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 729 case IRQ_TYPE_LEVEL_LOW: 730 default: 731 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 732 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 733 } 734 } 735 736 static int mpic_set_irq_type(unsigned int virq, unsigned int flow_type) 737 { 738 struct mpic *mpic = mpic_from_irq(virq); 739 unsigned int src = mpic_irq_to_hw(virq); 740 struct irq_desc *desc = get_irq_desc(virq); 741 unsigned int vecpri, vold, vnew; 742 743 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", 744 mpic, virq, src, flow_type); 745 746 if (src >= mpic->irq_count) 747 return -EINVAL; 748 749 if (flow_type == IRQ_TYPE_NONE) 750 if (mpic->senses && src < mpic->senses_count) 751 flow_type = mpic->senses[src]; 752 if (flow_type == IRQ_TYPE_NONE) 753 flow_type = IRQ_TYPE_LEVEL_LOW; 754 755 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 756 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; 757 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 758 desc->status |= IRQ_LEVEL; 759 760 if (mpic_is_ht_interrupt(mpic, src)) 761 vecpri = MPIC_VECPRI_POLARITY_POSITIVE | 762 MPIC_VECPRI_SENSE_EDGE; 763 else 764 vecpri = mpic_type_to_vecpri(mpic, flow_type); 765 766 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 767 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | 768 MPIC_INFO(VECPRI_SENSE_MASK)); 769 vnew |= vecpri; 770 if (vold != vnew) 771 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); 772 773 return 0; 774 } 775 776 static struct irq_chip mpic_irq_chip = { 777 .mask = mpic_mask_irq, 778 .unmask = mpic_unmask_irq, 779 .eoi = mpic_end_irq, 780 .set_type = mpic_set_irq_type, 781 }; 782 783 #ifdef CONFIG_SMP 784 static struct irq_chip mpic_ipi_chip = { 785 .mask = mpic_mask_ipi, 786 .unmask = mpic_unmask_ipi, 787 .eoi = mpic_end_ipi, 788 }; 789 #endif /* CONFIG_SMP */ 790 791 #ifdef CONFIG_MPIC_U3_HT_IRQS 792 static struct irq_chip mpic_irq_ht_chip = { 793 .startup = mpic_startup_ht_irq, 794 .shutdown = mpic_shutdown_ht_irq, 795 .mask = mpic_mask_irq, 796 .unmask = mpic_unmask_ht_irq, 797 .eoi = mpic_end_ht_irq, 798 .set_type = mpic_set_irq_type, 799 }; 800 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 801 802 803 static int mpic_host_match(struct irq_host *h, struct device_node *node) 804 { 805 struct mpic *mpic = h->host_data; 806 807 /* Exact match, unless mpic node is NULL */ 808 return mpic->of_node == NULL || mpic->of_node == node; 809 } 810 811 static int mpic_host_map(struct irq_host *h, unsigned int virq, 812 irq_hw_number_t hw) 813 { 814 struct mpic *mpic = h->host_data; 815 struct irq_chip *chip; 816 817 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); 818 819 if (hw == mpic->spurious_vec) 820 return -EINVAL; 821 822 #ifdef CONFIG_SMP 823 else if (hw >= mpic->ipi_vecs[0]) { 824 WARN_ON(!(mpic->flags & MPIC_PRIMARY)); 825 826 DBG("mpic: mapping as IPI\n"); 827 set_irq_chip_data(virq, mpic); 828 set_irq_chip_and_handler(virq, &mpic->hc_ipi, 829 handle_percpu_irq); 830 return 0; 831 } 832 #endif /* CONFIG_SMP */ 833 834 if (hw >= mpic->irq_count) 835 return -EINVAL; 836 837 /* Default chip */ 838 chip = &mpic->hc_irq; 839 840 #ifdef CONFIG_MPIC_U3_HT_IRQS 841 /* Check for HT interrupts, override vecpri */ 842 if (mpic_is_ht_interrupt(mpic, hw)) 843 chip = &mpic->hc_ht_irq; 844 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 845 846 DBG("mpic: mapping to irq chip @%p\n", chip); 847 848 set_irq_chip_data(virq, mpic); 849 set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq); 850 851 /* Set default irq type */ 852 set_irq_type(virq, IRQ_TYPE_NONE); 853 854 return 0; 855 } 856 857 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, 858 u32 *intspec, unsigned int intsize, 859 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 860 861 { 862 static unsigned char map_mpic_senses[4] = { 863 IRQ_TYPE_EDGE_RISING, 864 IRQ_TYPE_LEVEL_LOW, 865 IRQ_TYPE_LEVEL_HIGH, 866 IRQ_TYPE_EDGE_FALLING, 867 }; 868 869 *out_hwirq = intspec[0]; 870 if (intsize > 1) { 871 u32 mask = 0x3; 872 873 /* Apple invented a new race of encoding on machines with 874 * an HT APIC. They encode, among others, the index within 875 * the HT APIC. We don't care about it here since thankfully, 876 * it appears that they have the APIC already properly 877 * configured, and thus our current fixup code that reads the 878 * APIC config works fine. However, we still need to mask out 879 * bits in the specifier to make sure we only get bit 0 which 880 * is the level/edge bit (the only sense bit exposed by Apple), 881 * as their bit 1 means something else. 882 */ 883 if (machine_is(powermac)) 884 mask = 0x1; 885 *out_flags = map_mpic_senses[intspec[1] & mask]; 886 } else 887 *out_flags = IRQ_TYPE_NONE; 888 889 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", 890 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); 891 892 return 0; 893 } 894 895 static struct irq_host_ops mpic_host_ops = { 896 .match = mpic_host_match, 897 .map = mpic_host_map, 898 .xlate = mpic_host_xlate, 899 }; 900 901 /* 902 * Exported functions 903 */ 904 905 struct mpic * __init mpic_alloc(struct device_node *node, 906 phys_addr_t phys_addr, 907 unsigned int flags, 908 unsigned int isu_size, 909 unsigned int irq_count, 910 const char *name) 911 { 912 struct mpic *mpic; 913 u32 reg; 914 const char *vers; 915 int i; 916 int intvec_top; 917 u64 paddr = phys_addr; 918 919 mpic = alloc_bootmem(sizeof(struct mpic)); 920 if (mpic == NULL) 921 return NULL; 922 923 memset(mpic, 0, sizeof(struct mpic)); 924 mpic->name = name; 925 mpic->of_node = of_node_get(node); 926 927 mpic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, isu_size, 928 &mpic_host_ops, 929 flags & MPIC_LARGE_VECTORS ? 2048 : 256); 930 if (mpic->irqhost == NULL) { 931 of_node_put(node); 932 return NULL; 933 } 934 935 mpic->irqhost->host_data = mpic; 936 mpic->hc_irq = mpic_irq_chip; 937 mpic->hc_irq.typename = name; 938 if (flags & MPIC_PRIMARY) 939 mpic->hc_irq.set_affinity = mpic_set_affinity; 940 #ifdef CONFIG_MPIC_U3_HT_IRQS 941 mpic->hc_ht_irq = mpic_irq_ht_chip; 942 mpic->hc_ht_irq.typename = name; 943 if (flags & MPIC_PRIMARY) 944 mpic->hc_ht_irq.set_affinity = mpic_set_affinity; 945 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 946 947 #ifdef CONFIG_SMP 948 mpic->hc_ipi = mpic_ipi_chip; 949 mpic->hc_ipi.typename = name; 950 #endif /* CONFIG_SMP */ 951 952 mpic->flags = flags; 953 mpic->isu_size = isu_size; 954 mpic->irq_count = irq_count; 955 mpic->num_sources = 0; /* so far */ 956 957 if (flags & MPIC_LARGE_VECTORS) 958 intvec_top = 2047; 959 else 960 intvec_top = 255; 961 962 mpic->timer_vecs[0] = intvec_top - 8; 963 mpic->timer_vecs[1] = intvec_top - 7; 964 mpic->timer_vecs[2] = intvec_top - 6; 965 mpic->timer_vecs[3] = intvec_top - 5; 966 mpic->ipi_vecs[0] = intvec_top - 4; 967 mpic->ipi_vecs[1] = intvec_top - 3; 968 mpic->ipi_vecs[2] = intvec_top - 2; 969 mpic->ipi_vecs[3] = intvec_top - 1; 970 mpic->spurious_vec = intvec_top; 971 972 /* Check for "big-endian" in device-tree */ 973 if (node && of_get_property(node, "big-endian", NULL) != NULL) 974 mpic->flags |= MPIC_BIG_ENDIAN; 975 976 977 #ifdef CONFIG_MPIC_WEIRD 978 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)]; 979 #endif 980 981 /* default register type */ 982 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ? 983 mpic_access_mmio_be : mpic_access_mmio_le; 984 985 /* If no physical address is passed in, a device-node is mandatory */ 986 BUG_ON(paddr == 0 && node == NULL); 987 988 /* If no physical address passed in, check if it's dcr based */ 989 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) 990 mpic->flags |= MPIC_USES_DCR; 991 992 #ifdef CONFIG_PPC_DCR 993 if (mpic->flags & MPIC_USES_DCR) { 994 const u32 *dbasep; 995 dbasep = of_get_property(node, "dcr-reg", NULL); 996 BUG_ON(dbasep == NULL); 997 mpic->dcr_base = *dbasep; 998 mpic->reg_type = mpic_access_dcr; 999 } 1000 #else 1001 BUG_ON (mpic->flags & MPIC_USES_DCR); 1002 #endif /* CONFIG_PPC_DCR */ 1003 1004 /* If the MPIC is not DCR based, and no physical address was passed 1005 * in, try to obtain one 1006 */ 1007 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) { 1008 const u32 *reg; 1009 reg = of_get_property(node, "reg", NULL); 1010 BUG_ON(reg == NULL); 1011 paddr = of_translate_address(node, reg); 1012 BUG_ON(paddr == OF_BAD_ADDR); 1013 } 1014 1015 /* Map the global registers */ 1016 mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); 1017 mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); 1018 1019 /* Reset */ 1020 if (flags & MPIC_WANTS_RESET) { 1021 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1022 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1023 | MPIC_GREG_GCONF_RESET); 1024 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1025 & MPIC_GREG_GCONF_RESET) 1026 mb(); 1027 } 1028 1029 /* Read feature register, calculate num CPUs and, for non-ISU 1030 * MPICs, num sources as well. On ISU MPICs, sources are counted 1031 * as ISUs are added 1032 */ 1033 reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); 1034 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK) 1035 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; 1036 if (isu_size == 0) 1037 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK) 1038 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; 1039 1040 /* Map the per-CPU registers */ 1041 for (i = 0; i < mpic->num_cpus; i++) { 1042 mpic_map(mpic, paddr, &mpic->cpuregs[i], 1043 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), 1044 0x1000); 1045 } 1046 1047 /* Initialize main ISU if none provided */ 1048 if (mpic->isu_size == 0) { 1049 mpic->isu_size = mpic->num_sources; 1050 mpic_map(mpic, paddr, &mpic->isus[0], 1051 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1052 } 1053 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 1054 mpic->isu_mask = (1 << mpic->isu_shift) - 1; 1055 1056 /* Display version */ 1057 switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) { 1058 case 1: 1059 vers = "1.0"; 1060 break; 1061 case 2: 1062 vers = "1.2"; 1063 break; 1064 case 3: 1065 vers = "1.3"; 1066 break; 1067 default: 1068 vers = "<unknown>"; 1069 break; 1070 } 1071 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," 1072 " max %d CPUs\n", 1073 name, vers, (unsigned long long)paddr, mpic->num_cpus); 1074 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", 1075 mpic->isu_size, mpic->isu_shift, mpic->isu_mask); 1076 1077 mpic->next = mpics; 1078 mpics = mpic; 1079 1080 if (flags & MPIC_PRIMARY) { 1081 mpic_primary = mpic; 1082 irq_set_default_host(mpic->irqhost); 1083 } 1084 1085 return mpic; 1086 } 1087 1088 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, 1089 phys_addr_t paddr) 1090 { 1091 unsigned int isu_first = isu_num * mpic->isu_size; 1092 1093 BUG_ON(isu_num >= MPIC_MAX_ISU); 1094 1095 mpic_map(mpic, paddr, &mpic->isus[isu_num], 0, 1096 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1097 if ((isu_first + mpic->isu_size) > mpic->num_sources) 1098 mpic->num_sources = isu_first + mpic->isu_size; 1099 } 1100 1101 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) 1102 { 1103 mpic->senses = senses; 1104 mpic->senses_count = count; 1105 } 1106 1107 void __init mpic_init(struct mpic *mpic) 1108 { 1109 int i; 1110 1111 BUG_ON(mpic->num_sources == 0); 1112 1113 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); 1114 1115 /* Set current processor priority to max */ 1116 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1117 1118 /* Initialize timers: just disable them all */ 1119 for (i = 0; i < 4; i++) { 1120 mpic_write(mpic->tmregs, 1121 i * MPIC_INFO(TIMER_STRIDE) + 1122 MPIC_INFO(TIMER_DESTINATION), 0); 1123 mpic_write(mpic->tmregs, 1124 i * MPIC_INFO(TIMER_STRIDE) + 1125 MPIC_INFO(TIMER_VECTOR_PRI), 1126 MPIC_VECPRI_MASK | 1127 (mpic->timer_vecs[0] + i)); 1128 } 1129 1130 /* Initialize IPIs to our reserved vectors and mark them disabled for now */ 1131 mpic_test_broken_ipi(mpic); 1132 for (i = 0; i < 4; i++) { 1133 mpic_ipi_write(i, 1134 MPIC_VECPRI_MASK | 1135 (10 << MPIC_VECPRI_PRIORITY_SHIFT) | 1136 (mpic->ipi_vecs[0] + i)); 1137 } 1138 1139 /* Initialize interrupt sources */ 1140 if (mpic->irq_count == 0) 1141 mpic->irq_count = mpic->num_sources; 1142 1143 /* Do the HT PIC fixups on U3 broken mpic */ 1144 DBG("MPIC flags: %x\n", mpic->flags); 1145 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) 1146 mpic_scan_ht_pics(mpic); 1147 1148 for (i = 0; i < mpic->num_sources; i++) { 1149 /* start with vector = source number, and masked */ 1150 u32 vecpri = MPIC_VECPRI_MASK | i | 1151 (8 << MPIC_VECPRI_PRIORITY_SHIFT); 1152 1153 /* init hw */ 1154 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 1155 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1156 1 << hard_smp_processor_id()); 1157 } 1158 1159 /* Init spurious vector */ 1160 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); 1161 1162 /* Disable 8259 passthrough, if supported */ 1163 if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) 1164 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1165 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1166 | MPIC_GREG_GCONF_8259_PTHROU_DIS); 1167 1168 /* Set current processor priority to 0 */ 1169 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 1170 } 1171 1172 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) 1173 { 1174 u32 v; 1175 1176 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1177 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; 1178 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); 1179 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1180 } 1181 1182 void __init mpic_set_serial_int(struct mpic *mpic, int enable) 1183 { 1184 unsigned long flags; 1185 u32 v; 1186 1187 spin_lock_irqsave(&mpic_lock, flags); 1188 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1189 if (enable) 1190 v |= MPIC_GREG_GLOBAL_CONF_1_SIE; 1191 else 1192 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; 1193 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1194 spin_unlock_irqrestore(&mpic_lock, flags); 1195 } 1196 1197 void mpic_irq_set_priority(unsigned int irq, unsigned int pri) 1198 { 1199 int is_ipi; 1200 struct mpic *mpic = mpic_find(irq, &is_ipi); 1201 unsigned int src = mpic_irq_to_hw(irq); 1202 unsigned long flags; 1203 u32 reg; 1204 1205 spin_lock_irqsave(&mpic_lock, flags); 1206 if (is_ipi) { 1207 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & 1208 ~MPIC_VECPRI_PRIORITY_MASK; 1209 mpic_ipi_write(src - mpic->ipi_vecs[0], 1210 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1211 } else { 1212 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) 1213 & ~MPIC_VECPRI_PRIORITY_MASK; 1214 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 1215 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1216 } 1217 spin_unlock_irqrestore(&mpic_lock, flags); 1218 } 1219 1220 unsigned int mpic_irq_get_priority(unsigned int irq) 1221 { 1222 int is_ipi; 1223 struct mpic *mpic = mpic_find(irq, &is_ipi); 1224 unsigned int src = mpic_irq_to_hw(irq); 1225 unsigned long flags; 1226 u32 reg; 1227 1228 spin_lock_irqsave(&mpic_lock, flags); 1229 if (is_ipi) 1230 reg = mpic_ipi_read(src = mpic->ipi_vecs[0]); 1231 else 1232 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 1233 spin_unlock_irqrestore(&mpic_lock, flags); 1234 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT; 1235 } 1236 1237 void mpic_setup_this_cpu(void) 1238 { 1239 #ifdef CONFIG_SMP 1240 struct mpic *mpic = mpic_primary; 1241 unsigned long flags; 1242 u32 msk = 1 << hard_smp_processor_id(); 1243 unsigned int i; 1244 1245 BUG_ON(mpic == NULL); 1246 1247 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1248 1249 spin_lock_irqsave(&mpic_lock, flags); 1250 1251 /* let the mpic know we want intrs. default affinity is 0xffffffff 1252 * until changed via /proc. That's how it's done on x86. If we want 1253 * it differently, then we should make sure we also change the default 1254 * values of irq_desc[].affinity in irq.c. 1255 */ 1256 if (distribute_irqs) { 1257 for (i = 0; i < mpic->num_sources ; i++) 1258 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1259 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); 1260 } 1261 1262 /* Set current processor priority to 0 */ 1263 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 1264 1265 spin_unlock_irqrestore(&mpic_lock, flags); 1266 #endif /* CONFIG_SMP */ 1267 } 1268 1269 int mpic_cpu_get_priority(void) 1270 { 1271 struct mpic *mpic = mpic_primary; 1272 1273 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); 1274 } 1275 1276 void mpic_cpu_set_priority(int prio) 1277 { 1278 struct mpic *mpic = mpic_primary; 1279 1280 prio &= MPIC_CPU_TASKPRI_MASK; 1281 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); 1282 } 1283 1284 /* 1285 * XXX: someone who knows mpic should check this. 1286 * do we need to eoi the ipi including for kexec cpu here (see xics comments)? 1287 * or can we reset the mpic in the new kernel? 1288 */ 1289 void mpic_teardown_this_cpu(int secondary) 1290 { 1291 struct mpic *mpic = mpic_primary; 1292 unsigned long flags; 1293 u32 msk = 1 << hard_smp_processor_id(); 1294 unsigned int i; 1295 1296 BUG_ON(mpic == NULL); 1297 1298 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1299 spin_lock_irqsave(&mpic_lock, flags); 1300 1301 /* let the mpic know we don't want intrs. */ 1302 for (i = 0; i < mpic->num_sources ; i++) 1303 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1304 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); 1305 1306 /* Set current processor priority to max */ 1307 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1308 1309 spin_unlock_irqrestore(&mpic_lock, flags); 1310 } 1311 1312 1313 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask) 1314 { 1315 struct mpic *mpic = mpic_primary; 1316 1317 BUG_ON(mpic == NULL); 1318 1319 #ifdef DEBUG_IPI 1320 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); 1321 #endif 1322 1323 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + 1324 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), 1325 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); 1326 } 1327 1328 unsigned int mpic_get_one_irq(struct mpic *mpic) 1329 { 1330 u32 src; 1331 1332 src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK); 1333 #ifdef DEBUG_LOW 1334 DBG("%s: get_one_irq(): %d\n", mpic->name, src); 1335 #endif 1336 if (unlikely(src == mpic->spurious_vec)) 1337 return NO_IRQ; 1338 return irq_linear_revmap(mpic->irqhost, src); 1339 } 1340 1341 unsigned int mpic_get_irq(void) 1342 { 1343 struct mpic *mpic = mpic_primary; 1344 1345 BUG_ON(mpic == NULL); 1346 1347 return mpic_get_one_irq(mpic); 1348 } 1349 1350 1351 #ifdef CONFIG_SMP 1352 void mpic_request_ipis(void) 1353 { 1354 struct mpic *mpic = mpic_primary; 1355 int i; 1356 static char *ipi_names[] = { 1357 "IPI0 (call function)", 1358 "IPI1 (reschedule)", 1359 "IPI2 (unused)", 1360 "IPI3 (debugger break)", 1361 }; 1362 BUG_ON(mpic == NULL); 1363 1364 printk(KERN_INFO "mpic: requesting IPIs ... \n"); 1365 1366 for (i = 0; i < 4; i++) { 1367 unsigned int vipi = irq_create_mapping(mpic->irqhost, 1368 mpic->ipi_vecs[0] + i); 1369 if (vipi == NO_IRQ) { 1370 printk(KERN_ERR "Failed to map IPI %d\n", i); 1371 break; 1372 } 1373 request_irq(vipi, mpic_ipi_action, IRQF_DISABLED|IRQF_PERCPU, 1374 ipi_names[i], mpic); 1375 } 1376 } 1377 1378 void smp_mpic_message_pass(int target, int msg) 1379 { 1380 /* make sure we're sending something that translates to an IPI */ 1381 if ((unsigned int)msg > 3) { 1382 printk("SMP %d: smp_message_pass: unknown msg %d\n", 1383 smp_processor_id(), msg); 1384 return; 1385 } 1386 switch (target) { 1387 case MSG_ALL: 1388 mpic_send_ipi(msg, 0xffffffff); 1389 break; 1390 case MSG_ALL_BUT_SELF: 1391 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id())); 1392 break; 1393 default: 1394 mpic_send_ipi(msg, 1 << target); 1395 break; 1396 } 1397 } 1398 1399 int __init smp_mpic_probe(void) 1400 { 1401 int nr_cpus; 1402 1403 DBG("smp_mpic_probe()...\n"); 1404 1405 nr_cpus = cpus_weight(cpu_possible_map); 1406 1407 DBG("nr_cpus: %d\n", nr_cpus); 1408 1409 if (nr_cpus > 1) 1410 mpic_request_ipis(); 1411 1412 return nr_cpus; 1413 } 1414 1415 void __devinit smp_mpic_setup_cpu(int cpu) 1416 { 1417 mpic_setup_this_cpu(); 1418 } 1419 #endif /* CONFIG_SMP */ 1420