1 /* 2 * arch/powerpc/kernel/mpic.c 3 * 4 * Driver for interrupt controllers following the OpenPIC standard, the 5 * common implementation beeing IBM's MPIC. This driver also can deal 6 * with various broken implementations of this HW. 7 * 8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file COPYING in the main directory of this archive 12 * for more details. 13 */ 14 15 #undef DEBUG 16 #undef DEBUG_IPI 17 #undef DEBUG_IRQ 18 #undef DEBUG_LOW 19 20 #include <linux/types.h> 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/irq.h> 24 #include <linux/smp.h> 25 #include <linux/interrupt.h> 26 #include <linux/bootmem.h> 27 #include <linux/spinlock.h> 28 #include <linux/pci.h> 29 #include <linux/slab.h> 30 31 #include <asm/ptrace.h> 32 #include <asm/signal.h> 33 #include <asm/io.h> 34 #include <asm/pgtable.h> 35 #include <asm/irq.h> 36 #include <asm/machdep.h> 37 #include <asm/mpic.h> 38 #include <asm/smp.h> 39 40 #include "mpic.h" 41 42 #ifdef DEBUG 43 #define DBG(fmt...) printk(fmt) 44 #else 45 #define DBG(fmt...) 46 #endif 47 48 static struct mpic *mpics; 49 static struct mpic *mpic_primary; 50 static DEFINE_RAW_SPINLOCK(mpic_lock); 51 52 #ifdef CONFIG_PPC32 /* XXX for now */ 53 #ifdef CONFIG_IRQ_ALL_CPUS 54 #define distribute_irqs (1) 55 #else 56 #define distribute_irqs (0) 57 #endif 58 #endif 59 60 #ifdef CONFIG_MPIC_WEIRD 61 static u32 mpic_infos[][MPIC_IDX_END] = { 62 [0] = { /* Original OpenPIC compatible MPIC */ 63 MPIC_GREG_BASE, 64 MPIC_GREG_FEATURE_0, 65 MPIC_GREG_GLOBAL_CONF_0, 66 MPIC_GREG_VENDOR_ID, 67 MPIC_GREG_IPI_VECTOR_PRI_0, 68 MPIC_GREG_IPI_STRIDE, 69 MPIC_GREG_SPURIOUS, 70 MPIC_GREG_TIMER_FREQ, 71 72 MPIC_TIMER_BASE, 73 MPIC_TIMER_STRIDE, 74 MPIC_TIMER_CURRENT_CNT, 75 MPIC_TIMER_BASE_CNT, 76 MPIC_TIMER_VECTOR_PRI, 77 MPIC_TIMER_DESTINATION, 78 79 MPIC_CPU_BASE, 80 MPIC_CPU_STRIDE, 81 MPIC_CPU_IPI_DISPATCH_0, 82 MPIC_CPU_IPI_DISPATCH_STRIDE, 83 MPIC_CPU_CURRENT_TASK_PRI, 84 MPIC_CPU_WHOAMI, 85 MPIC_CPU_INTACK, 86 MPIC_CPU_EOI, 87 MPIC_CPU_MCACK, 88 89 MPIC_IRQ_BASE, 90 MPIC_IRQ_STRIDE, 91 MPIC_IRQ_VECTOR_PRI, 92 MPIC_VECPRI_VECTOR_MASK, 93 MPIC_VECPRI_POLARITY_POSITIVE, 94 MPIC_VECPRI_POLARITY_NEGATIVE, 95 MPIC_VECPRI_SENSE_LEVEL, 96 MPIC_VECPRI_SENSE_EDGE, 97 MPIC_VECPRI_POLARITY_MASK, 98 MPIC_VECPRI_SENSE_MASK, 99 MPIC_IRQ_DESTINATION 100 }, 101 [1] = { /* Tsi108/109 PIC */ 102 TSI108_GREG_BASE, 103 TSI108_GREG_FEATURE_0, 104 TSI108_GREG_GLOBAL_CONF_0, 105 TSI108_GREG_VENDOR_ID, 106 TSI108_GREG_IPI_VECTOR_PRI_0, 107 TSI108_GREG_IPI_STRIDE, 108 TSI108_GREG_SPURIOUS, 109 TSI108_GREG_TIMER_FREQ, 110 111 TSI108_TIMER_BASE, 112 TSI108_TIMER_STRIDE, 113 TSI108_TIMER_CURRENT_CNT, 114 TSI108_TIMER_BASE_CNT, 115 TSI108_TIMER_VECTOR_PRI, 116 TSI108_TIMER_DESTINATION, 117 118 TSI108_CPU_BASE, 119 TSI108_CPU_STRIDE, 120 TSI108_CPU_IPI_DISPATCH_0, 121 TSI108_CPU_IPI_DISPATCH_STRIDE, 122 TSI108_CPU_CURRENT_TASK_PRI, 123 TSI108_CPU_WHOAMI, 124 TSI108_CPU_INTACK, 125 TSI108_CPU_EOI, 126 TSI108_CPU_MCACK, 127 128 TSI108_IRQ_BASE, 129 TSI108_IRQ_STRIDE, 130 TSI108_IRQ_VECTOR_PRI, 131 TSI108_VECPRI_VECTOR_MASK, 132 TSI108_VECPRI_POLARITY_POSITIVE, 133 TSI108_VECPRI_POLARITY_NEGATIVE, 134 TSI108_VECPRI_SENSE_LEVEL, 135 TSI108_VECPRI_SENSE_EDGE, 136 TSI108_VECPRI_POLARITY_MASK, 137 TSI108_VECPRI_SENSE_MASK, 138 TSI108_IRQ_DESTINATION 139 }, 140 }; 141 142 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] 143 144 #else /* CONFIG_MPIC_WEIRD */ 145 146 #define MPIC_INFO(name) MPIC_##name 147 148 #endif /* CONFIG_MPIC_WEIRD */ 149 150 static inline unsigned int mpic_processor_id(struct mpic *mpic) 151 { 152 unsigned int cpu = 0; 153 154 if (mpic->flags & MPIC_PRIMARY) 155 cpu = hard_smp_processor_id(); 156 157 return cpu; 158 } 159 160 /* 161 * Register accessor functions 162 */ 163 164 165 static inline u32 _mpic_read(enum mpic_reg_type type, 166 struct mpic_reg_bank *rb, 167 unsigned int reg) 168 { 169 switch(type) { 170 #ifdef CONFIG_PPC_DCR 171 case mpic_access_dcr: 172 return dcr_read(rb->dhost, reg); 173 #endif 174 case mpic_access_mmio_be: 175 return in_be32(rb->base + (reg >> 2)); 176 case mpic_access_mmio_le: 177 default: 178 return in_le32(rb->base + (reg >> 2)); 179 } 180 } 181 182 static inline void _mpic_write(enum mpic_reg_type type, 183 struct mpic_reg_bank *rb, 184 unsigned int reg, u32 value) 185 { 186 switch(type) { 187 #ifdef CONFIG_PPC_DCR 188 case mpic_access_dcr: 189 dcr_write(rb->dhost, reg, value); 190 break; 191 #endif 192 case mpic_access_mmio_be: 193 out_be32(rb->base + (reg >> 2), value); 194 break; 195 case mpic_access_mmio_le: 196 default: 197 out_le32(rb->base + (reg >> 2), value); 198 break; 199 } 200 } 201 202 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) 203 { 204 enum mpic_reg_type type = mpic->reg_type; 205 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 206 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 207 208 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) 209 type = mpic_access_mmio_be; 210 return _mpic_read(type, &mpic->gregs, offset); 211 } 212 213 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) 214 { 215 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 216 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 217 218 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); 219 } 220 221 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) 222 { 223 unsigned int cpu = mpic_processor_id(mpic); 224 225 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); 226 } 227 228 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) 229 { 230 unsigned int cpu = mpic_processor_id(mpic); 231 232 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); 233 } 234 235 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) 236 { 237 unsigned int isu = src_no >> mpic->isu_shift; 238 unsigned int idx = src_no & mpic->isu_mask; 239 unsigned int val; 240 241 val = _mpic_read(mpic->reg_type, &mpic->isus[isu], 242 reg + (idx * MPIC_INFO(IRQ_STRIDE))); 243 #ifdef CONFIG_MPIC_BROKEN_REGREAD 244 if (reg == 0) 245 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) | 246 mpic->isu_reg0_shadow[src_no]; 247 #endif 248 return val; 249 } 250 251 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, 252 unsigned int reg, u32 value) 253 { 254 unsigned int isu = src_no >> mpic->isu_shift; 255 unsigned int idx = src_no & mpic->isu_mask; 256 257 _mpic_write(mpic->reg_type, &mpic->isus[isu], 258 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); 259 260 #ifdef CONFIG_MPIC_BROKEN_REGREAD 261 if (reg == 0) 262 mpic->isu_reg0_shadow[src_no] = 263 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY); 264 #endif 265 } 266 267 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) 268 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) 269 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) 270 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) 271 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) 272 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) 273 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) 274 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) 275 276 277 /* 278 * Low level utility functions 279 */ 280 281 282 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, 283 struct mpic_reg_bank *rb, unsigned int offset, 284 unsigned int size) 285 { 286 rb->base = ioremap(phys_addr + offset, size); 287 BUG_ON(rb->base == NULL); 288 } 289 290 #ifdef CONFIG_PPC_DCR 291 static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node, 292 struct mpic_reg_bank *rb, 293 unsigned int offset, unsigned int size) 294 { 295 const u32 *dbasep; 296 297 dbasep = of_get_property(node, "dcr-reg", NULL); 298 299 rb->dhost = dcr_map(node, *dbasep + offset, size); 300 BUG_ON(!DCR_MAP_OK(rb->dhost)); 301 } 302 303 static inline void mpic_map(struct mpic *mpic, struct device_node *node, 304 phys_addr_t phys_addr, struct mpic_reg_bank *rb, 305 unsigned int offset, unsigned int size) 306 { 307 if (mpic->flags & MPIC_USES_DCR) 308 _mpic_map_dcr(mpic, node, rb, offset, size); 309 else 310 _mpic_map_mmio(mpic, phys_addr, rb, offset, size); 311 } 312 #else /* CONFIG_PPC_DCR */ 313 #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) 314 #endif /* !CONFIG_PPC_DCR */ 315 316 317 318 /* Check if we have one of those nice broken MPICs with a flipped endian on 319 * reads from IPI registers 320 */ 321 static void __init mpic_test_broken_ipi(struct mpic *mpic) 322 { 323 u32 r; 324 325 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); 326 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); 327 328 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { 329 printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); 330 mpic->flags |= MPIC_BROKEN_IPI; 331 } 332 } 333 334 #ifdef CONFIG_MPIC_U3_HT_IRQS 335 336 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) 337 * to force the edge setting on the MPIC and do the ack workaround. 338 */ 339 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 340 { 341 if (source >= 128 || !mpic->fixups) 342 return 0; 343 return mpic->fixups[source].base != NULL; 344 } 345 346 347 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) 348 { 349 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 350 351 if (fixup->applebase) { 352 unsigned int soff = (fixup->index >> 3) & ~3; 353 unsigned int mask = 1U << (fixup->index & 0x1f); 354 writel(mask, fixup->applebase + soff); 355 } else { 356 raw_spin_lock(&mpic->fixup_lock); 357 writeb(0x11 + 2 * fixup->index, fixup->base + 2); 358 writel(fixup->data, fixup->base + 4); 359 raw_spin_unlock(&mpic->fixup_lock); 360 } 361 } 362 363 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, 364 unsigned int irqflags) 365 { 366 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 367 unsigned long flags; 368 u32 tmp; 369 370 if (fixup->base == NULL) 371 return; 372 373 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n", 374 source, irqflags, fixup->index); 375 raw_spin_lock_irqsave(&mpic->fixup_lock, flags); 376 /* Enable and configure */ 377 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 378 tmp = readl(fixup->base + 4); 379 tmp &= ~(0x23U); 380 if (irqflags & IRQ_LEVEL) 381 tmp |= 0x22; 382 writel(tmp, fixup->base + 4); 383 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); 384 385 #ifdef CONFIG_PM 386 /* use the lowest bit inverted to the actual HW, 387 * set if this fixup was enabled, clear otherwise */ 388 mpic->save_data[source].fixup_data = tmp | 1; 389 #endif 390 } 391 392 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, 393 unsigned int irqflags) 394 { 395 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 396 unsigned long flags; 397 u32 tmp; 398 399 if (fixup->base == NULL) 400 return; 401 402 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags); 403 404 /* Disable */ 405 raw_spin_lock_irqsave(&mpic->fixup_lock, flags); 406 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 407 tmp = readl(fixup->base + 4); 408 tmp |= 1; 409 writel(tmp, fixup->base + 4); 410 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); 411 412 #ifdef CONFIG_PM 413 /* use the lowest bit inverted to the actual HW, 414 * set if this fixup was enabled, clear otherwise */ 415 mpic->save_data[source].fixup_data = tmp & ~1; 416 #endif 417 } 418 419 #ifdef CONFIG_PCI_MSI 420 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, 421 unsigned int devfn) 422 { 423 u8 __iomem *base; 424 u8 pos, flags; 425 u64 addr = 0; 426 427 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 428 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 429 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 430 if (id == PCI_CAP_ID_HT) { 431 id = readb(devbase + pos + 3); 432 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) 433 break; 434 } 435 } 436 437 if (pos == 0) 438 return; 439 440 base = devbase + pos; 441 442 flags = readb(base + HT_MSI_FLAGS); 443 if (!(flags & HT_MSI_FLAGS_FIXED)) { 444 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; 445 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); 446 } 447 448 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", 449 PCI_SLOT(devfn), PCI_FUNC(devfn), 450 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); 451 452 if (!(flags & HT_MSI_FLAGS_ENABLE)) 453 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); 454 } 455 #else 456 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, 457 unsigned int devfn) 458 { 459 return; 460 } 461 #endif 462 463 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, 464 unsigned int devfn, u32 vdid) 465 { 466 int i, irq, n; 467 u8 __iomem *base; 468 u32 tmp; 469 u8 pos; 470 471 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 472 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 473 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 474 if (id == PCI_CAP_ID_HT) { 475 id = readb(devbase + pos + 3); 476 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) 477 break; 478 } 479 } 480 if (pos == 0) 481 return; 482 483 base = devbase + pos; 484 writeb(0x01, base + 2); 485 n = (readl(base + 4) >> 16) & 0xff; 486 487 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" 488 " has %d irqs\n", 489 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); 490 491 for (i = 0; i <= n; i++) { 492 writeb(0x10 + 2 * i, base + 2); 493 tmp = readl(base + 4); 494 irq = (tmp >> 16) & 0xff; 495 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); 496 /* mask it , will be unmasked later */ 497 tmp |= 0x1; 498 writel(tmp, base + 4); 499 mpic->fixups[irq].index = i; 500 mpic->fixups[irq].base = base; 501 /* Apple HT PIC has a non-standard way of doing EOIs */ 502 if ((vdid & 0xffff) == 0x106b) 503 mpic->fixups[irq].applebase = devbase + 0x60; 504 else 505 mpic->fixups[irq].applebase = NULL; 506 writeb(0x11 + 2 * i, base + 2); 507 mpic->fixups[irq].data = readl(base + 4) | 0x80000000; 508 } 509 } 510 511 512 static void __init mpic_scan_ht_pics(struct mpic *mpic) 513 { 514 unsigned int devfn; 515 u8 __iomem *cfgspace; 516 517 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); 518 519 /* Allocate fixups array */ 520 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL); 521 BUG_ON(mpic->fixups == NULL); 522 523 /* Init spinlock */ 524 raw_spin_lock_init(&mpic->fixup_lock); 525 526 /* Map U3 config space. We assume all IO-APICs are on the primary bus 527 * so we only need to map 64kB. 528 */ 529 cfgspace = ioremap(0xf2000000, 0x10000); 530 BUG_ON(cfgspace == NULL); 531 532 /* Now we scan all slots. We do a very quick scan, we read the header 533 * type, vendor ID and device ID only, that's plenty enough 534 */ 535 for (devfn = 0; devfn < 0x100; devfn++) { 536 u8 __iomem *devbase = cfgspace + (devfn << 8); 537 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); 538 u32 l = readl(devbase + PCI_VENDOR_ID); 539 u16 s; 540 541 DBG("devfn %x, l: %x\n", devfn, l); 542 543 /* If no device, skip */ 544 if (l == 0xffffffff || l == 0x00000000 || 545 l == 0x0000ffff || l == 0xffff0000) 546 goto next; 547 /* Check if is supports capability lists */ 548 s = readw(devbase + PCI_STATUS); 549 if (!(s & PCI_STATUS_CAP_LIST)) 550 goto next; 551 552 mpic_scan_ht_pic(mpic, devbase, devfn, l); 553 mpic_scan_ht_msi(mpic, devbase, devfn); 554 555 next: 556 /* next device, if function 0 */ 557 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) 558 devfn += 7; 559 } 560 } 561 562 #else /* CONFIG_MPIC_U3_HT_IRQS */ 563 564 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 565 { 566 return 0; 567 } 568 569 static void __init mpic_scan_ht_pics(struct mpic *mpic) 570 { 571 } 572 573 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 574 575 #ifdef CONFIG_SMP 576 static int irq_choose_cpu(const struct cpumask *mask) 577 { 578 int cpuid; 579 580 if (cpumask_equal(mask, cpu_all_mask)) { 581 static int irq_rover = 0; 582 static DEFINE_RAW_SPINLOCK(irq_rover_lock); 583 unsigned long flags; 584 585 /* Round-robin distribution... */ 586 do_round_robin: 587 raw_spin_lock_irqsave(&irq_rover_lock, flags); 588 589 irq_rover = cpumask_next(irq_rover, cpu_online_mask); 590 if (irq_rover >= nr_cpu_ids) 591 irq_rover = cpumask_first(cpu_online_mask); 592 593 cpuid = irq_rover; 594 595 raw_spin_unlock_irqrestore(&irq_rover_lock, flags); 596 } else { 597 cpuid = cpumask_first_and(mask, cpu_online_mask); 598 if (cpuid >= nr_cpu_ids) 599 goto do_round_robin; 600 } 601 602 return get_hard_smp_processor_id(cpuid); 603 } 604 #else 605 static int irq_choose_cpu(const struct cpumask *mask) 606 { 607 return hard_smp_processor_id(); 608 } 609 #endif 610 611 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) 612 613 /* Find an mpic associated with a given linux interrupt */ 614 static struct mpic *mpic_find(unsigned int irq) 615 { 616 if (irq < NUM_ISA_INTERRUPTS) 617 return NULL; 618 619 return get_irq_chip_data(irq); 620 } 621 622 /* Determine if the linux irq is an IPI */ 623 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq) 624 { 625 unsigned int src = mpic_irq_to_hw(irq); 626 627 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); 628 } 629 630 631 /* Convert a cpu mask from logical to physical cpu numbers. */ 632 static inline u32 mpic_physmask(u32 cpumask) 633 { 634 int i; 635 u32 mask = 0; 636 637 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1) 638 mask |= (cpumask & 1) << get_hard_smp_processor_id(i); 639 return mask; 640 } 641 642 #ifdef CONFIG_SMP 643 /* Get the mpic structure from the IPI number */ 644 static inline struct mpic * mpic_from_ipi(struct irq_data *d) 645 { 646 return irq_data_get_irq_chip_data(d); 647 } 648 #endif 649 650 /* Get the mpic structure from the irq number */ 651 static inline struct mpic * mpic_from_irq(unsigned int irq) 652 { 653 return get_irq_chip_data(irq); 654 } 655 656 /* Get the mpic structure from the irq data */ 657 static inline struct mpic * mpic_from_irq_data(struct irq_data *d) 658 { 659 return irq_data_get_irq_chip_data(d); 660 } 661 662 /* Send an EOI */ 663 static inline void mpic_eoi(struct mpic *mpic) 664 { 665 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); 666 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); 667 } 668 669 /* 670 * Linux descriptor level callbacks 671 */ 672 673 674 void mpic_unmask_irq(struct irq_data *d) 675 { 676 unsigned int loops = 100000; 677 struct mpic *mpic = mpic_from_irq_data(d); 678 unsigned int src = mpic_irq_to_hw(d->irq); 679 680 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src); 681 682 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 683 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & 684 ~MPIC_VECPRI_MASK); 685 /* make sure mask gets to controller before we return to user */ 686 do { 687 if (!loops--) { 688 printk(KERN_ERR "%s: timeout on hwirq %u\n", 689 __func__, src); 690 break; 691 } 692 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); 693 } 694 695 void mpic_mask_irq(struct irq_data *d) 696 { 697 unsigned int loops = 100000; 698 struct mpic *mpic = mpic_from_irq_data(d); 699 unsigned int src = mpic_irq_to_hw(d->irq); 700 701 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src); 702 703 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 704 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | 705 MPIC_VECPRI_MASK); 706 707 /* make sure mask gets to controller before we return to user */ 708 do { 709 if (!loops--) { 710 printk(KERN_ERR "%s: timeout on hwirq %u\n", 711 __func__, src); 712 break; 713 } 714 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); 715 } 716 717 void mpic_end_irq(struct irq_data *d) 718 { 719 struct mpic *mpic = mpic_from_irq_data(d); 720 721 #ifdef DEBUG_IRQ 722 DBG("%s: end_irq: %d\n", mpic->name, d->irq); 723 #endif 724 /* We always EOI on end_irq() even for edge interrupts since that 725 * should only lower the priority, the MPIC should have properly 726 * latched another edge interrupt coming in anyway 727 */ 728 729 mpic_eoi(mpic); 730 } 731 732 #ifdef CONFIG_MPIC_U3_HT_IRQS 733 734 static void mpic_unmask_ht_irq(struct irq_data *d) 735 { 736 struct mpic *mpic = mpic_from_irq_data(d); 737 unsigned int src = mpic_irq_to_hw(d->irq); 738 739 mpic_unmask_irq(d); 740 741 if (irq_to_desc(d->irq)->status & IRQ_LEVEL) 742 mpic_ht_end_irq(mpic, src); 743 } 744 745 static unsigned int mpic_startup_ht_irq(struct irq_data *d) 746 { 747 struct mpic *mpic = mpic_from_irq_data(d); 748 unsigned int src = mpic_irq_to_hw(d->irq); 749 750 mpic_unmask_irq(d); 751 mpic_startup_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status); 752 753 return 0; 754 } 755 756 static void mpic_shutdown_ht_irq(struct irq_data *d) 757 { 758 struct mpic *mpic = mpic_from_irq_data(d); 759 unsigned int src = mpic_irq_to_hw(d->irq); 760 761 mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status); 762 mpic_mask_irq(d); 763 } 764 765 static void mpic_end_ht_irq(struct irq_data *d) 766 { 767 struct mpic *mpic = mpic_from_irq_data(d); 768 unsigned int src = mpic_irq_to_hw(d->irq); 769 770 #ifdef DEBUG_IRQ 771 DBG("%s: end_irq: %d\n", mpic->name, d->irq); 772 #endif 773 /* We always EOI on end_irq() even for edge interrupts since that 774 * should only lower the priority, the MPIC should have properly 775 * latched another edge interrupt coming in anyway 776 */ 777 778 if (irq_to_desc(d->irq)->status & IRQ_LEVEL) 779 mpic_ht_end_irq(mpic, src); 780 mpic_eoi(mpic); 781 } 782 #endif /* !CONFIG_MPIC_U3_HT_IRQS */ 783 784 #ifdef CONFIG_SMP 785 786 static void mpic_unmask_ipi(struct irq_data *d) 787 { 788 struct mpic *mpic = mpic_from_ipi(d); 789 unsigned int src = mpic_irq_to_hw(d->irq) - mpic->ipi_vecs[0]; 790 791 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src); 792 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); 793 } 794 795 static void mpic_mask_ipi(struct irq_data *d) 796 { 797 /* NEVER disable an IPI... that's just plain wrong! */ 798 } 799 800 static void mpic_end_ipi(struct irq_data *d) 801 { 802 struct mpic *mpic = mpic_from_ipi(d); 803 804 /* 805 * IPIs are marked IRQ_PER_CPU. This has the side effect of 806 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from 807 * applying to them. We EOI them late to avoid re-entering. 808 * We mark IPI's with IRQF_DISABLED as they must run with 809 * irqs disabled. 810 */ 811 mpic_eoi(mpic); 812 } 813 814 #endif /* CONFIG_SMP */ 815 816 int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, 817 bool force) 818 { 819 struct mpic *mpic = mpic_from_irq_data(d); 820 unsigned int src = mpic_irq_to_hw(d->irq); 821 822 if (mpic->flags & MPIC_SINGLE_DEST_CPU) { 823 int cpuid = irq_choose_cpu(cpumask); 824 825 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); 826 } else { 827 cpumask_var_t tmp; 828 829 alloc_cpumask_var(&tmp, GFP_KERNEL); 830 831 cpumask_and(tmp, cpumask, cpu_online_mask); 832 833 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 834 mpic_physmask(cpumask_bits(tmp)[0])); 835 836 free_cpumask_var(tmp); 837 } 838 839 return 0; 840 } 841 842 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) 843 { 844 /* Now convert sense value */ 845 switch(type & IRQ_TYPE_SENSE_MASK) { 846 case IRQ_TYPE_EDGE_RISING: 847 return MPIC_INFO(VECPRI_SENSE_EDGE) | 848 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 849 case IRQ_TYPE_EDGE_FALLING: 850 case IRQ_TYPE_EDGE_BOTH: 851 return MPIC_INFO(VECPRI_SENSE_EDGE) | 852 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 853 case IRQ_TYPE_LEVEL_HIGH: 854 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 855 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 856 case IRQ_TYPE_LEVEL_LOW: 857 default: 858 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 859 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 860 } 861 } 862 863 int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) 864 { 865 struct mpic *mpic = mpic_from_irq_data(d); 866 unsigned int src = mpic_irq_to_hw(d->irq); 867 struct irq_desc *desc = irq_to_desc(d->irq); 868 unsigned int vecpri, vold, vnew; 869 870 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", 871 mpic, d->irq, src, flow_type); 872 873 if (src >= mpic->irq_count) 874 return -EINVAL; 875 876 if (flow_type == IRQ_TYPE_NONE) 877 if (mpic->senses && src < mpic->senses_count) 878 flow_type = mpic->senses[src]; 879 if (flow_type == IRQ_TYPE_NONE) 880 flow_type = IRQ_TYPE_LEVEL_LOW; 881 882 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 883 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; 884 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 885 desc->status |= IRQ_LEVEL; 886 887 if (mpic_is_ht_interrupt(mpic, src)) 888 vecpri = MPIC_VECPRI_POLARITY_POSITIVE | 889 MPIC_VECPRI_SENSE_EDGE; 890 else 891 vecpri = mpic_type_to_vecpri(mpic, flow_type); 892 893 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 894 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | 895 MPIC_INFO(VECPRI_SENSE_MASK)); 896 vnew |= vecpri; 897 if (vold != vnew) 898 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); 899 900 return 0; 901 } 902 903 void mpic_set_vector(unsigned int virq, unsigned int vector) 904 { 905 struct mpic *mpic = mpic_from_irq(virq); 906 unsigned int src = mpic_irq_to_hw(virq); 907 unsigned int vecpri; 908 909 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", 910 mpic, virq, src, vector); 911 912 if (src >= mpic->irq_count) 913 return; 914 915 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 916 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK); 917 vecpri |= vector; 918 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 919 } 920 921 void mpic_set_destination(unsigned int virq, unsigned int cpuid) 922 { 923 struct mpic *mpic = mpic_from_irq(virq); 924 unsigned int src = mpic_irq_to_hw(virq); 925 926 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n", 927 mpic, virq, src, cpuid); 928 929 if (src >= mpic->irq_count) 930 return; 931 932 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); 933 } 934 935 static struct irq_chip mpic_irq_chip = { 936 .irq_mask = mpic_mask_irq, 937 .irq_unmask = mpic_unmask_irq, 938 .irq_eoi = mpic_end_irq, 939 .irq_set_type = mpic_set_irq_type, 940 }; 941 942 #ifdef CONFIG_SMP 943 static struct irq_chip mpic_ipi_chip = { 944 .irq_mask = mpic_mask_ipi, 945 .irq_unmask = mpic_unmask_ipi, 946 .irq_eoi = mpic_end_ipi, 947 }; 948 #endif /* CONFIG_SMP */ 949 950 #ifdef CONFIG_MPIC_U3_HT_IRQS 951 static struct irq_chip mpic_irq_ht_chip = { 952 .irq_startup = mpic_startup_ht_irq, 953 .irq_shutdown = mpic_shutdown_ht_irq, 954 .irq_mask = mpic_mask_irq, 955 .irq_unmask = mpic_unmask_ht_irq, 956 .irq_eoi = mpic_end_ht_irq, 957 .irq_set_type = mpic_set_irq_type, 958 }; 959 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 960 961 962 static int mpic_host_match(struct irq_host *h, struct device_node *node) 963 { 964 /* Exact match, unless mpic node is NULL */ 965 return h->of_node == NULL || h->of_node == node; 966 } 967 968 static int mpic_host_map(struct irq_host *h, unsigned int virq, 969 irq_hw_number_t hw) 970 { 971 struct mpic *mpic = h->host_data; 972 struct irq_chip *chip; 973 974 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); 975 976 if (hw == mpic->spurious_vec) 977 return -EINVAL; 978 if (mpic->protected && test_bit(hw, mpic->protected)) 979 return -EINVAL; 980 981 #ifdef CONFIG_SMP 982 else if (hw >= mpic->ipi_vecs[0]) { 983 WARN_ON(!(mpic->flags & MPIC_PRIMARY)); 984 985 DBG("mpic: mapping as IPI\n"); 986 set_irq_chip_data(virq, mpic); 987 set_irq_chip_and_handler(virq, &mpic->hc_ipi, 988 handle_percpu_irq); 989 return 0; 990 } 991 #endif /* CONFIG_SMP */ 992 993 if (hw >= mpic->irq_count) 994 return -EINVAL; 995 996 mpic_msi_reserve_hwirq(mpic, hw); 997 998 /* Default chip */ 999 chip = &mpic->hc_irq; 1000 1001 #ifdef CONFIG_MPIC_U3_HT_IRQS 1002 /* Check for HT interrupts, override vecpri */ 1003 if (mpic_is_ht_interrupt(mpic, hw)) 1004 chip = &mpic->hc_ht_irq; 1005 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 1006 1007 DBG("mpic: mapping to irq chip @%p\n", chip); 1008 1009 set_irq_chip_data(virq, mpic); 1010 set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq); 1011 1012 /* Set default irq type */ 1013 set_irq_type(virq, IRQ_TYPE_NONE); 1014 1015 /* If the MPIC was reset, then all vectors have already been 1016 * initialized. Otherwise, a per source lazy initialization 1017 * is done here. 1018 */ 1019 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) { 1020 mpic_set_vector(virq, hw); 1021 mpic_set_destination(virq, mpic_processor_id(mpic)); 1022 mpic_irq_set_priority(virq, 8); 1023 } 1024 1025 return 0; 1026 } 1027 1028 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, 1029 const u32 *intspec, unsigned int intsize, 1030 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 1031 1032 { 1033 static unsigned char map_mpic_senses[4] = { 1034 IRQ_TYPE_EDGE_RISING, 1035 IRQ_TYPE_LEVEL_LOW, 1036 IRQ_TYPE_LEVEL_HIGH, 1037 IRQ_TYPE_EDGE_FALLING, 1038 }; 1039 1040 *out_hwirq = intspec[0]; 1041 if (intsize > 1) { 1042 u32 mask = 0x3; 1043 1044 /* Apple invented a new race of encoding on machines with 1045 * an HT APIC. They encode, among others, the index within 1046 * the HT APIC. We don't care about it here since thankfully, 1047 * it appears that they have the APIC already properly 1048 * configured, and thus our current fixup code that reads the 1049 * APIC config works fine. However, we still need to mask out 1050 * bits in the specifier to make sure we only get bit 0 which 1051 * is the level/edge bit (the only sense bit exposed by Apple), 1052 * as their bit 1 means something else. 1053 */ 1054 if (machine_is(powermac)) 1055 mask = 0x1; 1056 *out_flags = map_mpic_senses[intspec[1] & mask]; 1057 } else 1058 *out_flags = IRQ_TYPE_NONE; 1059 1060 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", 1061 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); 1062 1063 return 0; 1064 } 1065 1066 static struct irq_host_ops mpic_host_ops = { 1067 .match = mpic_host_match, 1068 .map = mpic_host_map, 1069 .xlate = mpic_host_xlate, 1070 }; 1071 1072 static int mpic_reset_prohibited(struct device_node *node) 1073 { 1074 return node && of_get_property(node, "pic-no-reset", NULL); 1075 } 1076 1077 /* 1078 * Exported functions 1079 */ 1080 1081 struct mpic * __init mpic_alloc(struct device_node *node, 1082 phys_addr_t phys_addr, 1083 unsigned int flags, 1084 unsigned int isu_size, 1085 unsigned int irq_count, 1086 const char *name) 1087 { 1088 struct mpic *mpic; 1089 u32 greg_feature; 1090 const char *vers; 1091 int i; 1092 int intvec_top; 1093 u64 paddr = phys_addr; 1094 1095 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); 1096 if (mpic == NULL) 1097 return NULL; 1098 1099 mpic->name = name; 1100 1101 mpic->hc_irq = mpic_irq_chip; 1102 mpic->hc_irq.name = name; 1103 if (flags & MPIC_PRIMARY) 1104 mpic->hc_irq.irq_set_affinity = mpic_set_affinity; 1105 #ifdef CONFIG_MPIC_U3_HT_IRQS 1106 mpic->hc_ht_irq = mpic_irq_ht_chip; 1107 mpic->hc_ht_irq.name = name; 1108 if (flags & MPIC_PRIMARY) 1109 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity; 1110 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 1111 1112 #ifdef CONFIG_SMP 1113 mpic->hc_ipi = mpic_ipi_chip; 1114 mpic->hc_ipi.name = name; 1115 #endif /* CONFIG_SMP */ 1116 1117 mpic->flags = flags; 1118 mpic->isu_size = isu_size; 1119 mpic->irq_count = irq_count; 1120 mpic->num_sources = 0; /* so far */ 1121 1122 if (flags & MPIC_LARGE_VECTORS) 1123 intvec_top = 2047; 1124 else 1125 intvec_top = 255; 1126 1127 mpic->timer_vecs[0] = intvec_top - 8; 1128 mpic->timer_vecs[1] = intvec_top - 7; 1129 mpic->timer_vecs[2] = intvec_top - 6; 1130 mpic->timer_vecs[3] = intvec_top - 5; 1131 mpic->ipi_vecs[0] = intvec_top - 4; 1132 mpic->ipi_vecs[1] = intvec_top - 3; 1133 mpic->ipi_vecs[2] = intvec_top - 2; 1134 mpic->ipi_vecs[3] = intvec_top - 1; 1135 mpic->spurious_vec = intvec_top; 1136 1137 /* Check for "big-endian" in device-tree */ 1138 if (node && of_get_property(node, "big-endian", NULL) != NULL) 1139 mpic->flags |= MPIC_BIG_ENDIAN; 1140 1141 /* Look for protected sources */ 1142 if (node) { 1143 int psize; 1144 unsigned int bits, mapsize; 1145 const u32 *psrc = 1146 of_get_property(node, "protected-sources", &psize); 1147 if (psrc) { 1148 psize /= 4; 1149 bits = intvec_top + 1; 1150 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long); 1151 mpic->protected = kzalloc(mapsize, GFP_KERNEL); 1152 BUG_ON(mpic->protected == NULL); 1153 for (i = 0; i < psize; i++) { 1154 if (psrc[i] > intvec_top) 1155 continue; 1156 __set_bit(psrc[i], mpic->protected); 1157 } 1158 } 1159 } 1160 1161 #ifdef CONFIG_MPIC_WEIRD 1162 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)]; 1163 #endif 1164 1165 /* default register type */ 1166 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ? 1167 mpic_access_mmio_be : mpic_access_mmio_le; 1168 1169 /* If no physical address is passed in, a device-node is mandatory */ 1170 BUG_ON(paddr == 0 && node == NULL); 1171 1172 /* If no physical address passed in, check if it's dcr based */ 1173 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) { 1174 #ifdef CONFIG_PPC_DCR 1175 mpic->flags |= MPIC_USES_DCR; 1176 mpic->reg_type = mpic_access_dcr; 1177 #else 1178 BUG(); 1179 #endif /* CONFIG_PPC_DCR */ 1180 } 1181 1182 /* If the MPIC is not DCR based, and no physical address was passed 1183 * in, try to obtain one 1184 */ 1185 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) { 1186 const u32 *reg = of_get_property(node, "reg", NULL); 1187 BUG_ON(reg == NULL); 1188 paddr = of_translate_address(node, reg); 1189 BUG_ON(paddr == OF_BAD_ADDR); 1190 } 1191 1192 /* Map the global registers */ 1193 mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); 1194 mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); 1195 1196 /* Reset */ 1197 1198 /* When using a device-node, reset requests are only honored if the MPIC 1199 * is allowed to reset. 1200 */ 1201 if (mpic_reset_prohibited(node)) 1202 mpic->flags |= MPIC_NO_RESET; 1203 1204 if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) { 1205 printk(KERN_DEBUG "mpic: Resetting\n"); 1206 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1207 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1208 | MPIC_GREG_GCONF_RESET); 1209 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1210 & MPIC_GREG_GCONF_RESET) 1211 mb(); 1212 } 1213 1214 /* CoreInt */ 1215 if (flags & MPIC_ENABLE_COREINT) 1216 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1217 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1218 | MPIC_GREG_GCONF_COREINT); 1219 1220 if (flags & MPIC_ENABLE_MCK) 1221 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1222 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1223 | MPIC_GREG_GCONF_MCK); 1224 1225 /* Read feature register, calculate num CPUs and, for non-ISU 1226 * MPICs, num sources as well. On ISU MPICs, sources are counted 1227 * as ISUs are added 1228 */ 1229 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); 1230 mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK) 1231 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; 1232 if (isu_size == 0) { 1233 if (flags & MPIC_BROKEN_FRR_NIRQS) 1234 mpic->num_sources = mpic->irq_count; 1235 else 1236 mpic->num_sources = 1237 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) 1238 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; 1239 } 1240 1241 /* Map the per-CPU registers */ 1242 for (i = 0; i < mpic->num_cpus; i++) { 1243 mpic_map(mpic, node, paddr, &mpic->cpuregs[i], 1244 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), 1245 0x1000); 1246 } 1247 1248 /* Initialize main ISU if none provided */ 1249 if (mpic->isu_size == 0) { 1250 mpic->isu_size = mpic->num_sources; 1251 mpic_map(mpic, node, paddr, &mpic->isus[0], 1252 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1253 } 1254 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 1255 mpic->isu_mask = (1 << mpic->isu_shift) - 1; 1256 1257 mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 1258 isu_size ? isu_size : mpic->num_sources, 1259 &mpic_host_ops, 1260 flags & MPIC_LARGE_VECTORS ? 2048 : 256); 1261 if (mpic->irqhost == NULL) 1262 return NULL; 1263 1264 mpic->irqhost->host_data = mpic; 1265 1266 /* Display version */ 1267 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) { 1268 case 1: 1269 vers = "1.0"; 1270 break; 1271 case 2: 1272 vers = "1.2"; 1273 break; 1274 case 3: 1275 vers = "1.3"; 1276 break; 1277 default: 1278 vers = "<unknown>"; 1279 break; 1280 } 1281 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," 1282 " max %d CPUs\n", 1283 name, vers, (unsigned long long)paddr, mpic->num_cpus); 1284 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", 1285 mpic->isu_size, mpic->isu_shift, mpic->isu_mask); 1286 1287 mpic->next = mpics; 1288 mpics = mpic; 1289 1290 if (flags & MPIC_PRIMARY) { 1291 mpic_primary = mpic; 1292 irq_set_default_host(mpic->irqhost); 1293 } 1294 1295 return mpic; 1296 } 1297 1298 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, 1299 phys_addr_t paddr) 1300 { 1301 unsigned int isu_first = isu_num * mpic->isu_size; 1302 1303 BUG_ON(isu_num >= MPIC_MAX_ISU); 1304 1305 mpic_map(mpic, mpic->irqhost->of_node, 1306 paddr, &mpic->isus[isu_num], 0, 1307 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1308 1309 if ((isu_first + mpic->isu_size) > mpic->num_sources) 1310 mpic->num_sources = isu_first + mpic->isu_size; 1311 } 1312 1313 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) 1314 { 1315 mpic->senses = senses; 1316 mpic->senses_count = count; 1317 } 1318 1319 void __init mpic_init(struct mpic *mpic) 1320 { 1321 int i; 1322 int cpu; 1323 1324 BUG_ON(mpic->num_sources == 0); 1325 1326 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); 1327 1328 /* Set current processor priority to max */ 1329 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1330 1331 /* Initialize timers: just disable them all */ 1332 for (i = 0; i < 4; i++) { 1333 mpic_write(mpic->tmregs, 1334 i * MPIC_INFO(TIMER_STRIDE) + 1335 MPIC_INFO(TIMER_DESTINATION), 0); 1336 mpic_write(mpic->tmregs, 1337 i * MPIC_INFO(TIMER_STRIDE) + 1338 MPIC_INFO(TIMER_VECTOR_PRI), 1339 MPIC_VECPRI_MASK | 1340 (mpic->timer_vecs[0] + i)); 1341 } 1342 1343 /* Initialize IPIs to our reserved vectors and mark them disabled for now */ 1344 mpic_test_broken_ipi(mpic); 1345 for (i = 0; i < 4; i++) { 1346 mpic_ipi_write(i, 1347 MPIC_VECPRI_MASK | 1348 (10 << MPIC_VECPRI_PRIORITY_SHIFT) | 1349 (mpic->ipi_vecs[0] + i)); 1350 } 1351 1352 /* Initialize interrupt sources */ 1353 if (mpic->irq_count == 0) 1354 mpic->irq_count = mpic->num_sources; 1355 1356 /* Do the HT PIC fixups on U3 broken mpic */ 1357 DBG("MPIC flags: %x\n", mpic->flags); 1358 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) { 1359 mpic_scan_ht_pics(mpic); 1360 mpic_u3msi_init(mpic); 1361 } 1362 1363 mpic_pasemi_msi_init(mpic); 1364 1365 cpu = mpic_processor_id(mpic); 1366 1367 if (!(mpic->flags & MPIC_NO_RESET)) { 1368 for (i = 0; i < mpic->num_sources; i++) { 1369 /* start with vector = source number, and masked */ 1370 u32 vecpri = MPIC_VECPRI_MASK | i | 1371 (8 << MPIC_VECPRI_PRIORITY_SHIFT); 1372 1373 /* check if protected */ 1374 if (mpic->protected && test_bit(i, mpic->protected)) 1375 continue; 1376 /* init hw */ 1377 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 1378 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); 1379 } 1380 } 1381 1382 /* Init spurious vector */ 1383 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); 1384 1385 /* Disable 8259 passthrough, if supported */ 1386 if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) 1387 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1388 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1389 | MPIC_GREG_GCONF_8259_PTHROU_DIS); 1390 1391 if (mpic->flags & MPIC_NO_BIAS) 1392 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1393 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1394 | MPIC_GREG_GCONF_NO_BIAS); 1395 1396 /* Set current processor priority to 0 */ 1397 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 1398 1399 #ifdef CONFIG_PM 1400 /* allocate memory to save mpic state */ 1401 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data), 1402 GFP_KERNEL); 1403 BUG_ON(mpic->save_data == NULL); 1404 #endif 1405 } 1406 1407 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) 1408 { 1409 u32 v; 1410 1411 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1412 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; 1413 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); 1414 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1415 } 1416 1417 void __init mpic_set_serial_int(struct mpic *mpic, int enable) 1418 { 1419 unsigned long flags; 1420 u32 v; 1421 1422 raw_spin_lock_irqsave(&mpic_lock, flags); 1423 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1424 if (enable) 1425 v |= MPIC_GREG_GLOBAL_CONF_1_SIE; 1426 else 1427 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; 1428 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1429 raw_spin_unlock_irqrestore(&mpic_lock, flags); 1430 } 1431 1432 void mpic_irq_set_priority(unsigned int irq, unsigned int pri) 1433 { 1434 struct mpic *mpic = mpic_find(irq); 1435 unsigned int src = mpic_irq_to_hw(irq); 1436 unsigned long flags; 1437 u32 reg; 1438 1439 if (!mpic) 1440 return; 1441 1442 raw_spin_lock_irqsave(&mpic_lock, flags); 1443 if (mpic_is_ipi(mpic, irq)) { 1444 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & 1445 ~MPIC_VECPRI_PRIORITY_MASK; 1446 mpic_ipi_write(src - mpic->ipi_vecs[0], 1447 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1448 } else { 1449 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) 1450 & ~MPIC_VECPRI_PRIORITY_MASK; 1451 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 1452 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1453 } 1454 raw_spin_unlock_irqrestore(&mpic_lock, flags); 1455 } 1456 1457 void mpic_setup_this_cpu(void) 1458 { 1459 #ifdef CONFIG_SMP 1460 struct mpic *mpic = mpic_primary; 1461 unsigned long flags; 1462 u32 msk = 1 << hard_smp_processor_id(); 1463 unsigned int i; 1464 1465 BUG_ON(mpic == NULL); 1466 1467 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1468 1469 raw_spin_lock_irqsave(&mpic_lock, flags); 1470 1471 /* let the mpic know we want intrs. default affinity is 0xffffffff 1472 * until changed via /proc. That's how it's done on x86. If we want 1473 * it differently, then we should make sure we also change the default 1474 * values of irq_desc[].affinity in irq.c. 1475 */ 1476 if (distribute_irqs) { 1477 for (i = 0; i < mpic->num_sources ; i++) 1478 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1479 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); 1480 } 1481 1482 /* Set current processor priority to 0 */ 1483 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 1484 1485 raw_spin_unlock_irqrestore(&mpic_lock, flags); 1486 #endif /* CONFIG_SMP */ 1487 } 1488 1489 int mpic_cpu_get_priority(void) 1490 { 1491 struct mpic *mpic = mpic_primary; 1492 1493 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); 1494 } 1495 1496 void mpic_cpu_set_priority(int prio) 1497 { 1498 struct mpic *mpic = mpic_primary; 1499 1500 prio &= MPIC_CPU_TASKPRI_MASK; 1501 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); 1502 } 1503 1504 void mpic_teardown_this_cpu(int secondary) 1505 { 1506 struct mpic *mpic = mpic_primary; 1507 unsigned long flags; 1508 u32 msk = 1 << hard_smp_processor_id(); 1509 unsigned int i; 1510 1511 BUG_ON(mpic == NULL); 1512 1513 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1514 raw_spin_lock_irqsave(&mpic_lock, flags); 1515 1516 /* let the mpic know we don't want intrs. */ 1517 for (i = 0; i < mpic->num_sources ; i++) 1518 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1519 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); 1520 1521 /* Set current processor priority to max */ 1522 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1523 /* We need to EOI the IPI since not all platforms reset the MPIC 1524 * on boot and new interrupts wouldn't get delivered otherwise. 1525 */ 1526 mpic_eoi(mpic); 1527 1528 raw_spin_unlock_irqrestore(&mpic_lock, flags); 1529 } 1530 1531 1532 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) 1533 { 1534 u32 src; 1535 1536 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); 1537 #ifdef DEBUG_LOW 1538 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); 1539 #endif 1540 if (unlikely(src == mpic->spurious_vec)) { 1541 if (mpic->flags & MPIC_SPV_EOI) 1542 mpic_eoi(mpic); 1543 return NO_IRQ; 1544 } 1545 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { 1546 if (printk_ratelimit()) 1547 printk(KERN_WARNING "%s: Got protected source %d !\n", 1548 mpic->name, (int)src); 1549 mpic_eoi(mpic); 1550 return NO_IRQ; 1551 } 1552 1553 return irq_linear_revmap(mpic->irqhost, src); 1554 } 1555 1556 unsigned int mpic_get_one_irq(struct mpic *mpic) 1557 { 1558 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); 1559 } 1560 1561 unsigned int mpic_get_irq(void) 1562 { 1563 struct mpic *mpic = mpic_primary; 1564 1565 BUG_ON(mpic == NULL); 1566 1567 return mpic_get_one_irq(mpic); 1568 } 1569 1570 unsigned int mpic_get_coreint_irq(void) 1571 { 1572 #ifdef CONFIG_BOOKE 1573 struct mpic *mpic = mpic_primary; 1574 u32 src; 1575 1576 BUG_ON(mpic == NULL); 1577 1578 src = mfspr(SPRN_EPR); 1579 1580 if (unlikely(src == mpic->spurious_vec)) { 1581 if (mpic->flags & MPIC_SPV_EOI) 1582 mpic_eoi(mpic); 1583 return NO_IRQ; 1584 } 1585 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { 1586 if (printk_ratelimit()) 1587 printk(KERN_WARNING "%s: Got protected source %d !\n", 1588 mpic->name, (int)src); 1589 return NO_IRQ; 1590 } 1591 1592 return irq_linear_revmap(mpic->irqhost, src); 1593 #else 1594 return NO_IRQ; 1595 #endif 1596 } 1597 1598 unsigned int mpic_get_mcirq(void) 1599 { 1600 struct mpic *mpic = mpic_primary; 1601 1602 BUG_ON(mpic == NULL); 1603 1604 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); 1605 } 1606 1607 #ifdef CONFIG_SMP 1608 void mpic_request_ipis(void) 1609 { 1610 struct mpic *mpic = mpic_primary; 1611 int i; 1612 BUG_ON(mpic == NULL); 1613 1614 printk(KERN_INFO "mpic: requesting IPIs...\n"); 1615 1616 for (i = 0; i < 4; i++) { 1617 unsigned int vipi = irq_create_mapping(mpic->irqhost, 1618 mpic->ipi_vecs[0] + i); 1619 if (vipi == NO_IRQ) { 1620 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]); 1621 continue; 1622 } 1623 smp_request_message_ipi(vipi, i); 1624 } 1625 } 1626 1627 static void mpic_send_ipi(unsigned int ipi_no, const struct cpumask *cpu_mask) 1628 { 1629 struct mpic *mpic = mpic_primary; 1630 1631 BUG_ON(mpic == NULL); 1632 1633 #ifdef DEBUG_IPI 1634 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); 1635 #endif 1636 1637 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + 1638 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), 1639 mpic_physmask(cpumask_bits(cpu_mask)[0])); 1640 } 1641 1642 void smp_mpic_message_pass(int target, int msg) 1643 { 1644 cpumask_var_t tmp; 1645 1646 /* make sure we're sending something that translates to an IPI */ 1647 if ((unsigned int)msg > 3) { 1648 printk("SMP %d: smp_message_pass: unknown msg %d\n", 1649 smp_processor_id(), msg); 1650 return; 1651 } 1652 switch (target) { 1653 case MSG_ALL: 1654 mpic_send_ipi(msg, cpu_online_mask); 1655 break; 1656 case MSG_ALL_BUT_SELF: 1657 alloc_cpumask_var(&tmp, GFP_NOWAIT); 1658 cpumask_andnot(tmp, cpu_online_mask, 1659 cpumask_of(smp_processor_id())); 1660 mpic_send_ipi(msg, tmp); 1661 free_cpumask_var(tmp); 1662 break; 1663 default: 1664 mpic_send_ipi(msg, cpumask_of(target)); 1665 break; 1666 } 1667 } 1668 1669 int __init smp_mpic_probe(void) 1670 { 1671 int nr_cpus; 1672 1673 DBG("smp_mpic_probe()...\n"); 1674 1675 nr_cpus = cpumask_weight(cpu_possible_mask); 1676 1677 DBG("nr_cpus: %d\n", nr_cpus); 1678 1679 if (nr_cpus > 1) 1680 mpic_request_ipis(); 1681 1682 return nr_cpus; 1683 } 1684 1685 void __devinit smp_mpic_setup_cpu(int cpu) 1686 { 1687 mpic_setup_this_cpu(); 1688 } 1689 1690 void mpic_reset_core(int cpu) 1691 { 1692 struct mpic *mpic = mpic_primary; 1693 u32 pir; 1694 int cpuid = get_hard_smp_processor_id(cpu); 1695 1696 /* Set target bit for core reset */ 1697 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); 1698 pir |= (1 << cpuid); 1699 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); 1700 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); 1701 1702 /* Restore target bit after reset complete */ 1703 pir &= ~(1 << cpuid); 1704 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); 1705 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); 1706 } 1707 #endif /* CONFIG_SMP */ 1708 1709 #ifdef CONFIG_PM 1710 static int mpic_suspend(struct sys_device *dev, pm_message_t state) 1711 { 1712 struct mpic *mpic = container_of(dev, struct mpic, sysdev); 1713 int i; 1714 1715 for (i = 0; i < mpic->num_sources; i++) { 1716 mpic->save_data[i].vecprio = 1717 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); 1718 mpic->save_data[i].dest = 1719 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); 1720 } 1721 1722 return 0; 1723 } 1724 1725 static int mpic_resume(struct sys_device *dev) 1726 { 1727 struct mpic *mpic = container_of(dev, struct mpic, sysdev); 1728 int i; 1729 1730 for (i = 0; i < mpic->num_sources; i++) { 1731 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), 1732 mpic->save_data[i].vecprio); 1733 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1734 mpic->save_data[i].dest); 1735 1736 #ifdef CONFIG_MPIC_U3_HT_IRQS 1737 if (mpic->fixups) { 1738 struct mpic_irq_fixup *fixup = &mpic->fixups[i]; 1739 1740 if (fixup->base) { 1741 /* we use the lowest bit in an inverted meaning */ 1742 if ((mpic->save_data[i].fixup_data & 1) == 0) 1743 continue; 1744 1745 /* Enable and configure */ 1746 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 1747 1748 writel(mpic->save_data[i].fixup_data & ~1, 1749 fixup->base + 4); 1750 } 1751 } 1752 #endif 1753 } /* end for loop */ 1754 1755 return 0; 1756 } 1757 #endif 1758 1759 static struct sysdev_class mpic_sysclass = { 1760 #ifdef CONFIG_PM 1761 .resume = mpic_resume, 1762 .suspend = mpic_suspend, 1763 #endif 1764 .name = "mpic", 1765 }; 1766 1767 static int mpic_init_sys(void) 1768 { 1769 struct mpic *mpic = mpics; 1770 int error, id = 0; 1771 1772 error = sysdev_class_register(&mpic_sysclass); 1773 1774 while (mpic && !error) { 1775 mpic->sysdev.cls = &mpic_sysclass; 1776 mpic->sysdev.id = id++; 1777 error = sysdev_register(&mpic->sysdev); 1778 mpic = mpic->next; 1779 } 1780 return error; 1781 } 1782 1783 device_initcall(mpic_init_sys); 1784