1 /* 2 * arch/powerpc/kernel/mpic.c 3 * 4 * Driver for interrupt controllers following the OpenPIC standard, the 5 * common implementation beeing IBM's MPIC. This driver also can deal 6 * with various broken implementations of this HW. 7 * 8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file COPYING in the main directory of this archive 12 * for more details. 13 */ 14 15 #undef DEBUG 16 #undef DEBUG_IPI 17 #undef DEBUG_IRQ 18 #undef DEBUG_LOW 19 20 #include <linux/types.h> 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/irq.h> 24 #include <linux/smp.h> 25 #include <linux/interrupt.h> 26 #include <linux/bootmem.h> 27 #include <linux/spinlock.h> 28 #include <linux/pci.h> 29 30 #include <asm/ptrace.h> 31 #include <asm/signal.h> 32 #include <asm/io.h> 33 #include <asm/pgtable.h> 34 #include <asm/irq.h> 35 #include <asm/machdep.h> 36 #include <asm/mpic.h> 37 #include <asm/smp.h> 38 39 #include "mpic.h" 40 41 #ifdef DEBUG 42 #define DBG(fmt...) printk(fmt) 43 #else 44 #define DBG(fmt...) 45 #endif 46 47 static struct mpic *mpics; 48 static struct mpic *mpic_primary; 49 static DEFINE_SPINLOCK(mpic_lock); 50 51 #ifdef CONFIG_PPC32 /* XXX for now */ 52 #ifdef CONFIG_IRQ_ALL_CPUS 53 #define distribute_irqs (1) 54 #else 55 #define distribute_irqs (0) 56 #endif 57 #endif 58 59 #ifdef CONFIG_MPIC_WEIRD 60 static u32 mpic_infos[][MPIC_IDX_END] = { 61 [0] = { /* Original OpenPIC compatible MPIC */ 62 MPIC_GREG_BASE, 63 MPIC_GREG_FEATURE_0, 64 MPIC_GREG_GLOBAL_CONF_0, 65 MPIC_GREG_VENDOR_ID, 66 MPIC_GREG_IPI_VECTOR_PRI_0, 67 MPIC_GREG_IPI_STRIDE, 68 MPIC_GREG_SPURIOUS, 69 MPIC_GREG_TIMER_FREQ, 70 71 MPIC_TIMER_BASE, 72 MPIC_TIMER_STRIDE, 73 MPIC_TIMER_CURRENT_CNT, 74 MPIC_TIMER_BASE_CNT, 75 MPIC_TIMER_VECTOR_PRI, 76 MPIC_TIMER_DESTINATION, 77 78 MPIC_CPU_BASE, 79 MPIC_CPU_STRIDE, 80 MPIC_CPU_IPI_DISPATCH_0, 81 MPIC_CPU_IPI_DISPATCH_STRIDE, 82 MPIC_CPU_CURRENT_TASK_PRI, 83 MPIC_CPU_WHOAMI, 84 MPIC_CPU_INTACK, 85 MPIC_CPU_EOI, 86 87 MPIC_IRQ_BASE, 88 MPIC_IRQ_STRIDE, 89 MPIC_IRQ_VECTOR_PRI, 90 MPIC_VECPRI_VECTOR_MASK, 91 MPIC_VECPRI_POLARITY_POSITIVE, 92 MPIC_VECPRI_POLARITY_NEGATIVE, 93 MPIC_VECPRI_SENSE_LEVEL, 94 MPIC_VECPRI_SENSE_EDGE, 95 MPIC_VECPRI_POLARITY_MASK, 96 MPIC_VECPRI_SENSE_MASK, 97 MPIC_IRQ_DESTINATION 98 }, 99 [1] = { /* Tsi108/109 PIC */ 100 TSI108_GREG_BASE, 101 TSI108_GREG_FEATURE_0, 102 TSI108_GREG_GLOBAL_CONF_0, 103 TSI108_GREG_VENDOR_ID, 104 TSI108_GREG_IPI_VECTOR_PRI_0, 105 TSI108_GREG_IPI_STRIDE, 106 TSI108_GREG_SPURIOUS, 107 TSI108_GREG_TIMER_FREQ, 108 109 TSI108_TIMER_BASE, 110 TSI108_TIMER_STRIDE, 111 TSI108_TIMER_CURRENT_CNT, 112 TSI108_TIMER_BASE_CNT, 113 TSI108_TIMER_VECTOR_PRI, 114 TSI108_TIMER_DESTINATION, 115 116 TSI108_CPU_BASE, 117 TSI108_CPU_STRIDE, 118 TSI108_CPU_IPI_DISPATCH_0, 119 TSI108_CPU_IPI_DISPATCH_STRIDE, 120 TSI108_CPU_CURRENT_TASK_PRI, 121 TSI108_CPU_WHOAMI, 122 TSI108_CPU_INTACK, 123 TSI108_CPU_EOI, 124 125 TSI108_IRQ_BASE, 126 TSI108_IRQ_STRIDE, 127 TSI108_IRQ_VECTOR_PRI, 128 TSI108_VECPRI_VECTOR_MASK, 129 TSI108_VECPRI_POLARITY_POSITIVE, 130 TSI108_VECPRI_POLARITY_NEGATIVE, 131 TSI108_VECPRI_SENSE_LEVEL, 132 TSI108_VECPRI_SENSE_EDGE, 133 TSI108_VECPRI_POLARITY_MASK, 134 TSI108_VECPRI_SENSE_MASK, 135 TSI108_IRQ_DESTINATION 136 }, 137 }; 138 139 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] 140 141 #else /* CONFIG_MPIC_WEIRD */ 142 143 #define MPIC_INFO(name) MPIC_##name 144 145 #endif /* CONFIG_MPIC_WEIRD */ 146 147 /* 148 * Register accessor functions 149 */ 150 151 152 static inline u32 _mpic_read(enum mpic_reg_type type, 153 struct mpic_reg_bank *rb, 154 unsigned int reg) 155 { 156 switch(type) { 157 #ifdef CONFIG_PPC_DCR 158 case mpic_access_dcr: 159 return dcr_read(rb->dhost, 160 rb->dbase + reg + rb->doff); 161 #endif 162 case mpic_access_mmio_be: 163 return in_be32(rb->base + (reg >> 2)); 164 case mpic_access_mmio_le: 165 default: 166 return in_le32(rb->base + (reg >> 2)); 167 } 168 } 169 170 static inline void _mpic_write(enum mpic_reg_type type, 171 struct mpic_reg_bank *rb, 172 unsigned int reg, u32 value) 173 { 174 switch(type) { 175 #ifdef CONFIG_PPC_DCR 176 case mpic_access_dcr: 177 return dcr_write(rb->dhost, 178 rb->dbase + reg + rb->doff, value); 179 #endif 180 case mpic_access_mmio_be: 181 return out_be32(rb->base + (reg >> 2), value); 182 case mpic_access_mmio_le: 183 default: 184 return out_le32(rb->base + (reg >> 2), value); 185 } 186 } 187 188 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) 189 { 190 enum mpic_reg_type type = mpic->reg_type; 191 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 192 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 193 194 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) 195 type = mpic_access_mmio_be; 196 return _mpic_read(type, &mpic->gregs, offset); 197 } 198 199 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) 200 { 201 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 202 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 203 204 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); 205 } 206 207 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) 208 { 209 unsigned int cpu = 0; 210 211 if (mpic->flags & MPIC_PRIMARY) 212 cpu = hard_smp_processor_id(); 213 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); 214 } 215 216 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) 217 { 218 unsigned int cpu = 0; 219 220 if (mpic->flags & MPIC_PRIMARY) 221 cpu = hard_smp_processor_id(); 222 223 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); 224 } 225 226 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) 227 { 228 unsigned int isu = src_no >> mpic->isu_shift; 229 unsigned int idx = src_no & mpic->isu_mask; 230 231 return _mpic_read(mpic->reg_type, &mpic->isus[isu], 232 reg + (idx * MPIC_INFO(IRQ_STRIDE))); 233 } 234 235 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, 236 unsigned int reg, u32 value) 237 { 238 unsigned int isu = src_no >> mpic->isu_shift; 239 unsigned int idx = src_no & mpic->isu_mask; 240 241 _mpic_write(mpic->reg_type, &mpic->isus[isu], 242 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); 243 } 244 245 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) 246 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) 247 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) 248 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) 249 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) 250 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) 251 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) 252 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) 253 254 255 /* 256 * Low level utility functions 257 */ 258 259 260 static void _mpic_map_mmio(struct mpic *mpic, unsigned long phys_addr, 261 struct mpic_reg_bank *rb, unsigned int offset, 262 unsigned int size) 263 { 264 rb->base = ioremap(phys_addr + offset, size); 265 BUG_ON(rb->base == NULL); 266 } 267 268 #ifdef CONFIG_PPC_DCR 269 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, 270 unsigned int offset, unsigned int size) 271 { 272 rb->dbase = mpic->dcr_base; 273 rb->doff = offset; 274 rb->dhost = dcr_map(mpic->irqhost->of_node, rb->dbase + rb->doff, size); 275 BUG_ON(!DCR_MAP_OK(rb->dhost)); 276 } 277 278 static inline void mpic_map(struct mpic *mpic, unsigned long phys_addr, 279 struct mpic_reg_bank *rb, unsigned int offset, 280 unsigned int size) 281 { 282 if (mpic->flags & MPIC_USES_DCR) 283 _mpic_map_dcr(mpic, rb, offset, size); 284 else 285 _mpic_map_mmio(mpic, phys_addr, rb, offset, size); 286 } 287 #else /* CONFIG_PPC_DCR */ 288 #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) 289 #endif /* !CONFIG_PPC_DCR */ 290 291 292 293 /* Check if we have one of those nice broken MPICs with a flipped endian on 294 * reads from IPI registers 295 */ 296 static void __init mpic_test_broken_ipi(struct mpic *mpic) 297 { 298 u32 r; 299 300 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); 301 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); 302 303 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { 304 printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); 305 mpic->flags |= MPIC_BROKEN_IPI; 306 } 307 } 308 309 #ifdef CONFIG_MPIC_U3_HT_IRQS 310 311 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) 312 * to force the edge setting on the MPIC and do the ack workaround. 313 */ 314 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 315 { 316 if (source >= 128 || !mpic->fixups) 317 return 0; 318 return mpic->fixups[source].base != NULL; 319 } 320 321 322 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) 323 { 324 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 325 326 if (fixup->applebase) { 327 unsigned int soff = (fixup->index >> 3) & ~3; 328 unsigned int mask = 1U << (fixup->index & 0x1f); 329 writel(mask, fixup->applebase + soff); 330 } else { 331 spin_lock(&mpic->fixup_lock); 332 writeb(0x11 + 2 * fixup->index, fixup->base + 2); 333 writel(fixup->data, fixup->base + 4); 334 spin_unlock(&mpic->fixup_lock); 335 } 336 } 337 338 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, 339 unsigned int irqflags) 340 { 341 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 342 unsigned long flags; 343 u32 tmp; 344 345 if (fixup->base == NULL) 346 return; 347 348 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n", 349 source, irqflags, fixup->index); 350 spin_lock_irqsave(&mpic->fixup_lock, flags); 351 /* Enable and configure */ 352 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 353 tmp = readl(fixup->base + 4); 354 tmp &= ~(0x23U); 355 if (irqflags & IRQ_LEVEL) 356 tmp |= 0x22; 357 writel(tmp, fixup->base + 4); 358 spin_unlock_irqrestore(&mpic->fixup_lock, flags); 359 360 #ifdef CONFIG_PM 361 /* use the lowest bit inverted to the actual HW, 362 * set if this fixup was enabled, clear otherwise */ 363 mpic->save_data[source].fixup_data = tmp | 1; 364 #endif 365 } 366 367 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, 368 unsigned int irqflags) 369 { 370 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 371 unsigned long flags; 372 u32 tmp; 373 374 if (fixup->base == NULL) 375 return; 376 377 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags); 378 379 /* Disable */ 380 spin_lock_irqsave(&mpic->fixup_lock, flags); 381 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 382 tmp = readl(fixup->base + 4); 383 tmp |= 1; 384 writel(tmp, fixup->base + 4); 385 spin_unlock_irqrestore(&mpic->fixup_lock, flags); 386 387 #ifdef CONFIG_PM 388 /* use the lowest bit inverted to the actual HW, 389 * set if this fixup was enabled, clear otherwise */ 390 mpic->save_data[source].fixup_data = tmp & ~1; 391 #endif 392 } 393 394 #ifdef CONFIG_PCI_MSI 395 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, 396 unsigned int devfn) 397 { 398 u8 __iomem *base; 399 u8 pos, flags; 400 u64 addr = 0; 401 402 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 403 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 404 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 405 if (id == PCI_CAP_ID_HT) { 406 id = readb(devbase + pos + 3); 407 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) 408 break; 409 } 410 } 411 412 if (pos == 0) 413 return; 414 415 base = devbase + pos; 416 417 flags = readb(base + HT_MSI_FLAGS); 418 if (!(flags & HT_MSI_FLAGS_FIXED)) { 419 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; 420 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); 421 } 422 423 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%lx\n", 424 PCI_SLOT(devfn), PCI_FUNC(devfn), 425 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); 426 427 if (!(flags & HT_MSI_FLAGS_ENABLE)) 428 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); 429 } 430 #else 431 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, 432 unsigned int devfn) 433 { 434 return; 435 } 436 #endif 437 438 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, 439 unsigned int devfn, u32 vdid) 440 { 441 int i, irq, n; 442 u8 __iomem *base; 443 u32 tmp; 444 u8 pos; 445 446 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 447 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 448 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 449 if (id == PCI_CAP_ID_HT) { 450 id = readb(devbase + pos + 3); 451 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) 452 break; 453 } 454 } 455 if (pos == 0) 456 return; 457 458 base = devbase + pos; 459 writeb(0x01, base + 2); 460 n = (readl(base + 4) >> 16) & 0xff; 461 462 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" 463 " has %d irqs\n", 464 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); 465 466 for (i = 0; i <= n; i++) { 467 writeb(0x10 + 2 * i, base + 2); 468 tmp = readl(base + 4); 469 irq = (tmp >> 16) & 0xff; 470 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); 471 /* mask it , will be unmasked later */ 472 tmp |= 0x1; 473 writel(tmp, base + 4); 474 mpic->fixups[irq].index = i; 475 mpic->fixups[irq].base = base; 476 /* Apple HT PIC has a non-standard way of doing EOIs */ 477 if ((vdid & 0xffff) == 0x106b) 478 mpic->fixups[irq].applebase = devbase + 0x60; 479 else 480 mpic->fixups[irq].applebase = NULL; 481 writeb(0x11 + 2 * i, base + 2); 482 mpic->fixups[irq].data = readl(base + 4) | 0x80000000; 483 } 484 } 485 486 487 static void __init mpic_scan_ht_pics(struct mpic *mpic) 488 { 489 unsigned int devfn; 490 u8 __iomem *cfgspace; 491 492 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); 493 494 /* Allocate fixups array */ 495 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup)); 496 BUG_ON(mpic->fixups == NULL); 497 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup)); 498 499 /* Init spinlock */ 500 spin_lock_init(&mpic->fixup_lock); 501 502 /* Map U3 config space. We assume all IO-APICs are on the primary bus 503 * so we only need to map 64kB. 504 */ 505 cfgspace = ioremap(0xf2000000, 0x10000); 506 BUG_ON(cfgspace == NULL); 507 508 /* Now we scan all slots. We do a very quick scan, we read the header 509 * type, vendor ID and device ID only, that's plenty enough 510 */ 511 for (devfn = 0; devfn < 0x100; devfn++) { 512 u8 __iomem *devbase = cfgspace + (devfn << 8); 513 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); 514 u32 l = readl(devbase + PCI_VENDOR_ID); 515 u16 s; 516 517 DBG("devfn %x, l: %x\n", devfn, l); 518 519 /* If no device, skip */ 520 if (l == 0xffffffff || l == 0x00000000 || 521 l == 0x0000ffff || l == 0xffff0000) 522 goto next; 523 /* Check if is supports capability lists */ 524 s = readw(devbase + PCI_STATUS); 525 if (!(s & PCI_STATUS_CAP_LIST)) 526 goto next; 527 528 mpic_scan_ht_pic(mpic, devbase, devfn, l); 529 mpic_scan_ht_msi(mpic, devbase, devfn); 530 531 next: 532 /* next device, if function 0 */ 533 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) 534 devfn += 7; 535 } 536 } 537 538 #else /* CONFIG_MPIC_U3_HT_IRQS */ 539 540 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 541 { 542 return 0; 543 } 544 545 static void __init mpic_scan_ht_pics(struct mpic *mpic) 546 { 547 } 548 549 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 550 551 552 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) 553 554 /* Find an mpic associated with a given linux interrupt */ 555 static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi) 556 { 557 unsigned int src = mpic_irq_to_hw(irq); 558 struct mpic *mpic; 559 560 if (irq < NUM_ISA_INTERRUPTS) 561 return NULL; 562 563 mpic = irq_desc[irq].chip_data; 564 565 if (is_ipi) 566 *is_ipi = (src >= mpic->ipi_vecs[0] && 567 src <= mpic->ipi_vecs[3]); 568 569 return mpic; 570 } 571 572 /* Convert a cpu mask from logical to physical cpu numbers. */ 573 static inline u32 mpic_physmask(u32 cpumask) 574 { 575 int i; 576 u32 mask = 0; 577 578 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1) 579 mask |= (cpumask & 1) << get_hard_smp_processor_id(i); 580 return mask; 581 } 582 583 #ifdef CONFIG_SMP 584 /* Get the mpic structure from the IPI number */ 585 static inline struct mpic * mpic_from_ipi(unsigned int ipi) 586 { 587 return irq_desc[ipi].chip_data; 588 } 589 #endif 590 591 /* Get the mpic structure from the irq number */ 592 static inline struct mpic * mpic_from_irq(unsigned int irq) 593 { 594 return irq_desc[irq].chip_data; 595 } 596 597 /* Send an EOI */ 598 static inline void mpic_eoi(struct mpic *mpic) 599 { 600 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); 601 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); 602 } 603 604 #ifdef CONFIG_SMP 605 static irqreturn_t mpic_ipi_action(int irq, void *dev_id) 606 { 607 struct mpic *mpic; 608 609 mpic = mpic_find(irq, NULL); 610 smp_message_recv(mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]); 611 612 return IRQ_HANDLED; 613 } 614 #endif /* CONFIG_SMP */ 615 616 /* 617 * Linux descriptor level callbacks 618 */ 619 620 621 void mpic_unmask_irq(unsigned int irq) 622 { 623 unsigned int loops = 100000; 624 struct mpic *mpic = mpic_from_irq(irq); 625 unsigned int src = mpic_irq_to_hw(irq); 626 627 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src); 628 629 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 630 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & 631 ~MPIC_VECPRI_MASK); 632 /* make sure mask gets to controller before we return to user */ 633 do { 634 if (!loops--) { 635 printk(KERN_ERR "mpic_enable_irq timeout\n"); 636 break; 637 } 638 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); 639 } 640 641 void mpic_mask_irq(unsigned int irq) 642 { 643 unsigned int loops = 100000; 644 struct mpic *mpic = mpic_from_irq(irq); 645 unsigned int src = mpic_irq_to_hw(irq); 646 647 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); 648 649 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 650 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | 651 MPIC_VECPRI_MASK); 652 653 /* make sure mask gets to controller before we return to user */ 654 do { 655 if (!loops--) { 656 printk(KERN_ERR "mpic_enable_irq timeout\n"); 657 break; 658 } 659 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); 660 } 661 662 void mpic_end_irq(unsigned int irq) 663 { 664 struct mpic *mpic = mpic_from_irq(irq); 665 666 #ifdef DEBUG_IRQ 667 DBG("%s: end_irq: %d\n", mpic->name, irq); 668 #endif 669 /* We always EOI on end_irq() even for edge interrupts since that 670 * should only lower the priority, the MPIC should have properly 671 * latched another edge interrupt coming in anyway 672 */ 673 674 mpic_eoi(mpic); 675 } 676 677 #ifdef CONFIG_MPIC_U3_HT_IRQS 678 679 static void mpic_unmask_ht_irq(unsigned int irq) 680 { 681 struct mpic *mpic = mpic_from_irq(irq); 682 unsigned int src = mpic_irq_to_hw(irq); 683 684 mpic_unmask_irq(irq); 685 686 if (irq_desc[irq].status & IRQ_LEVEL) 687 mpic_ht_end_irq(mpic, src); 688 } 689 690 static unsigned int mpic_startup_ht_irq(unsigned int irq) 691 { 692 struct mpic *mpic = mpic_from_irq(irq); 693 unsigned int src = mpic_irq_to_hw(irq); 694 695 mpic_unmask_irq(irq); 696 mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status); 697 698 return 0; 699 } 700 701 static void mpic_shutdown_ht_irq(unsigned int irq) 702 { 703 struct mpic *mpic = mpic_from_irq(irq); 704 unsigned int src = mpic_irq_to_hw(irq); 705 706 mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status); 707 mpic_mask_irq(irq); 708 } 709 710 static void mpic_end_ht_irq(unsigned int irq) 711 { 712 struct mpic *mpic = mpic_from_irq(irq); 713 unsigned int src = mpic_irq_to_hw(irq); 714 715 #ifdef DEBUG_IRQ 716 DBG("%s: end_irq: %d\n", mpic->name, irq); 717 #endif 718 /* We always EOI on end_irq() even for edge interrupts since that 719 * should only lower the priority, the MPIC should have properly 720 * latched another edge interrupt coming in anyway 721 */ 722 723 if (irq_desc[irq].status & IRQ_LEVEL) 724 mpic_ht_end_irq(mpic, src); 725 mpic_eoi(mpic); 726 } 727 #endif /* !CONFIG_MPIC_U3_HT_IRQS */ 728 729 #ifdef CONFIG_SMP 730 731 static void mpic_unmask_ipi(unsigned int irq) 732 { 733 struct mpic *mpic = mpic_from_ipi(irq); 734 unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]; 735 736 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src); 737 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); 738 } 739 740 static void mpic_mask_ipi(unsigned int irq) 741 { 742 /* NEVER disable an IPI... that's just plain wrong! */ 743 } 744 745 static void mpic_end_ipi(unsigned int irq) 746 { 747 struct mpic *mpic = mpic_from_ipi(irq); 748 749 /* 750 * IPIs are marked IRQ_PER_CPU. This has the side effect of 751 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from 752 * applying to them. We EOI them late to avoid re-entering. 753 * We mark IPI's with IRQF_DISABLED as they must run with 754 * irqs disabled. 755 */ 756 mpic_eoi(mpic); 757 } 758 759 #endif /* CONFIG_SMP */ 760 761 static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask) 762 { 763 struct mpic *mpic = mpic_from_irq(irq); 764 unsigned int src = mpic_irq_to_hw(irq); 765 766 cpumask_t tmp; 767 768 cpus_and(tmp, cpumask, cpu_online_map); 769 770 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 771 mpic_physmask(cpus_addr(tmp)[0])); 772 } 773 774 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) 775 { 776 /* Now convert sense value */ 777 switch(type & IRQ_TYPE_SENSE_MASK) { 778 case IRQ_TYPE_EDGE_RISING: 779 return MPIC_INFO(VECPRI_SENSE_EDGE) | 780 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 781 case IRQ_TYPE_EDGE_FALLING: 782 case IRQ_TYPE_EDGE_BOTH: 783 return MPIC_INFO(VECPRI_SENSE_EDGE) | 784 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 785 case IRQ_TYPE_LEVEL_HIGH: 786 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 787 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 788 case IRQ_TYPE_LEVEL_LOW: 789 default: 790 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 791 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 792 } 793 } 794 795 int mpic_set_irq_type(unsigned int virq, unsigned int flow_type) 796 { 797 struct mpic *mpic = mpic_from_irq(virq); 798 unsigned int src = mpic_irq_to_hw(virq); 799 struct irq_desc *desc = get_irq_desc(virq); 800 unsigned int vecpri, vold, vnew; 801 802 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", 803 mpic, virq, src, flow_type); 804 805 if (src >= mpic->irq_count) 806 return -EINVAL; 807 808 if (flow_type == IRQ_TYPE_NONE) 809 if (mpic->senses && src < mpic->senses_count) 810 flow_type = mpic->senses[src]; 811 if (flow_type == IRQ_TYPE_NONE) 812 flow_type = IRQ_TYPE_LEVEL_LOW; 813 814 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 815 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; 816 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 817 desc->status |= IRQ_LEVEL; 818 819 if (mpic_is_ht_interrupt(mpic, src)) 820 vecpri = MPIC_VECPRI_POLARITY_POSITIVE | 821 MPIC_VECPRI_SENSE_EDGE; 822 else 823 vecpri = mpic_type_to_vecpri(mpic, flow_type); 824 825 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 826 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | 827 MPIC_INFO(VECPRI_SENSE_MASK)); 828 vnew |= vecpri; 829 if (vold != vnew) 830 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); 831 832 return 0; 833 } 834 835 static struct irq_chip mpic_irq_chip = { 836 .mask = mpic_mask_irq, 837 .unmask = mpic_unmask_irq, 838 .eoi = mpic_end_irq, 839 .set_type = mpic_set_irq_type, 840 }; 841 842 #ifdef CONFIG_SMP 843 static struct irq_chip mpic_ipi_chip = { 844 .mask = mpic_mask_ipi, 845 .unmask = mpic_unmask_ipi, 846 .eoi = mpic_end_ipi, 847 }; 848 #endif /* CONFIG_SMP */ 849 850 #ifdef CONFIG_MPIC_U3_HT_IRQS 851 static struct irq_chip mpic_irq_ht_chip = { 852 .startup = mpic_startup_ht_irq, 853 .shutdown = mpic_shutdown_ht_irq, 854 .mask = mpic_mask_irq, 855 .unmask = mpic_unmask_ht_irq, 856 .eoi = mpic_end_ht_irq, 857 .set_type = mpic_set_irq_type, 858 }; 859 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 860 861 862 static int mpic_host_match(struct irq_host *h, struct device_node *node) 863 { 864 /* Exact match, unless mpic node is NULL */ 865 return h->of_node == NULL || h->of_node == node; 866 } 867 868 static int mpic_host_map(struct irq_host *h, unsigned int virq, 869 irq_hw_number_t hw) 870 { 871 struct mpic *mpic = h->host_data; 872 struct irq_chip *chip; 873 874 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); 875 876 if (hw == mpic->spurious_vec) 877 return -EINVAL; 878 if (mpic->protected && test_bit(hw, mpic->protected)) 879 return -EINVAL; 880 881 #ifdef CONFIG_SMP 882 else if (hw >= mpic->ipi_vecs[0]) { 883 WARN_ON(!(mpic->flags & MPIC_PRIMARY)); 884 885 DBG("mpic: mapping as IPI\n"); 886 set_irq_chip_data(virq, mpic); 887 set_irq_chip_and_handler(virq, &mpic->hc_ipi, 888 handle_percpu_irq); 889 return 0; 890 } 891 #endif /* CONFIG_SMP */ 892 893 if (hw >= mpic->irq_count) 894 return -EINVAL; 895 896 mpic_msi_reserve_hwirq(mpic, hw); 897 898 /* Default chip */ 899 chip = &mpic->hc_irq; 900 901 #ifdef CONFIG_MPIC_U3_HT_IRQS 902 /* Check for HT interrupts, override vecpri */ 903 if (mpic_is_ht_interrupt(mpic, hw)) 904 chip = &mpic->hc_ht_irq; 905 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 906 907 DBG("mpic: mapping to irq chip @%p\n", chip); 908 909 set_irq_chip_data(virq, mpic); 910 set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq); 911 912 /* Set default irq type */ 913 set_irq_type(virq, IRQ_TYPE_NONE); 914 915 return 0; 916 } 917 918 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, 919 u32 *intspec, unsigned int intsize, 920 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 921 922 { 923 static unsigned char map_mpic_senses[4] = { 924 IRQ_TYPE_EDGE_RISING, 925 IRQ_TYPE_LEVEL_LOW, 926 IRQ_TYPE_LEVEL_HIGH, 927 IRQ_TYPE_EDGE_FALLING, 928 }; 929 930 *out_hwirq = intspec[0]; 931 if (intsize > 1) { 932 u32 mask = 0x3; 933 934 /* Apple invented a new race of encoding on machines with 935 * an HT APIC. They encode, among others, the index within 936 * the HT APIC. We don't care about it here since thankfully, 937 * it appears that they have the APIC already properly 938 * configured, and thus our current fixup code that reads the 939 * APIC config works fine. However, we still need to mask out 940 * bits in the specifier to make sure we only get bit 0 which 941 * is the level/edge bit (the only sense bit exposed by Apple), 942 * as their bit 1 means something else. 943 */ 944 if (machine_is(powermac)) 945 mask = 0x1; 946 *out_flags = map_mpic_senses[intspec[1] & mask]; 947 } else 948 *out_flags = IRQ_TYPE_NONE; 949 950 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", 951 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); 952 953 return 0; 954 } 955 956 static struct irq_host_ops mpic_host_ops = { 957 .match = mpic_host_match, 958 .map = mpic_host_map, 959 .xlate = mpic_host_xlate, 960 }; 961 962 /* 963 * Exported functions 964 */ 965 966 struct mpic * __init mpic_alloc(struct device_node *node, 967 phys_addr_t phys_addr, 968 unsigned int flags, 969 unsigned int isu_size, 970 unsigned int irq_count, 971 const char *name) 972 { 973 struct mpic *mpic; 974 u32 reg; 975 const char *vers; 976 int i; 977 int intvec_top; 978 u64 paddr = phys_addr; 979 980 mpic = alloc_bootmem(sizeof(struct mpic)); 981 if (mpic == NULL) 982 return NULL; 983 984 memset(mpic, 0, sizeof(struct mpic)); 985 mpic->name = name; 986 987 mpic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR, 988 isu_size, &mpic_host_ops, 989 flags & MPIC_LARGE_VECTORS ? 2048 : 256); 990 if (mpic->irqhost == NULL) { 991 of_node_put(node); 992 return NULL; 993 } 994 995 mpic->irqhost->host_data = mpic; 996 mpic->hc_irq = mpic_irq_chip; 997 mpic->hc_irq.typename = name; 998 if (flags & MPIC_PRIMARY) 999 mpic->hc_irq.set_affinity = mpic_set_affinity; 1000 #ifdef CONFIG_MPIC_U3_HT_IRQS 1001 mpic->hc_ht_irq = mpic_irq_ht_chip; 1002 mpic->hc_ht_irq.typename = name; 1003 if (flags & MPIC_PRIMARY) 1004 mpic->hc_ht_irq.set_affinity = mpic_set_affinity; 1005 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 1006 1007 #ifdef CONFIG_SMP 1008 mpic->hc_ipi = mpic_ipi_chip; 1009 mpic->hc_ipi.typename = name; 1010 #endif /* CONFIG_SMP */ 1011 1012 mpic->flags = flags; 1013 mpic->isu_size = isu_size; 1014 mpic->irq_count = irq_count; 1015 mpic->num_sources = 0; /* so far */ 1016 1017 if (flags & MPIC_LARGE_VECTORS) 1018 intvec_top = 2047; 1019 else 1020 intvec_top = 255; 1021 1022 mpic->timer_vecs[0] = intvec_top - 8; 1023 mpic->timer_vecs[1] = intvec_top - 7; 1024 mpic->timer_vecs[2] = intvec_top - 6; 1025 mpic->timer_vecs[3] = intvec_top - 5; 1026 mpic->ipi_vecs[0] = intvec_top - 4; 1027 mpic->ipi_vecs[1] = intvec_top - 3; 1028 mpic->ipi_vecs[2] = intvec_top - 2; 1029 mpic->ipi_vecs[3] = intvec_top - 1; 1030 mpic->spurious_vec = intvec_top; 1031 1032 /* Check for "big-endian" in device-tree */ 1033 if (node && of_get_property(node, "big-endian", NULL) != NULL) 1034 mpic->flags |= MPIC_BIG_ENDIAN; 1035 1036 /* Look for protected sources */ 1037 if (node) { 1038 unsigned int psize, bits, mapsize; 1039 const u32 *psrc = 1040 of_get_property(node, "protected-sources", &psize); 1041 if (psrc) { 1042 psize /= 4; 1043 bits = intvec_top + 1; 1044 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long); 1045 mpic->protected = alloc_bootmem(mapsize); 1046 BUG_ON(mpic->protected == NULL); 1047 memset(mpic->protected, 0, mapsize); 1048 for (i = 0; i < psize; i++) { 1049 if (psrc[i] > intvec_top) 1050 continue; 1051 __set_bit(psrc[i], mpic->protected); 1052 } 1053 } 1054 } 1055 1056 #ifdef CONFIG_MPIC_WEIRD 1057 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)]; 1058 #endif 1059 1060 /* default register type */ 1061 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ? 1062 mpic_access_mmio_be : mpic_access_mmio_le; 1063 1064 /* If no physical address is passed in, a device-node is mandatory */ 1065 BUG_ON(paddr == 0 && node == NULL); 1066 1067 /* If no physical address passed in, check if it's dcr based */ 1068 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) 1069 mpic->flags |= MPIC_USES_DCR; 1070 1071 #ifdef CONFIG_PPC_DCR 1072 if (mpic->flags & MPIC_USES_DCR) { 1073 const u32 *dbasep; 1074 dbasep = of_get_property(node, "dcr-reg", NULL); 1075 BUG_ON(dbasep == NULL); 1076 mpic->dcr_base = *dbasep; 1077 mpic->reg_type = mpic_access_dcr; 1078 } 1079 #else 1080 BUG_ON (mpic->flags & MPIC_USES_DCR); 1081 #endif /* CONFIG_PPC_DCR */ 1082 1083 /* If the MPIC is not DCR based, and no physical address was passed 1084 * in, try to obtain one 1085 */ 1086 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) { 1087 const u32 *reg; 1088 reg = of_get_property(node, "reg", NULL); 1089 BUG_ON(reg == NULL); 1090 paddr = of_translate_address(node, reg); 1091 BUG_ON(paddr == OF_BAD_ADDR); 1092 } 1093 1094 /* Map the global registers */ 1095 mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); 1096 mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); 1097 1098 /* Reset */ 1099 if (flags & MPIC_WANTS_RESET) { 1100 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1101 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1102 | MPIC_GREG_GCONF_RESET); 1103 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1104 & MPIC_GREG_GCONF_RESET) 1105 mb(); 1106 } 1107 1108 /* Read feature register, calculate num CPUs and, for non-ISU 1109 * MPICs, num sources as well. On ISU MPICs, sources are counted 1110 * as ISUs are added 1111 */ 1112 reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); 1113 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK) 1114 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; 1115 if (isu_size == 0) 1116 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK) 1117 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; 1118 1119 /* Map the per-CPU registers */ 1120 for (i = 0; i < mpic->num_cpus; i++) { 1121 mpic_map(mpic, paddr, &mpic->cpuregs[i], 1122 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), 1123 0x1000); 1124 } 1125 1126 /* Initialize main ISU if none provided */ 1127 if (mpic->isu_size == 0) { 1128 mpic->isu_size = mpic->num_sources; 1129 mpic_map(mpic, paddr, &mpic->isus[0], 1130 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1131 } 1132 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 1133 mpic->isu_mask = (1 << mpic->isu_shift) - 1; 1134 1135 /* Display version */ 1136 switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) { 1137 case 1: 1138 vers = "1.0"; 1139 break; 1140 case 2: 1141 vers = "1.2"; 1142 break; 1143 case 3: 1144 vers = "1.3"; 1145 break; 1146 default: 1147 vers = "<unknown>"; 1148 break; 1149 } 1150 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," 1151 " max %d CPUs\n", 1152 name, vers, (unsigned long long)paddr, mpic->num_cpus); 1153 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", 1154 mpic->isu_size, mpic->isu_shift, mpic->isu_mask); 1155 1156 mpic->next = mpics; 1157 mpics = mpic; 1158 1159 if (flags & MPIC_PRIMARY) { 1160 mpic_primary = mpic; 1161 irq_set_default_host(mpic->irqhost); 1162 } 1163 1164 return mpic; 1165 } 1166 1167 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, 1168 phys_addr_t paddr) 1169 { 1170 unsigned int isu_first = isu_num * mpic->isu_size; 1171 1172 BUG_ON(isu_num >= MPIC_MAX_ISU); 1173 1174 mpic_map(mpic, paddr, &mpic->isus[isu_num], 0, 1175 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1176 if ((isu_first + mpic->isu_size) > mpic->num_sources) 1177 mpic->num_sources = isu_first + mpic->isu_size; 1178 } 1179 1180 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) 1181 { 1182 mpic->senses = senses; 1183 mpic->senses_count = count; 1184 } 1185 1186 void __init mpic_init(struct mpic *mpic) 1187 { 1188 int i; 1189 1190 BUG_ON(mpic->num_sources == 0); 1191 1192 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); 1193 1194 /* Set current processor priority to max */ 1195 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1196 1197 /* Initialize timers: just disable them all */ 1198 for (i = 0; i < 4; i++) { 1199 mpic_write(mpic->tmregs, 1200 i * MPIC_INFO(TIMER_STRIDE) + 1201 MPIC_INFO(TIMER_DESTINATION), 0); 1202 mpic_write(mpic->tmregs, 1203 i * MPIC_INFO(TIMER_STRIDE) + 1204 MPIC_INFO(TIMER_VECTOR_PRI), 1205 MPIC_VECPRI_MASK | 1206 (mpic->timer_vecs[0] + i)); 1207 } 1208 1209 /* Initialize IPIs to our reserved vectors and mark them disabled for now */ 1210 mpic_test_broken_ipi(mpic); 1211 for (i = 0; i < 4; i++) { 1212 mpic_ipi_write(i, 1213 MPIC_VECPRI_MASK | 1214 (10 << MPIC_VECPRI_PRIORITY_SHIFT) | 1215 (mpic->ipi_vecs[0] + i)); 1216 } 1217 1218 /* Initialize interrupt sources */ 1219 if (mpic->irq_count == 0) 1220 mpic->irq_count = mpic->num_sources; 1221 1222 /* Do the HT PIC fixups on U3 broken mpic */ 1223 DBG("MPIC flags: %x\n", mpic->flags); 1224 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) { 1225 mpic_scan_ht_pics(mpic); 1226 mpic_u3msi_init(mpic); 1227 } 1228 1229 for (i = 0; i < mpic->num_sources; i++) { 1230 /* start with vector = source number, and masked */ 1231 u32 vecpri = MPIC_VECPRI_MASK | i | 1232 (8 << MPIC_VECPRI_PRIORITY_SHIFT); 1233 1234 /* check if protected */ 1235 if (mpic->protected && test_bit(i, mpic->protected)) 1236 continue; 1237 /* init hw */ 1238 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 1239 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1240 1 << hard_smp_processor_id()); 1241 } 1242 1243 /* Init spurious vector */ 1244 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); 1245 1246 /* Disable 8259 passthrough, if supported */ 1247 if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) 1248 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1249 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1250 | MPIC_GREG_GCONF_8259_PTHROU_DIS); 1251 1252 /* Set current processor priority to 0 */ 1253 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 1254 1255 #ifdef CONFIG_PM 1256 /* allocate memory to save mpic state */ 1257 mpic->save_data = alloc_bootmem(mpic->num_sources * sizeof(struct mpic_irq_save)); 1258 BUG_ON(mpic->save_data == NULL); 1259 #endif 1260 } 1261 1262 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) 1263 { 1264 u32 v; 1265 1266 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1267 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; 1268 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); 1269 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1270 } 1271 1272 void __init mpic_set_serial_int(struct mpic *mpic, int enable) 1273 { 1274 unsigned long flags; 1275 u32 v; 1276 1277 spin_lock_irqsave(&mpic_lock, flags); 1278 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1279 if (enable) 1280 v |= MPIC_GREG_GLOBAL_CONF_1_SIE; 1281 else 1282 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; 1283 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1284 spin_unlock_irqrestore(&mpic_lock, flags); 1285 } 1286 1287 void mpic_irq_set_priority(unsigned int irq, unsigned int pri) 1288 { 1289 int is_ipi; 1290 struct mpic *mpic = mpic_find(irq, &is_ipi); 1291 unsigned int src = mpic_irq_to_hw(irq); 1292 unsigned long flags; 1293 u32 reg; 1294 1295 spin_lock_irqsave(&mpic_lock, flags); 1296 if (is_ipi) { 1297 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & 1298 ~MPIC_VECPRI_PRIORITY_MASK; 1299 mpic_ipi_write(src - mpic->ipi_vecs[0], 1300 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1301 } else { 1302 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) 1303 & ~MPIC_VECPRI_PRIORITY_MASK; 1304 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 1305 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1306 } 1307 spin_unlock_irqrestore(&mpic_lock, flags); 1308 } 1309 1310 unsigned int mpic_irq_get_priority(unsigned int irq) 1311 { 1312 int is_ipi; 1313 struct mpic *mpic = mpic_find(irq, &is_ipi); 1314 unsigned int src = mpic_irq_to_hw(irq); 1315 unsigned long flags; 1316 u32 reg; 1317 1318 spin_lock_irqsave(&mpic_lock, flags); 1319 if (is_ipi) 1320 reg = mpic_ipi_read(src = mpic->ipi_vecs[0]); 1321 else 1322 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 1323 spin_unlock_irqrestore(&mpic_lock, flags); 1324 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT; 1325 } 1326 1327 void mpic_setup_this_cpu(void) 1328 { 1329 #ifdef CONFIG_SMP 1330 struct mpic *mpic = mpic_primary; 1331 unsigned long flags; 1332 u32 msk = 1 << hard_smp_processor_id(); 1333 unsigned int i; 1334 1335 BUG_ON(mpic == NULL); 1336 1337 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1338 1339 spin_lock_irqsave(&mpic_lock, flags); 1340 1341 /* let the mpic know we want intrs. default affinity is 0xffffffff 1342 * until changed via /proc. That's how it's done on x86. If we want 1343 * it differently, then we should make sure we also change the default 1344 * values of irq_desc[].affinity in irq.c. 1345 */ 1346 if (distribute_irqs) { 1347 for (i = 0; i < mpic->num_sources ; i++) 1348 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1349 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); 1350 } 1351 1352 /* Set current processor priority to 0 */ 1353 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 1354 1355 spin_unlock_irqrestore(&mpic_lock, flags); 1356 #endif /* CONFIG_SMP */ 1357 } 1358 1359 int mpic_cpu_get_priority(void) 1360 { 1361 struct mpic *mpic = mpic_primary; 1362 1363 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); 1364 } 1365 1366 void mpic_cpu_set_priority(int prio) 1367 { 1368 struct mpic *mpic = mpic_primary; 1369 1370 prio &= MPIC_CPU_TASKPRI_MASK; 1371 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); 1372 } 1373 1374 /* 1375 * XXX: someone who knows mpic should check this. 1376 * do we need to eoi the ipi including for kexec cpu here (see xics comments)? 1377 * or can we reset the mpic in the new kernel? 1378 */ 1379 void mpic_teardown_this_cpu(int secondary) 1380 { 1381 struct mpic *mpic = mpic_primary; 1382 unsigned long flags; 1383 u32 msk = 1 << hard_smp_processor_id(); 1384 unsigned int i; 1385 1386 BUG_ON(mpic == NULL); 1387 1388 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1389 spin_lock_irqsave(&mpic_lock, flags); 1390 1391 /* let the mpic know we don't want intrs. */ 1392 for (i = 0; i < mpic->num_sources ; i++) 1393 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1394 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); 1395 1396 /* Set current processor priority to max */ 1397 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1398 1399 spin_unlock_irqrestore(&mpic_lock, flags); 1400 } 1401 1402 1403 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask) 1404 { 1405 struct mpic *mpic = mpic_primary; 1406 1407 BUG_ON(mpic == NULL); 1408 1409 #ifdef DEBUG_IPI 1410 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); 1411 #endif 1412 1413 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + 1414 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), 1415 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); 1416 } 1417 1418 unsigned int mpic_get_one_irq(struct mpic *mpic) 1419 { 1420 u32 src; 1421 1422 src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK); 1423 #ifdef DEBUG_LOW 1424 DBG("%s: get_one_irq(): %d\n", mpic->name, src); 1425 #endif 1426 if (unlikely(src == mpic->spurious_vec)) { 1427 if (mpic->flags & MPIC_SPV_EOI) 1428 mpic_eoi(mpic); 1429 return NO_IRQ; 1430 } 1431 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { 1432 if (printk_ratelimit()) 1433 printk(KERN_WARNING "%s: Got protected source %d !\n", 1434 mpic->name, (int)src); 1435 mpic_eoi(mpic); 1436 return NO_IRQ; 1437 } 1438 1439 return irq_linear_revmap(mpic->irqhost, src); 1440 } 1441 1442 unsigned int mpic_get_irq(void) 1443 { 1444 struct mpic *mpic = mpic_primary; 1445 1446 BUG_ON(mpic == NULL); 1447 1448 return mpic_get_one_irq(mpic); 1449 } 1450 1451 1452 #ifdef CONFIG_SMP 1453 void mpic_request_ipis(void) 1454 { 1455 struct mpic *mpic = mpic_primary; 1456 int i, err; 1457 static char *ipi_names[] = { 1458 "IPI0 (call function)", 1459 "IPI1 (reschedule)", 1460 "IPI2 (unused)", 1461 "IPI3 (debugger break)", 1462 }; 1463 BUG_ON(mpic == NULL); 1464 1465 printk(KERN_INFO "mpic: requesting IPIs ... \n"); 1466 1467 for (i = 0; i < 4; i++) { 1468 unsigned int vipi = irq_create_mapping(mpic->irqhost, 1469 mpic->ipi_vecs[0] + i); 1470 if (vipi == NO_IRQ) { 1471 printk(KERN_ERR "Failed to map IPI %d\n", i); 1472 break; 1473 } 1474 err = request_irq(vipi, mpic_ipi_action, 1475 IRQF_DISABLED|IRQF_PERCPU, 1476 ipi_names[i], mpic); 1477 if (err) { 1478 printk(KERN_ERR "Request of irq %d for IPI %d failed\n", 1479 vipi, i); 1480 break; 1481 } 1482 } 1483 } 1484 1485 void smp_mpic_message_pass(int target, int msg) 1486 { 1487 /* make sure we're sending something that translates to an IPI */ 1488 if ((unsigned int)msg > 3) { 1489 printk("SMP %d: smp_message_pass: unknown msg %d\n", 1490 smp_processor_id(), msg); 1491 return; 1492 } 1493 switch (target) { 1494 case MSG_ALL: 1495 mpic_send_ipi(msg, 0xffffffff); 1496 break; 1497 case MSG_ALL_BUT_SELF: 1498 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id())); 1499 break; 1500 default: 1501 mpic_send_ipi(msg, 1 << target); 1502 break; 1503 } 1504 } 1505 1506 int __init smp_mpic_probe(void) 1507 { 1508 int nr_cpus; 1509 1510 DBG("smp_mpic_probe()...\n"); 1511 1512 nr_cpus = cpus_weight(cpu_possible_map); 1513 1514 DBG("nr_cpus: %d\n", nr_cpus); 1515 1516 if (nr_cpus > 1) 1517 mpic_request_ipis(); 1518 1519 return nr_cpus; 1520 } 1521 1522 void __devinit smp_mpic_setup_cpu(int cpu) 1523 { 1524 mpic_setup_this_cpu(); 1525 } 1526 #endif /* CONFIG_SMP */ 1527 1528 #ifdef CONFIG_PM 1529 static int mpic_suspend(struct sys_device *dev, pm_message_t state) 1530 { 1531 struct mpic *mpic = container_of(dev, struct mpic, sysdev); 1532 int i; 1533 1534 for (i = 0; i < mpic->num_sources; i++) { 1535 mpic->save_data[i].vecprio = 1536 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); 1537 mpic->save_data[i].dest = 1538 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); 1539 } 1540 1541 return 0; 1542 } 1543 1544 static int mpic_resume(struct sys_device *dev) 1545 { 1546 struct mpic *mpic = container_of(dev, struct mpic, sysdev); 1547 int i; 1548 1549 for (i = 0; i < mpic->num_sources; i++) { 1550 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), 1551 mpic->save_data[i].vecprio); 1552 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1553 mpic->save_data[i].dest); 1554 1555 #ifdef CONFIG_MPIC_U3_HT_IRQS 1556 { 1557 struct mpic_irq_fixup *fixup = &mpic->fixups[i]; 1558 1559 if (fixup->base) { 1560 /* we use the lowest bit in an inverted meaning */ 1561 if ((mpic->save_data[i].fixup_data & 1) == 0) 1562 continue; 1563 1564 /* Enable and configure */ 1565 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 1566 1567 writel(mpic->save_data[i].fixup_data & ~1, 1568 fixup->base + 4); 1569 } 1570 } 1571 #endif 1572 } /* end for loop */ 1573 1574 return 0; 1575 } 1576 #endif 1577 1578 static struct sysdev_class mpic_sysclass = { 1579 #ifdef CONFIG_PM 1580 .resume = mpic_resume, 1581 .suspend = mpic_suspend, 1582 #endif 1583 set_kset_name("mpic"), 1584 }; 1585 1586 static int mpic_init_sys(void) 1587 { 1588 struct mpic *mpic = mpics; 1589 int error, id = 0; 1590 1591 error = sysdev_class_register(&mpic_sysclass); 1592 1593 while (mpic && !error) { 1594 mpic->sysdev.cls = &mpic_sysclass; 1595 mpic->sysdev.id = id++; 1596 error = sysdev_register(&mpic->sysdev); 1597 mpic = mpic->next; 1598 } 1599 return error; 1600 } 1601 1602 device_initcall(mpic_init_sys); 1603