1 /* 2 * arch/powerpc/kernel/mpic.c 3 * 4 * Driver for interrupt controllers following the OpenPIC standard, the 5 * common implementation beeing IBM's MPIC. This driver also can deal 6 * with various broken implementations of this HW. 7 * 8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file COPYING in the main directory of this archive 12 * for more details. 13 */ 14 15 #undef DEBUG 16 #undef DEBUG_IPI 17 #undef DEBUG_IRQ 18 #undef DEBUG_LOW 19 20 #include <linux/types.h> 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/irq.h> 24 #include <linux/smp.h> 25 #include <linux/interrupt.h> 26 #include <linux/bootmem.h> 27 #include <linux/spinlock.h> 28 #include <linux/pci.h> 29 30 #include <asm/ptrace.h> 31 #include <asm/signal.h> 32 #include <asm/io.h> 33 #include <asm/pgtable.h> 34 #include <asm/irq.h> 35 #include <asm/machdep.h> 36 #include <asm/mpic.h> 37 #include <asm/smp.h> 38 39 #include "mpic.h" 40 41 #ifdef DEBUG 42 #define DBG(fmt...) printk(fmt) 43 #else 44 #define DBG(fmt...) 45 #endif 46 47 static struct mpic *mpics; 48 static struct mpic *mpic_primary; 49 static DEFINE_SPINLOCK(mpic_lock); 50 51 #ifdef CONFIG_PPC32 /* XXX for now */ 52 #ifdef CONFIG_IRQ_ALL_CPUS 53 #define distribute_irqs (1) 54 #else 55 #define distribute_irqs (0) 56 #endif 57 #endif 58 59 #ifdef CONFIG_MPIC_WEIRD 60 static u32 mpic_infos[][MPIC_IDX_END] = { 61 [0] = { /* Original OpenPIC compatible MPIC */ 62 MPIC_GREG_BASE, 63 MPIC_GREG_FEATURE_0, 64 MPIC_GREG_GLOBAL_CONF_0, 65 MPIC_GREG_VENDOR_ID, 66 MPIC_GREG_IPI_VECTOR_PRI_0, 67 MPIC_GREG_IPI_STRIDE, 68 MPIC_GREG_SPURIOUS, 69 MPIC_GREG_TIMER_FREQ, 70 71 MPIC_TIMER_BASE, 72 MPIC_TIMER_STRIDE, 73 MPIC_TIMER_CURRENT_CNT, 74 MPIC_TIMER_BASE_CNT, 75 MPIC_TIMER_VECTOR_PRI, 76 MPIC_TIMER_DESTINATION, 77 78 MPIC_CPU_BASE, 79 MPIC_CPU_STRIDE, 80 MPIC_CPU_IPI_DISPATCH_0, 81 MPIC_CPU_IPI_DISPATCH_STRIDE, 82 MPIC_CPU_CURRENT_TASK_PRI, 83 MPIC_CPU_WHOAMI, 84 MPIC_CPU_INTACK, 85 MPIC_CPU_EOI, 86 MPIC_CPU_MCACK, 87 88 MPIC_IRQ_BASE, 89 MPIC_IRQ_STRIDE, 90 MPIC_IRQ_VECTOR_PRI, 91 MPIC_VECPRI_VECTOR_MASK, 92 MPIC_VECPRI_POLARITY_POSITIVE, 93 MPIC_VECPRI_POLARITY_NEGATIVE, 94 MPIC_VECPRI_SENSE_LEVEL, 95 MPIC_VECPRI_SENSE_EDGE, 96 MPIC_VECPRI_POLARITY_MASK, 97 MPIC_VECPRI_SENSE_MASK, 98 MPIC_IRQ_DESTINATION 99 }, 100 [1] = { /* Tsi108/109 PIC */ 101 TSI108_GREG_BASE, 102 TSI108_GREG_FEATURE_0, 103 TSI108_GREG_GLOBAL_CONF_0, 104 TSI108_GREG_VENDOR_ID, 105 TSI108_GREG_IPI_VECTOR_PRI_0, 106 TSI108_GREG_IPI_STRIDE, 107 TSI108_GREG_SPURIOUS, 108 TSI108_GREG_TIMER_FREQ, 109 110 TSI108_TIMER_BASE, 111 TSI108_TIMER_STRIDE, 112 TSI108_TIMER_CURRENT_CNT, 113 TSI108_TIMER_BASE_CNT, 114 TSI108_TIMER_VECTOR_PRI, 115 TSI108_TIMER_DESTINATION, 116 117 TSI108_CPU_BASE, 118 TSI108_CPU_STRIDE, 119 TSI108_CPU_IPI_DISPATCH_0, 120 TSI108_CPU_IPI_DISPATCH_STRIDE, 121 TSI108_CPU_CURRENT_TASK_PRI, 122 TSI108_CPU_WHOAMI, 123 TSI108_CPU_INTACK, 124 TSI108_CPU_EOI, 125 TSI108_CPU_MCACK, 126 127 TSI108_IRQ_BASE, 128 TSI108_IRQ_STRIDE, 129 TSI108_IRQ_VECTOR_PRI, 130 TSI108_VECPRI_VECTOR_MASK, 131 TSI108_VECPRI_POLARITY_POSITIVE, 132 TSI108_VECPRI_POLARITY_NEGATIVE, 133 TSI108_VECPRI_SENSE_LEVEL, 134 TSI108_VECPRI_SENSE_EDGE, 135 TSI108_VECPRI_POLARITY_MASK, 136 TSI108_VECPRI_SENSE_MASK, 137 TSI108_IRQ_DESTINATION 138 }, 139 }; 140 141 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] 142 143 #else /* CONFIG_MPIC_WEIRD */ 144 145 #define MPIC_INFO(name) MPIC_##name 146 147 #endif /* CONFIG_MPIC_WEIRD */ 148 149 /* 150 * Register accessor functions 151 */ 152 153 154 static inline u32 _mpic_read(enum mpic_reg_type type, 155 struct mpic_reg_bank *rb, 156 unsigned int reg) 157 { 158 switch(type) { 159 #ifdef CONFIG_PPC_DCR 160 case mpic_access_dcr: 161 return dcr_read(rb->dhost, reg); 162 #endif 163 case mpic_access_mmio_be: 164 return in_be32(rb->base + (reg >> 2)); 165 case mpic_access_mmio_le: 166 default: 167 return in_le32(rb->base + (reg >> 2)); 168 } 169 } 170 171 static inline void _mpic_write(enum mpic_reg_type type, 172 struct mpic_reg_bank *rb, 173 unsigned int reg, u32 value) 174 { 175 switch(type) { 176 #ifdef CONFIG_PPC_DCR 177 case mpic_access_dcr: 178 dcr_write(rb->dhost, reg, value); 179 break; 180 #endif 181 case mpic_access_mmio_be: 182 out_be32(rb->base + (reg >> 2), value); 183 break; 184 case mpic_access_mmio_le: 185 default: 186 out_le32(rb->base + (reg >> 2), value); 187 break; 188 } 189 } 190 191 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) 192 { 193 enum mpic_reg_type type = mpic->reg_type; 194 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 195 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 196 197 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) 198 type = mpic_access_mmio_be; 199 return _mpic_read(type, &mpic->gregs, offset); 200 } 201 202 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) 203 { 204 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 205 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 206 207 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); 208 } 209 210 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) 211 { 212 unsigned int cpu = 0; 213 214 if (mpic->flags & MPIC_PRIMARY) 215 cpu = hard_smp_processor_id(); 216 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); 217 } 218 219 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) 220 { 221 unsigned int cpu = 0; 222 223 if (mpic->flags & MPIC_PRIMARY) 224 cpu = hard_smp_processor_id(); 225 226 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); 227 } 228 229 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) 230 { 231 unsigned int isu = src_no >> mpic->isu_shift; 232 unsigned int idx = src_no & mpic->isu_mask; 233 234 #ifdef CONFIG_MPIC_BROKEN_REGREAD 235 if (reg == 0) 236 return mpic->isu_reg0_shadow[idx]; 237 else 238 #endif 239 return _mpic_read(mpic->reg_type, &mpic->isus[isu], 240 reg + (idx * MPIC_INFO(IRQ_STRIDE))); 241 } 242 243 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, 244 unsigned int reg, u32 value) 245 { 246 unsigned int isu = src_no >> mpic->isu_shift; 247 unsigned int idx = src_no & mpic->isu_mask; 248 249 _mpic_write(mpic->reg_type, &mpic->isus[isu], 250 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); 251 252 #ifdef CONFIG_MPIC_BROKEN_REGREAD 253 if (reg == 0) 254 mpic->isu_reg0_shadow[idx] = value; 255 #endif 256 } 257 258 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) 259 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) 260 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) 261 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) 262 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) 263 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) 264 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) 265 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) 266 267 268 /* 269 * Low level utility functions 270 */ 271 272 273 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, 274 struct mpic_reg_bank *rb, unsigned int offset, 275 unsigned int size) 276 { 277 rb->base = ioremap(phys_addr + offset, size); 278 BUG_ON(rb->base == NULL); 279 } 280 281 #ifdef CONFIG_PPC_DCR 282 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, 283 unsigned int offset, unsigned int size) 284 { 285 const u32 *dbasep; 286 287 dbasep = of_get_property(mpic->irqhost->of_node, "dcr-reg", NULL); 288 289 rb->dhost = dcr_map(mpic->irqhost->of_node, *dbasep + offset, size); 290 BUG_ON(!DCR_MAP_OK(rb->dhost)); 291 } 292 293 static inline void mpic_map(struct mpic *mpic, phys_addr_t phys_addr, 294 struct mpic_reg_bank *rb, unsigned int offset, 295 unsigned int size) 296 { 297 if (mpic->flags & MPIC_USES_DCR) 298 _mpic_map_dcr(mpic, rb, offset, size); 299 else 300 _mpic_map_mmio(mpic, phys_addr, rb, offset, size); 301 } 302 #else /* CONFIG_PPC_DCR */ 303 #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) 304 #endif /* !CONFIG_PPC_DCR */ 305 306 307 308 /* Check if we have one of those nice broken MPICs with a flipped endian on 309 * reads from IPI registers 310 */ 311 static void __init mpic_test_broken_ipi(struct mpic *mpic) 312 { 313 u32 r; 314 315 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); 316 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); 317 318 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { 319 printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); 320 mpic->flags |= MPIC_BROKEN_IPI; 321 } 322 } 323 324 #ifdef CONFIG_MPIC_U3_HT_IRQS 325 326 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) 327 * to force the edge setting on the MPIC and do the ack workaround. 328 */ 329 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 330 { 331 if (source >= 128 || !mpic->fixups) 332 return 0; 333 return mpic->fixups[source].base != NULL; 334 } 335 336 337 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) 338 { 339 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 340 341 if (fixup->applebase) { 342 unsigned int soff = (fixup->index >> 3) & ~3; 343 unsigned int mask = 1U << (fixup->index & 0x1f); 344 writel(mask, fixup->applebase + soff); 345 } else { 346 spin_lock(&mpic->fixup_lock); 347 writeb(0x11 + 2 * fixup->index, fixup->base + 2); 348 writel(fixup->data, fixup->base + 4); 349 spin_unlock(&mpic->fixup_lock); 350 } 351 } 352 353 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, 354 unsigned int irqflags) 355 { 356 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 357 unsigned long flags; 358 u32 tmp; 359 360 if (fixup->base == NULL) 361 return; 362 363 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n", 364 source, irqflags, fixup->index); 365 spin_lock_irqsave(&mpic->fixup_lock, flags); 366 /* Enable and configure */ 367 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 368 tmp = readl(fixup->base + 4); 369 tmp &= ~(0x23U); 370 if (irqflags & IRQ_LEVEL) 371 tmp |= 0x22; 372 writel(tmp, fixup->base + 4); 373 spin_unlock_irqrestore(&mpic->fixup_lock, flags); 374 375 #ifdef CONFIG_PM 376 /* use the lowest bit inverted to the actual HW, 377 * set if this fixup was enabled, clear otherwise */ 378 mpic->save_data[source].fixup_data = tmp | 1; 379 #endif 380 } 381 382 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, 383 unsigned int irqflags) 384 { 385 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 386 unsigned long flags; 387 u32 tmp; 388 389 if (fixup->base == NULL) 390 return; 391 392 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags); 393 394 /* Disable */ 395 spin_lock_irqsave(&mpic->fixup_lock, flags); 396 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 397 tmp = readl(fixup->base + 4); 398 tmp |= 1; 399 writel(tmp, fixup->base + 4); 400 spin_unlock_irqrestore(&mpic->fixup_lock, flags); 401 402 #ifdef CONFIG_PM 403 /* use the lowest bit inverted to the actual HW, 404 * set if this fixup was enabled, clear otherwise */ 405 mpic->save_data[source].fixup_data = tmp & ~1; 406 #endif 407 } 408 409 #ifdef CONFIG_PCI_MSI 410 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, 411 unsigned int devfn) 412 { 413 u8 __iomem *base; 414 u8 pos, flags; 415 u64 addr = 0; 416 417 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 418 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 419 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 420 if (id == PCI_CAP_ID_HT) { 421 id = readb(devbase + pos + 3); 422 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) 423 break; 424 } 425 } 426 427 if (pos == 0) 428 return; 429 430 base = devbase + pos; 431 432 flags = readb(base + HT_MSI_FLAGS); 433 if (!(flags & HT_MSI_FLAGS_FIXED)) { 434 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; 435 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); 436 } 437 438 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%lx\n", 439 PCI_SLOT(devfn), PCI_FUNC(devfn), 440 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); 441 442 if (!(flags & HT_MSI_FLAGS_ENABLE)) 443 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); 444 } 445 #else 446 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, 447 unsigned int devfn) 448 { 449 return; 450 } 451 #endif 452 453 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, 454 unsigned int devfn, u32 vdid) 455 { 456 int i, irq, n; 457 u8 __iomem *base; 458 u32 tmp; 459 u8 pos; 460 461 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 462 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 463 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 464 if (id == PCI_CAP_ID_HT) { 465 id = readb(devbase + pos + 3); 466 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) 467 break; 468 } 469 } 470 if (pos == 0) 471 return; 472 473 base = devbase + pos; 474 writeb(0x01, base + 2); 475 n = (readl(base + 4) >> 16) & 0xff; 476 477 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" 478 " has %d irqs\n", 479 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); 480 481 for (i = 0; i <= n; i++) { 482 writeb(0x10 + 2 * i, base + 2); 483 tmp = readl(base + 4); 484 irq = (tmp >> 16) & 0xff; 485 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); 486 /* mask it , will be unmasked later */ 487 tmp |= 0x1; 488 writel(tmp, base + 4); 489 mpic->fixups[irq].index = i; 490 mpic->fixups[irq].base = base; 491 /* Apple HT PIC has a non-standard way of doing EOIs */ 492 if ((vdid & 0xffff) == 0x106b) 493 mpic->fixups[irq].applebase = devbase + 0x60; 494 else 495 mpic->fixups[irq].applebase = NULL; 496 writeb(0x11 + 2 * i, base + 2); 497 mpic->fixups[irq].data = readl(base + 4) | 0x80000000; 498 } 499 } 500 501 502 static void __init mpic_scan_ht_pics(struct mpic *mpic) 503 { 504 unsigned int devfn; 505 u8 __iomem *cfgspace; 506 507 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); 508 509 /* Allocate fixups array */ 510 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup)); 511 BUG_ON(mpic->fixups == NULL); 512 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup)); 513 514 /* Init spinlock */ 515 spin_lock_init(&mpic->fixup_lock); 516 517 /* Map U3 config space. We assume all IO-APICs are on the primary bus 518 * so we only need to map 64kB. 519 */ 520 cfgspace = ioremap(0xf2000000, 0x10000); 521 BUG_ON(cfgspace == NULL); 522 523 /* Now we scan all slots. We do a very quick scan, we read the header 524 * type, vendor ID and device ID only, that's plenty enough 525 */ 526 for (devfn = 0; devfn < 0x100; devfn++) { 527 u8 __iomem *devbase = cfgspace + (devfn << 8); 528 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); 529 u32 l = readl(devbase + PCI_VENDOR_ID); 530 u16 s; 531 532 DBG("devfn %x, l: %x\n", devfn, l); 533 534 /* If no device, skip */ 535 if (l == 0xffffffff || l == 0x00000000 || 536 l == 0x0000ffff || l == 0xffff0000) 537 goto next; 538 /* Check if is supports capability lists */ 539 s = readw(devbase + PCI_STATUS); 540 if (!(s & PCI_STATUS_CAP_LIST)) 541 goto next; 542 543 mpic_scan_ht_pic(mpic, devbase, devfn, l); 544 mpic_scan_ht_msi(mpic, devbase, devfn); 545 546 next: 547 /* next device, if function 0 */ 548 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) 549 devfn += 7; 550 } 551 } 552 553 #else /* CONFIG_MPIC_U3_HT_IRQS */ 554 555 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 556 { 557 return 0; 558 } 559 560 static void __init mpic_scan_ht_pics(struct mpic *mpic) 561 { 562 } 563 564 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 565 566 567 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) 568 569 /* Find an mpic associated with a given linux interrupt */ 570 static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi) 571 { 572 unsigned int src = mpic_irq_to_hw(irq); 573 struct mpic *mpic; 574 575 if (irq < NUM_ISA_INTERRUPTS) 576 return NULL; 577 578 mpic = irq_desc[irq].chip_data; 579 580 if (is_ipi) 581 *is_ipi = (src >= mpic->ipi_vecs[0] && 582 src <= mpic->ipi_vecs[3]); 583 584 return mpic; 585 } 586 587 /* Convert a cpu mask from logical to physical cpu numbers. */ 588 static inline u32 mpic_physmask(u32 cpumask) 589 { 590 int i; 591 u32 mask = 0; 592 593 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1) 594 mask |= (cpumask & 1) << get_hard_smp_processor_id(i); 595 return mask; 596 } 597 598 #ifdef CONFIG_SMP 599 /* Get the mpic structure from the IPI number */ 600 static inline struct mpic * mpic_from_ipi(unsigned int ipi) 601 { 602 return irq_desc[ipi].chip_data; 603 } 604 #endif 605 606 /* Get the mpic structure from the irq number */ 607 static inline struct mpic * mpic_from_irq(unsigned int irq) 608 { 609 return irq_desc[irq].chip_data; 610 } 611 612 /* Send an EOI */ 613 static inline void mpic_eoi(struct mpic *mpic) 614 { 615 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); 616 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); 617 } 618 619 #ifdef CONFIG_SMP 620 static irqreturn_t mpic_ipi_action(int irq, void *data) 621 { 622 long ipi = (long)data; 623 624 smp_message_recv(ipi); 625 626 return IRQ_HANDLED; 627 } 628 #endif /* CONFIG_SMP */ 629 630 /* 631 * Linux descriptor level callbacks 632 */ 633 634 635 void mpic_unmask_irq(unsigned int irq) 636 { 637 unsigned int loops = 100000; 638 struct mpic *mpic = mpic_from_irq(irq); 639 unsigned int src = mpic_irq_to_hw(irq); 640 641 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src); 642 643 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 644 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & 645 ~MPIC_VECPRI_MASK); 646 /* make sure mask gets to controller before we return to user */ 647 do { 648 if (!loops--) { 649 printk(KERN_ERR "mpic_enable_irq timeout\n"); 650 break; 651 } 652 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); 653 } 654 655 void mpic_mask_irq(unsigned int irq) 656 { 657 unsigned int loops = 100000; 658 struct mpic *mpic = mpic_from_irq(irq); 659 unsigned int src = mpic_irq_to_hw(irq); 660 661 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); 662 663 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 664 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | 665 MPIC_VECPRI_MASK); 666 667 /* make sure mask gets to controller before we return to user */ 668 do { 669 if (!loops--) { 670 printk(KERN_ERR "mpic_enable_irq timeout\n"); 671 break; 672 } 673 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); 674 } 675 676 void mpic_end_irq(unsigned int irq) 677 { 678 struct mpic *mpic = mpic_from_irq(irq); 679 680 #ifdef DEBUG_IRQ 681 DBG("%s: end_irq: %d\n", mpic->name, irq); 682 #endif 683 /* We always EOI on end_irq() even for edge interrupts since that 684 * should only lower the priority, the MPIC should have properly 685 * latched another edge interrupt coming in anyway 686 */ 687 688 mpic_eoi(mpic); 689 } 690 691 #ifdef CONFIG_MPIC_U3_HT_IRQS 692 693 static void mpic_unmask_ht_irq(unsigned int irq) 694 { 695 struct mpic *mpic = mpic_from_irq(irq); 696 unsigned int src = mpic_irq_to_hw(irq); 697 698 mpic_unmask_irq(irq); 699 700 if (irq_desc[irq].status & IRQ_LEVEL) 701 mpic_ht_end_irq(mpic, src); 702 } 703 704 static unsigned int mpic_startup_ht_irq(unsigned int irq) 705 { 706 struct mpic *mpic = mpic_from_irq(irq); 707 unsigned int src = mpic_irq_to_hw(irq); 708 709 mpic_unmask_irq(irq); 710 mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status); 711 712 return 0; 713 } 714 715 static void mpic_shutdown_ht_irq(unsigned int irq) 716 { 717 struct mpic *mpic = mpic_from_irq(irq); 718 unsigned int src = mpic_irq_to_hw(irq); 719 720 mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status); 721 mpic_mask_irq(irq); 722 } 723 724 static void mpic_end_ht_irq(unsigned int irq) 725 { 726 struct mpic *mpic = mpic_from_irq(irq); 727 unsigned int src = mpic_irq_to_hw(irq); 728 729 #ifdef DEBUG_IRQ 730 DBG("%s: end_irq: %d\n", mpic->name, irq); 731 #endif 732 /* We always EOI on end_irq() even for edge interrupts since that 733 * should only lower the priority, the MPIC should have properly 734 * latched another edge interrupt coming in anyway 735 */ 736 737 if (irq_desc[irq].status & IRQ_LEVEL) 738 mpic_ht_end_irq(mpic, src); 739 mpic_eoi(mpic); 740 } 741 #endif /* !CONFIG_MPIC_U3_HT_IRQS */ 742 743 #ifdef CONFIG_SMP 744 745 static void mpic_unmask_ipi(unsigned int irq) 746 { 747 struct mpic *mpic = mpic_from_ipi(irq); 748 unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]; 749 750 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src); 751 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); 752 } 753 754 static void mpic_mask_ipi(unsigned int irq) 755 { 756 /* NEVER disable an IPI... that's just plain wrong! */ 757 } 758 759 static void mpic_end_ipi(unsigned int irq) 760 { 761 struct mpic *mpic = mpic_from_ipi(irq); 762 763 /* 764 * IPIs are marked IRQ_PER_CPU. This has the side effect of 765 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from 766 * applying to them. We EOI them late to avoid re-entering. 767 * We mark IPI's with IRQF_DISABLED as they must run with 768 * irqs disabled. 769 */ 770 mpic_eoi(mpic); 771 } 772 773 #endif /* CONFIG_SMP */ 774 775 void mpic_set_affinity(unsigned int irq, cpumask_t cpumask) 776 { 777 struct mpic *mpic = mpic_from_irq(irq); 778 unsigned int src = mpic_irq_to_hw(irq); 779 780 cpumask_t tmp; 781 782 cpus_and(tmp, cpumask, cpu_online_map); 783 784 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 785 mpic_physmask(cpus_addr(tmp)[0])); 786 } 787 788 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) 789 { 790 /* Now convert sense value */ 791 switch(type & IRQ_TYPE_SENSE_MASK) { 792 case IRQ_TYPE_EDGE_RISING: 793 return MPIC_INFO(VECPRI_SENSE_EDGE) | 794 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 795 case IRQ_TYPE_EDGE_FALLING: 796 case IRQ_TYPE_EDGE_BOTH: 797 return MPIC_INFO(VECPRI_SENSE_EDGE) | 798 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 799 case IRQ_TYPE_LEVEL_HIGH: 800 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 801 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 802 case IRQ_TYPE_LEVEL_LOW: 803 default: 804 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 805 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 806 } 807 } 808 809 int mpic_set_irq_type(unsigned int virq, unsigned int flow_type) 810 { 811 struct mpic *mpic = mpic_from_irq(virq); 812 unsigned int src = mpic_irq_to_hw(virq); 813 struct irq_desc *desc = get_irq_desc(virq); 814 unsigned int vecpri, vold, vnew; 815 816 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", 817 mpic, virq, src, flow_type); 818 819 if (src >= mpic->irq_count) 820 return -EINVAL; 821 822 if (flow_type == IRQ_TYPE_NONE) 823 if (mpic->senses && src < mpic->senses_count) 824 flow_type = mpic->senses[src]; 825 if (flow_type == IRQ_TYPE_NONE) 826 flow_type = IRQ_TYPE_LEVEL_LOW; 827 828 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 829 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; 830 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 831 desc->status |= IRQ_LEVEL; 832 833 if (mpic_is_ht_interrupt(mpic, src)) 834 vecpri = MPIC_VECPRI_POLARITY_POSITIVE | 835 MPIC_VECPRI_SENSE_EDGE; 836 else 837 vecpri = mpic_type_to_vecpri(mpic, flow_type); 838 839 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 840 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | 841 MPIC_INFO(VECPRI_SENSE_MASK)); 842 vnew |= vecpri; 843 if (vold != vnew) 844 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); 845 846 return 0; 847 } 848 849 void mpic_set_vector(unsigned int virq, unsigned int vector) 850 { 851 struct mpic *mpic = mpic_from_irq(virq); 852 unsigned int src = mpic_irq_to_hw(virq); 853 unsigned int vecpri; 854 855 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", 856 mpic, virq, src, vector); 857 858 if (src >= mpic->irq_count) 859 return; 860 861 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 862 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK); 863 vecpri |= vector; 864 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 865 } 866 867 static struct irq_chip mpic_irq_chip = { 868 .mask = mpic_mask_irq, 869 .unmask = mpic_unmask_irq, 870 .eoi = mpic_end_irq, 871 .set_type = mpic_set_irq_type, 872 }; 873 874 #ifdef CONFIG_SMP 875 static struct irq_chip mpic_ipi_chip = { 876 .mask = mpic_mask_ipi, 877 .unmask = mpic_unmask_ipi, 878 .eoi = mpic_end_ipi, 879 }; 880 #endif /* CONFIG_SMP */ 881 882 #ifdef CONFIG_MPIC_U3_HT_IRQS 883 static struct irq_chip mpic_irq_ht_chip = { 884 .startup = mpic_startup_ht_irq, 885 .shutdown = mpic_shutdown_ht_irq, 886 .mask = mpic_mask_irq, 887 .unmask = mpic_unmask_ht_irq, 888 .eoi = mpic_end_ht_irq, 889 .set_type = mpic_set_irq_type, 890 }; 891 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 892 893 894 static int mpic_host_match(struct irq_host *h, struct device_node *node) 895 { 896 /* Exact match, unless mpic node is NULL */ 897 return h->of_node == NULL || h->of_node == node; 898 } 899 900 static int mpic_host_map(struct irq_host *h, unsigned int virq, 901 irq_hw_number_t hw) 902 { 903 struct mpic *mpic = h->host_data; 904 struct irq_chip *chip; 905 906 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); 907 908 if (hw == mpic->spurious_vec) 909 return -EINVAL; 910 if (mpic->protected && test_bit(hw, mpic->protected)) 911 return -EINVAL; 912 913 #ifdef CONFIG_SMP 914 else if (hw >= mpic->ipi_vecs[0]) { 915 WARN_ON(!(mpic->flags & MPIC_PRIMARY)); 916 917 DBG("mpic: mapping as IPI\n"); 918 set_irq_chip_data(virq, mpic); 919 set_irq_chip_and_handler(virq, &mpic->hc_ipi, 920 handle_percpu_irq); 921 return 0; 922 } 923 #endif /* CONFIG_SMP */ 924 925 if (hw >= mpic->irq_count) 926 return -EINVAL; 927 928 mpic_msi_reserve_hwirq(mpic, hw); 929 930 /* Default chip */ 931 chip = &mpic->hc_irq; 932 933 #ifdef CONFIG_MPIC_U3_HT_IRQS 934 /* Check for HT interrupts, override vecpri */ 935 if (mpic_is_ht_interrupt(mpic, hw)) 936 chip = &mpic->hc_ht_irq; 937 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 938 939 DBG("mpic: mapping to irq chip @%p\n", chip); 940 941 set_irq_chip_data(virq, mpic); 942 set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq); 943 944 /* Set default irq type */ 945 set_irq_type(virq, IRQ_TYPE_NONE); 946 947 return 0; 948 } 949 950 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, 951 u32 *intspec, unsigned int intsize, 952 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 953 954 { 955 static unsigned char map_mpic_senses[4] = { 956 IRQ_TYPE_EDGE_RISING, 957 IRQ_TYPE_LEVEL_LOW, 958 IRQ_TYPE_LEVEL_HIGH, 959 IRQ_TYPE_EDGE_FALLING, 960 }; 961 962 *out_hwirq = intspec[0]; 963 if (intsize > 1) { 964 u32 mask = 0x3; 965 966 /* Apple invented a new race of encoding on machines with 967 * an HT APIC. They encode, among others, the index within 968 * the HT APIC. We don't care about it here since thankfully, 969 * it appears that they have the APIC already properly 970 * configured, and thus our current fixup code that reads the 971 * APIC config works fine. However, we still need to mask out 972 * bits in the specifier to make sure we only get bit 0 which 973 * is the level/edge bit (the only sense bit exposed by Apple), 974 * as their bit 1 means something else. 975 */ 976 if (machine_is(powermac)) 977 mask = 0x1; 978 *out_flags = map_mpic_senses[intspec[1] & mask]; 979 } else 980 *out_flags = IRQ_TYPE_NONE; 981 982 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", 983 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); 984 985 return 0; 986 } 987 988 static struct irq_host_ops mpic_host_ops = { 989 .match = mpic_host_match, 990 .map = mpic_host_map, 991 .xlate = mpic_host_xlate, 992 }; 993 994 /* 995 * Exported functions 996 */ 997 998 struct mpic * __init mpic_alloc(struct device_node *node, 999 phys_addr_t phys_addr, 1000 unsigned int flags, 1001 unsigned int isu_size, 1002 unsigned int irq_count, 1003 const char *name) 1004 { 1005 struct mpic *mpic; 1006 u32 greg_feature; 1007 const char *vers; 1008 int i; 1009 int intvec_top; 1010 u64 paddr = phys_addr; 1011 1012 mpic = alloc_bootmem(sizeof(struct mpic)); 1013 if (mpic == NULL) 1014 return NULL; 1015 1016 memset(mpic, 0, sizeof(struct mpic)); 1017 mpic->name = name; 1018 1019 mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 1020 isu_size, &mpic_host_ops, 1021 flags & MPIC_LARGE_VECTORS ? 2048 : 256); 1022 if (mpic->irqhost == NULL) 1023 return NULL; 1024 1025 mpic->irqhost->host_data = mpic; 1026 mpic->hc_irq = mpic_irq_chip; 1027 mpic->hc_irq.typename = name; 1028 if (flags & MPIC_PRIMARY) 1029 mpic->hc_irq.set_affinity = mpic_set_affinity; 1030 #ifdef CONFIG_MPIC_U3_HT_IRQS 1031 mpic->hc_ht_irq = mpic_irq_ht_chip; 1032 mpic->hc_ht_irq.typename = name; 1033 if (flags & MPIC_PRIMARY) 1034 mpic->hc_ht_irq.set_affinity = mpic_set_affinity; 1035 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 1036 1037 #ifdef CONFIG_SMP 1038 mpic->hc_ipi = mpic_ipi_chip; 1039 mpic->hc_ipi.typename = name; 1040 #endif /* CONFIG_SMP */ 1041 1042 mpic->flags = flags; 1043 mpic->isu_size = isu_size; 1044 mpic->irq_count = irq_count; 1045 mpic->num_sources = 0; /* so far */ 1046 1047 if (flags & MPIC_LARGE_VECTORS) 1048 intvec_top = 2047; 1049 else 1050 intvec_top = 255; 1051 1052 mpic->timer_vecs[0] = intvec_top - 8; 1053 mpic->timer_vecs[1] = intvec_top - 7; 1054 mpic->timer_vecs[2] = intvec_top - 6; 1055 mpic->timer_vecs[3] = intvec_top - 5; 1056 mpic->ipi_vecs[0] = intvec_top - 4; 1057 mpic->ipi_vecs[1] = intvec_top - 3; 1058 mpic->ipi_vecs[2] = intvec_top - 2; 1059 mpic->ipi_vecs[3] = intvec_top - 1; 1060 mpic->spurious_vec = intvec_top; 1061 1062 /* Check for "big-endian" in device-tree */ 1063 if (node && of_get_property(node, "big-endian", NULL) != NULL) 1064 mpic->flags |= MPIC_BIG_ENDIAN; 1065 1066 /* Look for protected sources */ 1067 if (node) { 1068 int psize; 1069 unsigned int bits, mapsize; 1070 const u32 *psrc = 1071 of_get_property(node, "protected-sources", &psize); 1072 if (psrc) { 1073 psize /= 4; 1074 bits = intvec_top + 1; 1075 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long); 1076 mpic->protected = alloc_bootmem(mapsize); 1077 BUG_ON(mpic->protected == NULL); 1078 memset(mpic->protected, 0, mapsize); 1079 for (i = 0; i < psize; i++) { 1080 if (psrc[i] > intvec_top) 1081 continue; 1082 __set_bit(psrc[i], mpic->protected); 1083 } 1084 } 1085 } 1086 1087 #ifdef CONFIG_MPIC_WEIRD 1088 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)]; 1089 #endif 1090 1091 /* default register type */ 1092 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ? 1093 mpic_access_mmio_be : mpic_access_mmio_le; 1094 1095 /* If no physical address is passed in, a device-node is mandatory */ 1096 BUG_ON(paddr == 0 && node == NULL); 1097 1098 /* If no physical address passed in, check if it's dcr based */ 1099 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) { 1100 #ifdef CONFIG_PPC_DCR 1101 mpic->flags |= MPIC_USES_DCR; 1102 mpic->reg_type = mpic_access_dcr; 1103 #else 1104 BUG(); 1105 #endif /* CONFIG_PPC_DCR */ 1106 } 1107 1108 /* If the MPIC is not DCR based, and no physical address was passed 1109 * in, try to obtain one 1110 */ 1111 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) { 1112 const u32 *reg = of_get_property(node, "reg", NULL); 1113 BUG_ON(reg == NULL); 1114 paddr = of_translate_address(node, reg); 1115 BUG_ON(paddr == OF_BAD_ADDR); 1116 } 1117 1118 /* Map the global registers */ 1119 mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); 1120 mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); 1121 1122 /* Reset */ 1123 if (flags & MPIC_WANTS_RESET) { 1124 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1125 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1126 | MPIC_GREG_GCONF_RESET); 1127 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1128 & MPIC_GREG_GCONF_RESET) 1129 mb(); 1130 } 1131 1132 if (flags & MPIC_ENABLE_MCK) 1133 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1134 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1135 | MPIC_GREG_GCONF_MCK); 1136 1137 /* Read feature register, calculate num CPUs and, for non-ISU 1138 * MPICs, num sources as well. On ISU MPICs, sources are counted 1139 * as ISUs are added 1140 */ 1141 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); 1142 mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK) 1143 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; 1144 if (isu_size == 0) { 1145 if (flags & MPIC_BROKEN_FRR_NIRQS) 1146 mpic->num_sources = mpic->irq_count; 1147 else 1148 mpic->num_sources = 1149 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) 1150 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; 1151 } 1152 1153 /* Map the per-CPU registers */ 1154 for (i = 0; i < mpic->num_cpus; i++) { 1155 mpic_map(mpic, paddr, &mpic->cpuregs[i], 1156 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), 1157 0x1000); 1158 } 1159 1160 /* Initialize main ISU if none provided */ 1161 if (mpic->isu_size == 0) { 1162 mpic->isu_size = mpic->num_sources; 1163 mpic_map(mpic, paddr, &mpic->isus[0], 1164 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1165 } 1166 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 1167 mpic->isu_mask = (1 << mpic->isu_shift) - 1; 1168 1169 /* Display version */ 1170 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) { 1171 case 1: 1172 vers = "1.0"; 1173 break; 1174 case 2: 1175 vers = "1.2"; 1176 break; 1177 case 3: 1178 vers = "1.3"; 1179 break; 1180 default: 1181 vers = "<unknown>"; 1182 break; 1183 } 1184 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," 1185 " max %d CPUs\n", 1186 name, vers, (unsigned long long)paddr, mpic->num_cpus); 1187 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", 1188 mpic->isu_size, mpic->isu_shift, mpic->isu_mask); 1189 1190 mpic->next = mpics; 1191 mpics = mpic; 1192 1193 if (flags & MPIC_PRIMARY) { 1194 mpic_primary = mpic; 1195 irq_set_default_host(mpic->irqhost); 1196 } 1197 1198 return mpic; 1199 } 1200 1201 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, 1202 phys_addr_t paddr) 1203 { 1204 unsigned int isu_first = isu_num * mpic->isu_size; 1205 1206 BUG_ON(isu_num >= MPIC_MAX_ISU); 1207 1208 mpic_map(mpic, paddr, &mpic->isus[isu_num], 0, 1209 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1210 if ((isu_first + mpic->isu_size) > mpic->num_sources) 1211 mpic->num_sources = isu_first + mpic->isu_size; 1212 } 1213 1214 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) 1215 { 1216 mpic->senses = senses; 1217 mpic->senses_count = count; 1218 } 1219 1220 void __init mpic_init(struct mpic *mpic) 1221 { 1222 int i; 1223 1224 BUG_ON(mpic->num_sources == 0); 1225 1226 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); 1227 1228 /* Set current processor priority to max */ 1229 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1230 1231 /* Initialize timers: just disable them all */ 1232 for (i = 0; i < 4; i++) { 1233 mpic_write(mpic->tmregs, 1234 i * MPIC_INFO(TIMER_STRIDE) + 1235 MPIC_INFO(TIMER_DESTINATION), 0); 1236 mpic_write(mpic->tmregs, 1237 i * MPIC_INFO(TIMER_STRIDE) + 1238 MPIC_INFO(TIMER_VECTOR_PRI), 1239 MPIC_VECPRI_MASK | 1240 (mpic->timer_vecs[0] + i)); 1241 } 1242 1243 /* Initialize IPIs to our reserved vectors and mark them disabled for now */ 1244 mpic_test_broken_ipi(mpic); 1245 for (i = 0; i < 4; i++) { 1246 mpic_ipi_write(i, 1247 MPIC_VECPRI_MASK | 1248 (10 << MPIC_VECPRI_PRIORITY_SHIFT) | 1249 (mpic->ipi_vecs[0] + i)); 1250 } 1251 1252 /* Initialize interrupt sources */ 1253 if (mpic->irq_count == 0) 1254 mpic->irq_count = mpic->num_sources; 1255 1256 /* Do the HT PIC fixups on U3 broken mpic */ 1257 DBG("MPIC flags: %x\n", mpic->flags); 1258 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) { 1259 mpic_scan_ht_pics(mpic); 1260 mpic_u3msi_init(mpic); 1261 } 1262 1263 mpic_pasemi_msi_init(mpic); 1264 1265 for (i = 0; i < mpic->num_sources; i++) { 1266 /* start with vector = source number, and masked */ 1267 u32 vecpri = MPIC_VECPRI_MASK | i | 1268 (8 << MPIC_VECPRI_PRIORITY_SHIFT); 1269 1270 /* check if protected */ 1271 if (mpic->protected && test_bit(i, mpic->protected)) 1272 continue; 1273 /* init hw */ 1274 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 1275 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1276 1 << hard_smp_processor_id()); 1277 } 1278 1279 /* Init spurious vector */ 1280 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); 1281 1282 /* Disable 8259 passthrough, if supported */ 1283 if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) 1284 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1285 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1286 | MPIC_GREG_GCONF_8259_PTHROU_DIS); 1287 1288 if (mpic->flags & MPIC_NO_BIAS) 1289 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1290 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1291 | MPIC_GREG_GCONF_NO_BIAS); 1292 1293 /* Set current processor priority to 0 */ 1294 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 1295 1296 #ifdef CONFIG_PM 1297 /* allocate memory to save mpic state */ 1298 mpic->save_data = alloc_bootmem(mpic->num_sources * sizeof(struct mpic_irq_save)); 1299 BUG_ON(mpic->save_data == NULL); 1300 #endif 1301 } 1302 1303 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) 1304 { 1305 u32 v; 1306 1307 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1308 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; 1309 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); 1310 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1311 } 1312 1313 void __init mpic_set_serial_int(struct mpic *mpic, int enable) 1314 { 1315 unsigned long flags; 1316 u32 v; 1317 1318 spin_lock_irqsave(&mpic_lock, flags); 1319 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1320 if (enable) 1321 v |= MPIC_GREG_GLOBAL_CONF_1_SIE; 1322 else 1323 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; 1324 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1325 spin_unlock_irqrestore(&mpic_lock, flags); 1326 } 1327 1328 void mpic_irq_set_priority(unsigned int irq, unsigned int pri) 1329 { 1330 unsigned int is_ipi; 1331 struct mpic *mpic = mpic_find(irq, &is_ipi); 1332 unsigned int src = mpic_irq_to_hw(irq); 1333 unsigned long flags; 1334 u32 reg; 1335 1336 if (!mpic) 1337 return; 1338 1339 spin_lock_irqsave(&mpic_lock, flags); 1340 if (is_ipi) { 1341 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & 1342 ~MPIC_VECPRI_PRIORITY_MASK; 1343 mpic_ipi_write(src - mpic->ipi_vecs[0], 1344 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1345 } else { 1346 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) 1347 & ~MPIC_VECPRI_PRIORITY_MASK; 1348 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 1349 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1350 } 1351 spin_unlock_irqrestore(&mpic_lock, flags); 1352 } 1353 1354 void mpic_setup_this_cpu(void) 1355 { 1356 #ifdef CONFIG_SMP 1357 struct mpic *mpic = mpic_primary; 1358 unsigned long flags; 1359 u32 msk = 1 << hard_smp_processor_id(); 1360 unsigned int i; 1361 1362 BUG_ON(mpic == NULL); 1363 1364 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1365 1366 spin_lock_irqsave(&mpic_lock, flags); 1367 1368 /* let the mpic know we want intrs. default affinity is 0xffffffff 1369 * until changed via /proc. That's how it's done on x86. If we want 1370 * it differently, then we should make sure we also change the default 1371 * values of irq_desc[].affinity in irq.c. 1372 */ 1373 if (distribute_irqs) { 1374 for (i = 0; i < mpic->num_sources ; i++) 1375 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1376 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); 1377 } 1378 1379 /* Set current processor priority to 0 */ 1380 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 1381 1382 spin_unlock_irqrestore(&mpic_lock, flags); 1383 #endif /* CONFIG_SMP */ 1384 } 1385 1386 int mpic_cpu_get_priority(void) 1387 { 1388 struct mpic *mpic = mpic_primary; 1389 1390 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); 1391 } 1392 1393 void mpic_cpu_set_priority(int prio) 1394 { 1395 struct mpic *mpic = mpic_primary; 1396 1397 prio &= MPIC_CPU_TASKPRI_MASK; 1398 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); 1399 } 1400 1401 void mpic_teardown_this_cpu(int secondary) 1402 { 1403 struct mpic *mpic = mpic_primary; 1404 unsigned long flags; 1405 u32 msk = 1 << hard_smp_processor_id(); 1406 unsigned int i; 1407 1408 BUG_ON(mpic == NULL); 1409 1410 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1411 spin_lock_irqsave(&mpic_lock, flags); 1412 1413 /* let the mpic know we don't want intrs. */ 1414 for (i = 0; i < mpic->num_sources ; i++) 1415 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1416 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); 1417 1418 /* Set current processor priority to max */ 1419 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1420 /* We need to EOI the IPI since not all platforms reset the MPIC 1421 * on boot and new interrupts wouldn't get delivered otherwise. 1422 */ 1423 mpic_eoi(mpic); 1424 1425 spin_unlock_irqrestore(&mpic_lock, flags); 1426 } 1427 1428 1429 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask) 1430 { 1431 struct mpic *mpic = mpic_primary; 1432 1433 BUG_ON(mpic == NULL); 1434 1435 #ifdef DEBUG_IPI 1436 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); 1437 #endif 1438 1439 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + 1440 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), 1441 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); 1442 } 1443 1444 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) 1445 { 1446 u32 src; 1447 1448 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); 1449 #ifdef DEBUG_LOW 1450 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); 1451 #endif 1452 if (unlikely(src == mpic->spurious_vec)) { 1453 if (mpic->flags & MPIC_SPV_EOI) 1454 mpic_eoi(mpic); 1455 return NO_IRQ; 1456 } 1457 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { 1458 if (printk_ratelimit()) 1459 printk(KERN_WARNING "%s: Got protected source %d !\n", 1460 mpic->name, (int)src); 1461 mpic_eoi(mpic); 1462 return NO_IRQ; 1463 } 1464 1465 return irq_linear_revmap(mpic->irqhost, src); 1466 } 1467 1468 unsigned int mpic_get_one_irq(struct mpic *mpic) 1469 { 1470 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); 1471 } 1472 1473 unsigned int mpic_get_irq(void) 1474 { 1475 struct mpic *mpic = mpic_primary; 1476 1477 BUG_ON(mpic == NULL); 1478 1479 return mpic_get_one_irq(mpic); 1480 } 1481 1482 unsigned int mpic_get_mcirq(void) 1483 { 1484 struct mpic *mpic = mpic_primary; 1485 1486 BUG_ON(mpic == NULL); 1487 1488 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); 1489 } 1490 1491 #ifdef CONFIG_SMP 1492 void mpic_request_ipis(void) 1493 { 1494 struct mpic *mpic = mpic_primary; 1495 long i, err; 1496 static char *ipi_names[] = { 1497 "IPI0 (call function)", 1498 "IPI1 (reschedule)", 1499 "IPI2 (call function single)", 1500 "IPI3 (debugger break)", 1501 }; 1502 BUG_ON(mpic == NULL); 1503 1504 printk(KERN_INFO "mpic: requesting IPIs ... \n"); 1505 1506 for (i = 0; i < 4; i++) { 1507 unsigned int vipi = irq_create_mapping(mpic->irqhost, 1508 mpic->ipi_vecs[0] + i); 1509 if (vipi == NO_IRQ) { 1510 printk(KERN_ERR "Failed to map IPI %ld\n", i); 1511 break; 1512 } 1513 err = request_irq(vipi, mpic_ipi_action, 1514 IRQF_DISABLED|IRQF_PERCPU, 1515 ipi_names[i], (void *)i); 1516 if (err) { 1517 printk(KERN_ERR "Request of irq %d for IPI %ld failed\n", 1518 vipi, i); 1519 break; 1520 } 1521 } 1522 } 1523 1524 void smp_mpic_message_pass(int target, int msg) 1525 { 1526 /* make sure we're sending something that translates to an IPI */ 1527 if ((unsigned int)msg > 3) { 1528 printk("SMP %d: smp_message_pass: unknown msg %d\n", 1529 smp_processor_id(), msg); 1530 return; 1531 } 1532 switch (target) { 1533 case MSG_ALL: 1534 mpic_send_ipi(msg, 0xffffffff); 1535 break; 1536 case MSG_ALL_BUT_SELF: 1537 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id())); 1538 break; 1539 default: 1540 mpic_send_ipi(msg, 1 << target); 1541 break; 1542 } 1543 } 1544 1545 int __init smp_mpic_probe(void) 1546 { 1547 int nr_cpus; 1548 1549 DBG("smp_mpic_probe()...\n"); 1550 1551 nr_cpus = cpus_weight(cpu_possible_map); 1552 1553 DBG("nr_cpus: %d\n", nr_cpus); 1554 1555 if (nr_cpus > 1) 1556 mpic_request_ipis(); 1557 1558 return nr_cpus; 1559 } 1560 1561 void __devinit smp_mpic_setup_cpu(int cpu) 1562 { 1563 mpic_setup_this_cpu(); 1564 } 1565 #endif /* CONFIG_SMP */ 1566 1567 #ifdef CONFIG_PM 1568 static int mpic_suspend(struct sys_device *dev, pm_message_t state) 1569 { 1570 struct mpic *mpic = container_of(dev, struct mpic, sysdev); 1571 int i; 1572 1573 for (i = 0; i < mpic->num_sources; i++) { 1574 mpic->save_data[i].vecprio = 1575 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); 1576 mpic->save_data[i].dest = 1577 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); 1578 } 1579 1580 return 0; 1581 } 1582 1583 static int mpic_resume(struct sys_device *dev) 1584 { 1585 struct mpic *mpic = container_of(dev, struct mpic, sysdev); 1586 int i; 1587 1588 for (i = 0; i < mpic->num_sources; i++) { 1589 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), 1590 mpic->save_data[i].vecprio); 1591 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1592 mpic->save_data[i].dest); 1593 1594 #ifdef CONFIG_MPIC_U3_HT_IRQS 1595 { 1596 struct mpic_irq_fixup *fixup = &mpic->fixups[i]; 1597 1598 if (fixup->base) { 1599 /* we use the lowest bit in an inverted meaning */ 1600 if ((mpic->save_data[i].fixup_data & 1) == 0) 1601 continue; 1602 1603 /* Enable and configure */ 1604 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 1605 1606 writel(mpic->save_data[i].fixup_data & ~1, 1607 fixup->base + 4); 1608 } 1609 } 1610 #endif 1611 } /* end for loop */ 1612 1613 return 0; 1614 } 1615 #endif 1616 1617 static struct sysdev_class mpic_sysclass = { 1618 #ifdef CONFIG_PM 1619 .resume = mpic_resume, 1620 .suspend = mpic_suspend, 1621 #endif 1622 .name = "mpic", 1623 }; 1624 1625 static int mpic_init_sys(void) 1626 { 1627 struct mpic *mpic = mpics; 1628 int error, id = 0; 1629 1630 error = sysdev_class_register(&mpic_sysclass); 1631 1632 while (mpic && !error) { 1633 mpic->sysdev.cls = &mpic_sysclass; 1634 mpic->sysdev.id = id++; 1635 error = sysdev_register(&mpic->sysdev); 1636 mpic = mpic->next; 1637 } 1638 return error; 1639 } 1640 1641 device_initcall(mpic_init_sys); 1642