1 /* 2 * arch/powerpc/kernel/mpic.c 3 * 4 * Driver for interrupt controllers following the OpenPIC standard, the 5 * common implementation beeing IBM's MPIC. This driver also can deal 6 * with various broken implementations of this HW. 7 * 8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file COPYING in the main directory of this archive 12 * for more details. 13 */ 14 15 #undef DEBUG 16 #undef DEBUG_IPI 17 #undef DEBUG_IRQ 18 #undef DEBUG_LOW 19 20 #include <linux/types.h> 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/irq.h> 24 #include <linux/smp.h> 25 #include <linux/interrupt.h> 26 #include <linux/bootmem.h> 27 #include <linux/spinlock.h> 28 #include <linux/pci.h> 29 30 #include <asm/ptrace.h> 31 #include <asm/signal.h> 32 #include <asm/io.h> 33 #include <asm/pgtable.h> 34 #include <asm/irq.h> 35 #include <asm/machdep.h> 36 #include <asm/mpic.h> 37 #include <asm/smp.h> 38 39 #ifdef DEBUG 40 #define DBG(fmt...) printk(fmt) 41 #else 42 #define DBG(fmt...) 43 #endif 44 45 static struct mpic *mpics; 46 static struct mpic *mpic_primary; 47 static DEFINE_SPINLOCK(mpic_lock); 48 49 #ifdef CONFIG_PPC32 /* XXX for now */ 50 #ifdef CONFIG_IRQ_ALL_CPUS 51 #define distribute_irqs (1) 52 #else 53 #define distribute_irqs (0) 54 #endif 55 #endif 56 57 #ifdef CONFIG_MPIC_WEIRD 58 static u32 mpic_infos[][MPIC_IDX_END] = { 59 [0] = { /* Original OpenPIC compatible MPIC */ 60 MPIC_GREG_BASE, 61 MPIC_GREG_FEATURE_0, 62 MPIC_GREG_GLOBAL_CONF_0, 63 MPIC_GREG_VENDOR_ID, 64 MPIC_GREG_IPI_VECTOR_PRI_0, 65 MPIC_GREG_IPI_STRIDE, 66 MPIC_GREG_SPURIOUS, 67 MPIC_GREG_TIMER_FREQ, 68 69 MPIC_TIMER_BASE, 70 MPIC_TIMER_STRIDE, 71 MPIC_TIMER_CURRENT_CNT, 72 MPIC_TIMER_BASE_CNT, 73 MPIC_TIMER_VECTOR_PRI, 74 MPIC_TIMER_DESTINATION, 75 76 MPIC_CPU_BASE, 77 MPIC_CPU_STRIDE, 78 MPIC_CPU_IPI_DISPATCH_0, 79 MPIC_CPU_IPI_DISPATCH_STRIDE, 80 MPIC_CPU_CURRENT_TASK_PRI, 81 MPIC_CPU_WHOAMI, 82 MPIC_CPU_INTACK, 83 MPIC_CPU_EOI, 84 85 MPIC_IRQ_BASE, 86 MPIC_IRQ_STRIDE, 87 MPIC_IRQ_VECTOR_PRI, 88 MPIC_VECPRI_VECTOR_MASK, 89 MPIC_VECPRI_POLARITY_POSITIVE, 90 MPIC_VECPRI_POLARITY_NEGATIVE, 91 MPIC_VECPRI_SENSE_LEVEL, 92 MPIC_VECPRI_SENSE_EDGE, 93 MPIC_VECPRI_POLARITY_MASK, 94 MPIC_VECPRI_SENSE_MASK, 95 MPIC_IRQ_DESTINATION 96 }, 97 [1] = { /* Tsi108/109 PIC */ 98 TSI108_GREG_BASE, 99 TSI108_GREG_FEATURE_0, 100 TSI108_GREG_GLOBAL_CONF_0, 101 TSI108_GREG_VENDOR_ID, 102 TSI108_GREG_IPI_VECTOR_PRI_0, 103 TSI108_GREG_IPI_STRIDE, 104 TSI108_GREG_SPURIOUS, 105 TSI108_GREG_TIMER_FREQ, 106 107 TSI108_TIMER_BASE, 108 TSI108_TIMER_STRIDE, 109 TSI108_TIMER_CURRENT_CNT, 110 TSI108_TIMER_BASE_CNT, 111 TSI108_TIMER_VECTOR_PRI, 112 TSI108_TIMER_DESTINATION, 113 114 TSI108_CPU_BASE, 115 TSI108_CPU_STRIDE, 116 TSI108_CPU_IPI_DISPATCH_0, 117 TSI108_CPU_IPI_DISPATCH_STRIDE, 118 TSI108_CPU_CURRENT_TASK_PRI, 119 TSI108_CPU_WHOAMI, 120 TSI108_CPU_INTACK, 121 TSI108_CPU_EOI, 122 123 TSI108_IRQ_BASE, 124 TSI108_IRQ_STRIDE, 125 TSI108_IRQ_VECTOR_PRI, 126 TSI108_VECPRI_VECTOR_MASK, 127 TSI108_VECPRI_POLARITY_POSITIVE, 128 TSI108_VECPRI_POLARITY_NEGATIVE, 129 TSI108_VECPRI_SENSE_LEVEL, 130 TSI108_VECPRI_SENSE_EDGE, 131 TSI108_VECPRI_POLARITY_MASK, 132 TSI108_VECPRI_SENSE_MASK, 133 TSI108_IRQ_DESTINATION 134 }, 135 }; 136 137 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] 138 139 #else /* CONFIG_MPIC_WEIRD */ 140 141 #define MPIC_INFO(name) MPIC_##name 142 143 #endif /* CONFIG_MPIC_WEIRD */ 144 145 /* 146 * Register accessor functions 147 */ 148 149 150 static inline u32 _mpic_read(enum mpic_reg_type type, 151 struct mpic_reg_bank *rb, 152 unsigned int reg) 153 { 154 switch(type) { 155 #ifdef CONFIG_PPC_DCR 156 case mpic_access_dcr: 157 return dcr_read(rb->dhost, 158 rb->dbase + reg + rb->doff); 159 #endif 160 case mpic_access_mmio_be: 161 return in_be32(rb->base + (reg >> 2)); 162 case mpic_access_mmio_le: 163 default: 164 return in_le32(rb->base + (reg >> 2)); 165 } 166 } 167 168 static inline void _mpic_write(enum mpic_reg_type type, 169 struct mpic_reg_bank *rb, 170 unsigned int reg, u32 value) 171 { 172 switch(type) { 173 #ifdef CONFIG_PPC_DCR 174 case mpic_access_dcr: 175 return dcr_write(rb->dhost, 176 rb->dbase + reg + rb->doff, value); 177 #endif 178 case mpic_access_mmio_be: 179 return out_be32(rb->base + (reg >> 2), value); 180 case mpic_access_mmio_le: 181 default: 182 return out_le32(rb->base + (reg >> 2), value); 183 } 184 } 185 186 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) 187 { 188 enum mpic_reg_type type = mpic->reg_type; 189 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 190 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 191 192 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) 193 type = mpic_access_mmio_be; 194 return _mpic_read(type, &mpic->gregs, offset); 195 } 196 197 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) 198 { 199 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 200 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 201 202 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); 203 } 204 205 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) 206 { 207 unsigned int cpu = 0; 208 209 if (mpic->flags & MPIC_PRIMARY) 210 cpu = hard_smp_processor_id(); 211 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); 212 } 213 214 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) 215 { 216 unsigned int cpu = 0; 217 218 if (mpic->flags & MPIC_PRIMARY) 219 cpu = hard_smp_processor_id(); 220 221 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); 222 } 223 224 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) 225 { 226 unsigned int isu = src_no >> mpic->isu_shift; 227 unsigned int idx = src_no & mpic->isu_mask; 228 229 return _mpic_read(mpic->reg_type, &mpic->isus[isu], 230 reg + (idx * MPIC_INFO(IRQ_STRIDE))); 231 } 232 233 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, 234 unsigned int reg, u32 value) 235 { 236 unsigned int isu = src_no >> mpic->isu_shift; 237 unsigned int idx = src_no & mpic->isu_mask; 238 239 _mpic_write(mpic->reg_type, &mpic->isus[isu], 240 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); 241 } 242 243 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) 244 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) 245 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) 246 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) 247 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) 248 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) 249 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) 250 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) 251 252 253 /* 254 * Low level utility functions 255 */ 256 257 258 static void _mpic_map_mmio(struct mpic *mpic, unsigned long phys_addr, 259 struct mpic_reg_bank *rb, unsigned int offset, 260 unsigned int size) 261 { 262 rb->base = ioremap(phys_addr + offset, size); 263 BUG_ON(rb->base == NULL); 264 } 265 266 #ifdef CONFIG_PPC_DCR 267 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, 268 unsigned int offset, unsigned int size) 269 { 270 rb->dbase = mpic->dcr_base; 271 rb->doff = offset; 272 rb->dhost = dcr_map(mpic->of_node, rb->dbase + rb->doff, size); 273 BUG_ON(!DCR_MAP_OK(rb->dhost)); 274 } 275 276 static inline void mpic_map(struct mpic *mpic, unsigned long phys_addr, 277 struct mpic_reg_bank *rb, unsigned int offset, 278 unsigned int size) 279 { 280 if (mpic->flags & MPIC_USES_DCR) 281 _mpic_map_dcr(mpic, rb, offset, size); 282 else 283 _mpic_map_mmio(mpic, phys_addr, rb, offset, size); 284 } 285 #else /* CONFIG_PPC_DCR */ 286 #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) 287 #endif /* !CONFIG_PPC_DCR */ 288 289 290 291 /* Check if we have one of those nice broken MPICs with a flipped endian on 292 * reads from IPI registers 293 */ 294 static void __init mpic_test_broken_ipi(struct mpic *mpic) 295 { 296 u32 r; 297 298 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); 299 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); 300 301 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { 302 printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); 303 mpic->flags |= MPIC_BROKEN_IPI; 304 } 305 } 306 307 #ifdef CONFIG_MPIC_U3_HT_IRQS 308 309 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) 310 * to force the edge setting on the MPIC and do the ack workaround. 311 */ 312 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 313 { 314 if (source >= 128 || !mpic->fixups) 315 return 0; 316 return mpic->fixups[source].base != NULL; 317 } 318 319 320 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) 321 { 322 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 323 324 if (fixup->applebase) { 325 unsigned int soff = (fixup->index >> 3) & ~3; 326 unsigned int mask = 1U << (fixup->index & 0x1f); 327 writel(mask, fixup->applebase + soff); 328 } else { 329 spin_lock(&mpic->fixup_lock); 330 writeb(0x11 + 2 * fixup->index, fixup->base + 2); 331 writel(fixup->data, fixup->base + 4); 332 spin_unlock(&mpic->fixup_lock); 333 } 334 } 335 336 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, 337 unsigned int irqflags) 338 { 339 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 340 unsigned long flags; 341 u32 tmp; 342 343 if (fixup->base == NULL) 344 return; 345 346 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n", 347 source, irqflags, fixup->index); 348 spin_lock_irqsave(&mpic->fixup_lock, flags); 349 /* Enable and configure */ 350 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 351 tmp = readl(fixup->base + 4); 352 tmp &= ~(0x23U); 353 if (irqflags & IRQ_LEVEL) 354 tmp |= 0x22; 355 writel(tmp, fixup->base + 4); 356 spin_unlock_irqrestore(&mpic->fixup_lock, flags); 357 358 #ifdef CONFIG_PM 359 /* use the lowest bit inverted to the actual HW, 360 * set if this fixup was enabled, clear otherwise */ 361 mpic->save_data[source].fixup_data = tmp | 1; 362 #endif 363 } 364 365 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, 366 unsigned int irqflags) 367 { 368 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 369 unsigned long flags; 370 u32 tmp; 371 372 if (fixup->base == NULL) 373 return; 374 375 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags); 376 377 /* Disable */ 378 spin_lock_irqsave(&mpic->fixup_lock, flags); 379 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 380 tmp = readl(fixup->base + 4); 381 tmp |= 1; 382 writel(tmp, fixup->base + 4); 383 spin_unlock_irqrestore(&mpic->fixup_lock, flags); 384 385 #ifdef CONFIG_PM 386 /* use the lowest bit inverted to the actual HW, 387 * set if this fixup was enabled, clear otherwise */ 388 mpic->save_data[source].fixup_data = tmp & ~1; 389 #endif 390 } 391 392 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, 393 unsigned int devfn, u32 vdid) 394 { 395 int i, irq, n; 396 u8 __iomem *base; 397 u32 tmp; 398 u8 pos; 399 400 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 401 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 402 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 403 if (id == PCI_CAP_ID_HT) { 404 id = readb(devbase + pos + 3); 405 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) 406 break; 407 } 408 } 409 if (pos == 0) 410 return; 411 412 base = devbase + pos; 413 writeb(0x01, base + 2); 414 n = (readl(base + 4) >> 16) & 0xff; 415 416 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" 417 " has %d irqs\n", 418 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); 419 420 for (i = 0; i <= n; i++) { 421 writeb(0x10 + 2 * i, base + 2); 422 tmp = readl(base + 4); 423 irq = (tmp >> 16) & 0xff; 424 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); 425 /* mask it , will be unmasked later */ 426 tmp |= 0x1; 427 writel(tmp, base + 4); 428 mpic->fixups[irq].index = i; 429 mpic->fixups[irq].base = base; 430 /* Apple HT PIC has a non-standard way of doing EOIs */ 431 if ((vdid & 0xffff) == 0x106b) 432 mpic->fixups[irq].applebase = devbase + 0x60; 433 else 434 mpic->fixups[irq].applebase = NULL; 435 writeb(0x11 + 2 * i, base + 2); 436 mpic->fixups[irq].data = readl(base + 4) | 0x80000000; 437 } 438 } 439 440 441 static void __init mpic_scan_ht_pics(struct mpic *mpic) 442 { 443 unsigned int devfn; 444 u8 __iomem *cfgspace; 445 446 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); 447 448 /* Allocate fixups array */ 449 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup)); 450 BUG_ON(mpic->fixups == NULL); 451 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup)); 452 453 /* Init spinlock */ 454 spin_lock_init(&mpic->fixup_lock); 455 456 /* Map U3 config space. We assume all IO-APICs are on the primary bus 457 * so we only need to map 64kB. 458 */ 459 cfgspace = ioremap(0xf2000000, 0x10000); 460 BUG_ON(cfgspace == NULL); 461 462 /* Now we scan all slots. We do a very quick scan, we read the header 463 * type, vendor ID and device ID only, that's plenty enough 464 */ 465 for (devfn = 0; devfn < 0x100; devfn++) { 466 u8 __iomem *devbase = cfgspace + (devfn << 8); 467 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); 468 u32 l = readl(devbase + PCI_VENDOR_ID); 469 u16 s; 470 471 DBG("devfn %x, l: %x\n", devfn, l); 472 473 /* If no device, skip */ 474 if (l == 0xffffffff || l == 0x00000000 || 475 l == 0x0000ffff || l == 0xffff0000) 476 goto next; 477 /* Check if is supports capability lists */ 478 s = readw(devbase + PCI_STATUS); 479 if (!(s & PCI_STATUS_CAP_LIST)) 480 goto next; 481 482 mpic_scan_ht_pic(mpic, devbase, devfn, l); 483 484 next: 485 /* next device, if function 0 */ 486 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) 487 devfn += 7; 488 } 489 } 490 491 #else /* CONFIG_MPIC_U3_HT_IRQS */ 492 493 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 494 { 495 return 0; 496 } 497 498 static void __init mpic_scan_ht_pics(struct mpic *mpic) 499 { 500 } 501 502 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 503 504 505 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) 506 507 /* Find an mpic associated with a given linux interrupt */ 508 static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi) 509 { 510 unsigned int src = mpic_irq_to_hw(irq); 511 struct mpic *mpic; 512 513 if (irq < NUM_ISA_INTERRUPTS) 514 return NULL; 515 516 mpic = irq_desc[irq].chip_data; 517 518 if (is_ipi) 519 *is_ipi = (src >= mpic->ipi_vecs[0] && 520 src <= mpic->ipi_vecs[3]); 521 522 return mpic; 523 } 524 525 /* Convert a cpu mask from logical to physical cpu numbers. */ 526 static inline u32 mpic_physmask(u32 cpumask) 527 { 528 int i; 529 u32 mask = 0; 530 531 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1) 532 mask |= (cpumask & 1) << get_hard_smp_processor_id(i); 533 return mask; 534 } 535 536 #ifdef CONFIG_SMP 537 /* Get the mpic structure from the IPI number */ 538 static inline struct mpic * mpic_from_ipi(unsigned int ipi) 539 { 540 return irq_desc[ipi].chip_data; 541 } 542 #endif 543 544 /* Get the mpic structure from the irq number */ 545 static inline struct mpic * mpic_from_irq(unsigned int irq) 546 { 547 return irq_desc[irq].chip_data; 548 } 549 550 /* Send an EOI */ 551 static inline void mpic_eoi(struct mpic *mpic) 552 { 553 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); 554 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); 555 } 556 557 #ifdef CONFIG_SMP 558 static irqreturn_t mpic_ipi_action(int irq, void *dev_id) 559 { 560 struct mpic *mpic; 561 562 mpic = mpic_find(irq, NULL); 563 smp_message_recv(mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]); 564 565 return IRQ_HANDLED; 566 } 567 #endif /* CONFIG_SMP */ 568 569 /* 570 * Linux descriptor level callbacks 571 */ 572 573 574 static void mpic_unmask_irq(unsigned int irq) 575 { 576 unsigned int loops = 100000; 577 struct mpic *mpic = mpic_from_irq(irq); 578 unsigned int src = mpic_irq_to_hw(irq); 579 580 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src); 581 582 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 583 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & 584 ~MPIC_VECPRI_MASK); 585 /* make sure mask gets to controller before we return to user */ 586 do { 587 if (!loops--) { 588 printk(KERN_ERR "mpic_enable_irq timeout\n"); 589 break; 590 } 591 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); 592 } 593 594 static void mpic_mask_irq(unsigned int irq) 595 { 596 unsigned int loops = 100000; 597 struct mpic *mpic = mpic_from_irq(irq); 598 unsigned int src = mpic_irq_to_hw(irq); 599 600 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); 601 602 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 603 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | 604 MPIC_VECPRI_MASK); 605 606 /* make sure mask gets to controller before we return to user */ 607 do { 608 if (!loops--) { 609 printk(KERN_ERR "mpic_enable_irq timeout\n"); 610 break; 611 } 612 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); 613 } 614 615 static void mpic_end_irq(unsigned int irq) 616 { 617 struct mpic *mpic = mpic_from_irq(irq); 618 619 #ifdef DEBUG_IRQ 620 DBG("%s: end_irq: %d\n", mpic->name, irq); 621 #endif 622 /* We always EOI on end_irq() even for edge interrupts since that 623 * should only lower the priority, the MPIC should have properly 624 * latched another edge interrupt coming in anyway 625 */ 626 627 mpic_eoi(mpic); 628 } 629 630 #ifdef CONFIG_MPIC_U3_HT_IRQS 631 632 static void mpic_unmask_ht_irq(unsigned int irq) 633 { 634 struct mpic *mpic = mpic_from_irq(irq); 635 unsigned int src = mpic_irq_to_hw(irq); 636 637 mpic_unmask_irq(irq); 638 639 if (irq_desc[irq].status & IRQ_LEVEL) 640 mpic_ht_end_irq(mpic, src); 641 } 642 643 static unsigned int mpic_startup_ht_irq(unsigned int irq) 644 { 645 struct mpic *mpic = mpic_from_irq(irq); 646 unsigned int src = mpic_irq_to_hw(irq); 647 648 mpic_unmask_irq(irq); 649 mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status); 650 651 return 0; 652 } 653 654 static void mpic_shutdown_ht_irq(unsigned int irq) 655 { 656 struct mpic *mpic = mpic_from_irq(irq); 657 unsigned int src = mpic_irq_to_hw(irq); 658 659 mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status); 660 mpic_mask_irq(irq); 661 } 662 663 static void mpic_end_ht_irq(unsigned int irq) 664 { 665 struct mpic *mpic = mpic_from_irq(irq); 666 unsigned int src = mpic_irq_to_hw(irq); 667 668 #ifdef DEBUG_IRQ 669 DBG("%s: end_irq: %d\n", mpic->name, irq); 670 #endif 671 /* We always EOI on end_irq() even for edge interrupts since that 672 * should only lower the priority, the MPIC should have properly 673 * latched another edge interrupt coming in anyway 674 */ 675 676 if (irq_desc[irq].status & IRQ_LEVEL) 677 mpic_ht_end_irq(mpic, src); 678 mpic_eoi(mpic); 679 } 680 #endif /* !CONFIG_MPIC_U3_HT_IRQS */ 681 682 #ifdef CONFIG_SMP 683 684 static void mpic_unmask_ipi(unsigned int irq) 685 { 686 struct mpic *mpic = mpic_from_ipi(irq); 687 unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]; 688 689 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src); 690 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); 691 } 692 693 static void mpic_mask_ipi(unsigned int irq) 694 { 695 /* NEVER disable an IPI... that's just plain wrong! */ 696 } 697 698 static void mpic_end_ipi(unsigned int irq) 699 { 700 struct mpic *mpic = mpic_from_ipi(irq); 701 702 /* 703 * IPIs are marked IRQ_PER_CPU. This has the side effect of 704 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from 705 * applying to them. We EOI them late to avoid re-entering. 706 * We mark IPI's with IRQF_DISABLED as they must run with 707 * irqs disabled. 708 */ 709 mpic_eoi(mpic); 710 } 711 712 #endif /* CONFIG_SMP */ 713 714 static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask) 715 { 716 struct mpic *mpic = mpic_from_irq(irq); 717 unsigned int src = mpic_irq_to_hw(irq); 718 719 cpumask_t tmp; 720 721 cpus_and(tmp, cpumask, cpu_online_map); 722 723 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 724 mpic_physmask(cpus_addr(tmp)[0])); 725 } 726 727 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) 728 { 729 /* Now convert sense value */ 730 switch(type & IRQ_TYPE_SENSE_MASK) { 731 case IRQ_TYPE_EDGE_RISING: 732 return MPIC_INFO(VECPRI_SENSE_EDGE) | 733 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 734 case IRQ_TYPE_EDGE_FALLING: 735 case IRQ_TYPE_EDGE_BOTH: 736 return MPIC_INFO(VECPRI_SENSE_EDGE) | 737 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 738 case IRQ_TYPE_LEVEL_HIGH: 739 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 740 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 741 case IRQ_TYPE_LEVEL_LOW: 742 default: 743 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 744 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 745 } 746 } 747 748 static int mpic_set_irq_type(unsigned int virq, unsigned int flow_type) 749 { 750 struct mpic *mpic = mpic_from_irq(virq); 751 unsigned int src = mpic_irq_to_hw(virq); 752 struct irq_desc *desc = get_irq_desc(virq); 753 unsigned int vecpri, vold, vnew; 754 755 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", 756 mpic, virq, src, flow_type); 757 758 if (src >= mpic->irq_count) 759 return -EINVAL; 760 761 if (flow_type == IRQ_TYPE_NONE) 762 if (mpic->senses && src < mpic->senses_count) 763 flow_type = mpic->senses[src]; 764 if (flow_type == IRQ_TYPE_NONE) 765 flow_type = IRQ_TYPE_LEVEL_LOW; 766 767 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 768 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; 769 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 770 desc->status |= IRQ_LEVEL; 771 772 if (mpic_is_ht_interrupt(mpic, src)) 773 vecpri = MPIC_VECPRI_POLARITY_POSITIVE | 774 MPIC_VECPRI_SENSE_EDGE; 775 else 776 vecpri = mpic_type_to_vecpri(mpic, flow_type); 777 778 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 779 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | 780 MPIC_INFO(VECPRI_SENSE_MASK)); 781 vnew |= vecpri; 782 if (vold != vnew) 783 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); 784 785 return 0; 786 } 787 788 static struct irq_chip mpic_irq_chip = { 789 .mask = mpic_mask_irq, 790 .unmask = mpic_unmask_irq, 791 .eoi = mpic_end_irq, 792 .set_type = mpic_set_irq_type, 793 }; 794 795 #ifdef CONFIG_SMP 796 static struct irq_chip mpic_ipi_chip = { 797 .mask = mpic_mask_ipi, 798 .unmask = mpic_unmask_ipi, 799 .eoi = mpic_end_ipi, 800 }; 801 #endif /* CONFIG_SMP */ 802 803 #ifdef CONFIG_MPIC_U3_HT_IRQS 804 static struct irq_chip mpic_irq_ht_chip = { 805 .startup = mpic_startup_ht_irq, 806 .shutdown = mpic_shutdown_ht_irq, 807 .mask = mpic_mask_irq, 808 .unmask = mpic_unmask_ht_irq, 809 .eoi = mpic_end_ht_irq, 810 .set_type = mpic_set_irq_type, 811 }; 812 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 813 814 815 static int mpic_host_match(struct irq_host *h, struct device_node *node) 816 { 817 struct mpic *mpic = h->host_data; 818 819 /* Exact match, unless mpic node is NULL */ 820 return mpic->of_node == NULL || mpic->of_node == node; 821 } 822 823 static int mpic_host_map(struct irq_host *h, unsigned int virq, 824 irq_hw_number_t hw) 825 { 826 struct mpic *mpic = h->host_data; 827 struct irq_chip *chip; 828 829 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); 830 831 if (hw == mpic->spurious_vec) 832 return -EINVAL; 833 834 #ifdef CONFIG_SMP 835 else if (hw >= mpic->ipi_vecs[0]) { 836 WARN_ON(!(mpic->flags & MPIC_PRIMARY)); 837 838 DBG("mpic: mapping as IPI\n"); 839 set_irq_chip_data(virq, mpic); 840 set_irq_chip_and_handler(virq, &mpic->hc_ipi, 841 handle_percpu_irq); 842 return 0; 843 } 844 #endif /* CONFIG_SMP */ 845 846 if (hw >= mpic->irq_count) 847 return -EINVAL; 848 849 /* Default chip */ 850 chip = &mpic->hc_irq; 851 852 #ifdef CONFIG_MPIC_U3_HT_IRQS 853 /* Check for HT interrupts, override vecpri */ 854 if (mpic_is_ht_interrupt(mpic, hw)) 855 chip = &mpic->hc_ht_irq; 856 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 857 858 DBG("mpic: mapping to irq chip @%p\n", chip); 859 860 set_irq_chip_data(virq, mpic); 861 set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq); 862 863 /* Set default irq type */ 864 set_irq_type(virq, IRQ_TYPE_NONE); 865 866 return 0; 867 } 868 869 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, 870 u32 *intspec, unsigned int intsize, 871 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 872 873 { 874 static unsigned char map_mpic_senses[4] = { 875 IRQ_TYPE_EDGE_RISING, 876 IRQ_TYPE_LEVEL_LOW, 877 IRQ_TYPE_LEVEL_HIGH, 878 IRQ_TYPE_EDGE_FALLING, 879 }; 880 881 *out_hwirq = intspec[0]; 882 if (intsize > 1) { 883 u32 mask = 0x3; 884 885 /* Apple invented a new race of encoding on machines with 886 * an HT APIC. They encode, among others, the index within 887 * the HT APIC. We don't care about it here since thankfully, 888 * it appears that they have the APIC already properly 889 * configured, and thus our current fixup code that reads the 890 * APIC config works fine. However, we still need to mask out 891 * bits in the specifier to make sure we only get bit 0 which 892 * is the level/edge bit (the only sense bit exposed by Apple), 893 * as their bit 1 means something else. 894 */ 895 if (machine_is(powermac)) 896 mask = 0x1; 897 *out_flags = map_mpic_senses[intspec[1] & mask]; 898 } else 899 *out_flags = IRQ_TYPE_NONE; 900 901 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", 902 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); 903 904 return 0; 905 } 906 907 static struct irq_host_ops mpic_host_ops = { 908 .match = mpic_host_match, 909 .map = mpic_host_map, 910 .xlate = mpic_host_xlate, 911 }; 912 913 /* 914 * Exported functions 915 */ 916 917 struct mpic * __init mpic_alloc(struct device_node *node, 918 phys_addr_t phys_addr, 919 unsigned int flags, 920 unsigned int isu_size, 921 unsigned int irq_count, 922 const char *name) 923 { 924 struct mpic *mpic; 925 u32 reg; 926 const char *vers; 927 int i; 928 int intvec_top; 929 u64 paddr = phys_addr; 930 931 mpic = alloc_bootmem(sizeof(struct mpic)); 932 if (mpic == NULL) 933 return NULL; 934 935 memset(mpic, 0, sizeof(struct mpic)); 936 mpic->name = name; 937 mpic->of_node = of_node_get(node); 938 939 mpic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, isu_size, 940 &mpic_host_ops, 941 flags & MPIC_LARGE_VECTORS ? 2048 : 256); 942 if (mpic->irqhost == NULL) { 943 of_node_put(node); 944 return NULL; 945 } 946 947 mpic->irqhost->host_data = mpic; 948 mpic->hc_irq = mpic_irq_chip; 949 mpic->hc_irq.typename = name; 950 if (flags & MPIC_PRIMARY) 951 mpic->hc_irq.set_affinity = mpic_set_affinity; 952 #ifdef CONFIG_MPIC_U3_HT_IRQS 953 mpic->hc_ht_irq = mpic_irq_ht_chip; 954 mpic->hc_ht_irq.typename = name; 955 if (flags & MPIC_PRIMARY) 956 mpic->hc_ht_irq.set_affinity = mpic_set_affinity; 957 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 958 959 #ifdef CONFIG_SMP 960 mpic->hc_ipi = mpic_ipi_chip; 961 mpic->hc_ipi.typename = name; 962 #endif /* CONFIG_SMP */ 963 964 mpic->flags = flags; 965 mpic->isu_size = isu_size; 966 mpic->irq_count = irq_count; 967 mpic->num_sources = 0; /* so far */ 968 969 if (flags & MPIC_LARGE_VECTORS) 970 intvec_top = 2047; 971 else 972 intvec_top = 255; 973 974 mpic->timer_vecs[0] = intvec_top - 8; 975 mpic->timer_vecs[1] = intvec_top - 7; 976 mpic->timer_vecs[2] = intvec_top - 6; 977 mpic->timer_vecs[3] = intvec_top - 5; 978 mpic->ipi_vecs[0] = intvec_top - 4; 979 mpic->ipi_vecs[1] = intvec_top - 3; 980 mpic->ipi_vecs[2] = intvec_top - 2; 981 mpic->ipi_vecs[3] = intvec_top - 1; 982 mpic->spurious_vec = intvec_top; 983 984 /* Check for "big-endian" in device-tree */ 985 if (node && of_get_property(node, "big-endian", NULL) != NULL) 986 mpic->flags |= MPIC_BIG_ENDIAN; 987 988 989 #ifdef CONFIG_MPIC_WEIRD 990 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)]; 991 #endif 992 993 /* default register type */ 994 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ? 995 mpic_access_mmio_be : mpic_access_mmio_le; 996 997 /* If no physical address is passed in, a device-node is mandatory */ 998 BUG_ON(paddr == 0 && node == NULL); 999 1000 /* If no physical address passed in, check if it's dcr based */ 1001 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) 1002 mpic->flags |= MPIC_USES_DCR; 1003 1004 #ifdef CONFIG_PPC_DCR 1005 if (mpic->flags & MPIC_USES_DCR) { 1006 const u32 *dbasep; 1007 dbasep = of_get_property(node, "dcr-reg", NULL); 1008 BUG_ON(dbasep == NULL); 1009 mpic->dcr_base = *dbasep; 1010 mpic->reg_type = mpic_access_dcr; 1011 } 1012 #else 1013 BUG_ON (mpic->flags & MPIC_USES_DCR); 1014 #endif /* CONFIG_PPC_DCR */ 1015 1016 /* If the MPIC is not DCR based, and no physical address was passed 1017 * in, try to obtain one 1018 */ 1019 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) { 1020 const u32 *reg; 1021 reg = of_get_property(node, "reg", NULL); 1022 BUG_ON(reg == NULL); 1023 paddr = of_translate_address(node, reg); 1024 BUG_ON(paddr == OF_BAD_ADDR); 1025 } 1026 1027 /* Map the global registers */ 1028 mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); 1029 mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); 1030 1031 /* Reset */ 1032 if (flags & MPIC_WANTS_RESET) { 1033 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1034 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1035 | MPIC_GREG_GCONF_RESET); 1036 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1037 & MPIC_GREG_GCONF_RESET) 1038 mb(); 1039 } 1040 1041 /* Read feature register, calculate num CPUs and, for non-ISU 1042 * MPICs, num sources as well. On ISU MPICs, sources are counted 1043 * as ISUs are added 1044 */ 1045 reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); 1046 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK) 1047 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; 1048 if (isu_size == 0) 1049 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK) 1050 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; 1051 1052 /* Map the per-CPU registers */ 1053 for (i = 0; i < mpic->num_cpus; i++) { 1054 mpic_map(mpic, paddr, &mpic->cpuregs[i], 1055 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), 1056 0x1000); 1057 } 1058 1059 /* Initialize main ISU if none provided */ 1060 if (mpic->isu_size == 0) { 1061 mpic->isu_size = mpic->num_sources; 1062 mpic_map(mpic, paddr, &mpic->isus[0], 1063 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1064 } 1065 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 1066 mpic->isu_mask = (1 << mpic->isu_shift) - 1; 1067 1068 /* Display version */ 1069 switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) { 1070 case 1: 1071 vers = "1.0"; 1072 break; 1073 case 2: 1074 vers = "1.2"; 1075 break; 1076 case 3: 1077 vers = "1.3"; 1078 break; 1079 default: 1080 vers = "<unknown>"; 1081 break; 1082 } 1083 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," 1084 " max %d CPUs\n", 1085 name, vers, (unsigned long long)paddr, mpic->num_cpus); 1086 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", 1087 mpic->isu_size, mpic->isu_shift, mpic->isu_mask); 1088 1089 mpic->next = mpics; 1090 mpics = mpic; 1091 1092 if (flags & MPIC_PRIMARY) { 1093 mpic_primary = mpic; 1094 irq_set_default_host(mpic->irqhost); 1095 } 1096 1097 return mpic; 1098 } 1099 1100 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, 1101 phys_addr_t paddr) 1102 { 1103 unsigned int isu_first = isu_num * mpic->isu_size; 1104 1105 BUG_ON(isu_num >= MPIC_MAX_ISU); 1106 1107 mpic_map(mpic, paddr, &mpic->isus[isu_num], 0, 1108 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1109 if ((isu_first + mpic->isu_size) > mpic->num_sources) 1110 mpic->num_sources = isu_first + mpic->isu_size; 1111 } 1112 1113 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) 1114 { 1115 mpic->senses = senses; 1116 mpic->senses_count = count; 1117 } 1118 1119 void __init mpic_init(struct mpic *mpic) 1120 { 1121 int i; 1122 1123 BUG_ON(mpic->num_sources == 0); 1124 1125 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); 1126 1127 /* Set current processor priority to max */ 1128 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1129 1130 /* Initialize timers: just disable them all */ 1131 for (i = 0; i < 4; i++) { 1132 mpic_write(mpic->tmregs, 1133 i * MPIC_INFO(TIMER_STRIDE) + 1134 MPIC_INFO(TIMER_DESTINATION), 0); 1135 mpic_write(mpic->tmregs, 1136 i * MPIC_INFO(TIMER_STRIDE) + 1137 MPIC_INFO(TIMER_VECTOR_PRI), 1138 MPIC_VECPRI_MASK | 1139 (mpic->timer_vecs[0] + i)); 1140 } 1141 1142 /* Initialize IPIs to our reserved vectors and mark them disabled for now */ 1143 mpic_test_broken_ipi(mpic); 1144 for (i = 0; i < 4; i++) { 1145 mpic_ipi_write(i, 1146 MPIC_VECPRI_MASK | 1147 (10 << MPIC_VECPRI_PRIORITY_SHIFT) | 1148 (mpic->ipi_vecs[0] + i)); 1149 } 1150 1151 /* Initialize interrupt sources */ 1152 if (mpic->irq_count == 0) 1153 mpic->irq_count = mpic->num_sources; 1154 1155 /* Do the HT PIC fixups on U3 broken mpic */ 1156 DBG("MPIC flags: %x\n", mpic->flags); 1157 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) 1158 mpic_scan_ht_pics(mpic); 1159 1160 for (i = 0; i < mpic->num_sources; i++) { 1161 /* start with vector = source number, and masked */ 1162 u32 vecpri = MPIC_VECPRI_MASK | i | 1163 (8 << MPIC_VECPRI_PRIORITY_SHIFT); 1164 1165 /* init hw */ 1166 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 1167 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1168 1 << hard_smp_processor_id()); 1169 } 1170 1171 /* Init spurious vector */ 1172 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); 1173 1174 /* Disable 8259 passthrough, if supported */ 1175 if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) 1176 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1177 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1178 | MPIC_GREG_GCONF_8259_PTHROU_DIS); 1179 1180 /* Set current processor priority to 0 */ 1181 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 1182 1183 #ifdef CONFIG_PM 1184 /* allocate memory to save mpic state */ 1185 mpic->save_data = alloc_bootmem(mpic->num_sources * sizeof(struct mpic_irq_save)); 1186 BUG_ON(mpic->save_data == NULL); 1187 #endif 1188 } 1189 1190 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) 1191 { 1192 u32 v; 1193 1194 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1195 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; 1196 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); 1197 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1198 } 1199 1200 void __init mpic_set_serial_int(struct mpic *mpic, int enable) 1201 { 1202 unsigned long flags; 1203 u32 v; 1204 1205 spin_lock_irqsave(&mpic_lock, flags); 1206 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1207 if (enable) 1208 v |= MPIC_GREG_GLOBAL_CONF_1_SIE; 1209 else 1210 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; 1211 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1212 spin_unlock_irqrestore(&mpic_lock, flags); 1213 } 1214 1215 void mpic_irq_set_priority(unsigned int irq, unsigned int pri) 1216 { 1217 int is_ipi; 1218 struct mpic *mpic = mpic_find(irq, &is_ipi); 1219 unsigned int src = mpic_irq_to_hw(irq); 1220 unsigned long flags; 1221 u32 reg; 1222 1223 spin_lock_irqsave(&mpic_lock, flags); 1224 if (is_ipi) { 1225 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & 1226 ~MPIC_VECPRI_PRIORITY_MASK; 1227 mpic_ipi_write(src - mpic->ipi_vecs[0], 1228 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1229 } else { 1230 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) 1231 & ~MPIC_VECPRI_PRIORITY_MASK; 1232 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 1233 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1234 } 1235 spin_unlock_irqrestore(&mpic_lock, flags); 1236 } 1237 1238 unsigned int mpic_irq_get_priority(unsigned int irq) 1239 { 1240 int is_ipi; 1241 struct mpic *mpic = mpic_find(irq, &is_ipi); 1242 unsigned int src = mpic_irq_to_hw(irq); 1243 unsigned long flags; 1244 u32 reg; 1245 1246 spin_lock_irqsave(&mpic_lock, flags); 1247 if (is_ipi) 1248 reg = mpic_ipi_read(src = mpic->ipi_vecs[0]); 1249 else 1250 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 1251 spin_unlock_irqrestore(&mpic_lock, flags); 1252 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT; 1253 } 1254 1255 void mpic_setup_this_cpu(void) 1256 { 1257 #ifdef CONFIG_SMP 1258 struct mpic *mpic = mpic_primary; 1259 unsigned long flags; 1260 u32 msk = 1 << hard_smp_processor_id(); 1261 unsigned int i; 1262 1263 BUG_ON(mpic == NULL); 1264 1265 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1266 1267 spin_lock_irqsave(&mpic_lock, flags); 1268 1269 /* let the mpic know we want intrs. default affinity is 0xffffffff 1270 * until changed via /proc. That's how it's done on x86. If we want 1271 * it differently, then we should make sure we also change the default 1272 * values of irq_desc[].affinity in irq.c. 1273 */ 1274 if (distribute_irqs) { 1275 for (i = 0; i < mpic->num_sources ; i++) 1276 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1277 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); 1278 } 1279 1280 /* Set current processor priority to 0 */ 1281 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 1282 1283 spin_unlock_irqrestore(&mpic_lock, flags); 1284 #endif /* CONFIG_SMP */ 1285 } 1286 1287 int mpic_cpu_get_priority(void) 1288 { 1289 struct mpic *mpic = mpic_primary; 1290 1291 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); 1292 } 1293 1294 void mpic_cpu_set_priority(int prio) 1295 { 1296 struct mpic *mpic = mpic_primary; 1297 1298 prio &= MPIC_CPU_TASKPRI_MASK; 1299 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); 1300 } 1301 1302 /* 1303 * XXX: someone who knows mpic should check this. 1304 * do we need to eoi the ipi including for kexec cpu here (see xics comments)? 1305 * or can we reset the mpic in the new kernel? 1306 */ 1307 void mpic_teardown_this_cpu(int secondary) 1308 { 1309 struct mpic *mpic = mpic_primary; 1310 unsigned long flags; 1311 u32 msk = 1 << hard_smp_processor_id(); 1312 unsigned int i; 1313 1314 BUG_ON(mpic == NULL); 1315 1316 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1317 spin_lock_irqsave(&mpic_lock, flags); 1318 1319 /* let the mpic know we don't want intrs. */ 1320 for (i = 0; i < mpic->num_sources ; i++) 1321 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1322 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); 1323 1324 /* Set current processor priority to max */ 1325 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1326 1327 spin_unlock_irqrestore(&mpic_lock, flags); 1328 } 1329 1330 1331 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask) 1332 { 1333 struct mpic *mpic = mpic_primary; 1334 1335 BUG_ON(mpic == NULL); 1336 1337 #ifdef DEBUG_IPI 1338 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); 1339 #endif 1340 1341 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + 1342 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), 1343 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); 1344 } 1345 1346 unsigned int mpic_get_one_irq(struct mpic *mpic) 1347 { 1348 u32 src; 1349 1350 src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK); 1351 #ifdef DEBUG_LOW 1352 DBG("%s: get_one_irq(): %d\n", mpic->name, src); 1353 #endif 1354 if (unlikely(src == mpic->spurious_vec)) { 1355 if (mpic->flags & MPIC_SPV_EOI) 1356 mpic_eoi(mpic); 1357 return NO_IRQ; 1358 } 1359 return irq_linear_revmap(mpic->irqhost, src); 1360 } 1361 1362 unsigned int mpic_get_irq(void) 1363 { 1364 struct mpic *mpic = mpic_primary; 1365 1366 BUG_ON(mpic == NULL); 1367 1368 return mpic_get_one_irq(mpic); 1369 } 1370 1371 1372 #ifdef CONFIG_SMP 1373 void mpic_request_ipis(void) 1374 { 1375 struct mpic *mpic = mpic_primary; 1376 int i; 1377 static char *ipi_names[] = { 1378 "IPI0 (call function)", 1379 "IPI1 (reschedule)", 1380 "IPI2 (unused)", 1381 "IPI3 (debugger break)", 1382 }; 1383 BUG_ON(mpic == NULL); 1384 1385 printk(KERN_INFO "mpic: requesting IPIs ... \n"); 1386 1387 for (i = 0; i < 4; i++) { 1388 unsigned int vipi = irq_create_mapping(mpic->irqhost, 1389 mpic->ipi_vecs[0] + i); 1390 if (vipi == NO_IRQ) { 1391 printk(KERN_ERR "Failed to map IPI %d\n", i); 1392 break; 1393 } 1394 request_irq(vipi, mpic_ipi_action, IRQF_DISABLED|IRQF_PERCPU, 1395 ipi_names[i], mpic); 1396 } 1397 } 1398 1399 void smp_mpic_message_pass(int target, int msg) 1400 { 1401 /* make sure we're sending something that translates to an IPI */ 1402 if ((unsigned int)msg > 3) { 1403 printk("SMP %d: smp_message_pass: unknown msg %d\n", 1404 smp_processor_id(), msg); 1405 return; 1406 } 1407 switch (target) { 1408 case MSG_ALL: 1409 mpic_send_ipi(msg, 0xffffffff); 1410 break; 1411 case MSG_ALL_BUT_SELF: 1412 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id())); 1413 break; 1414 default: 1415 mpic_send_ipi(msg, 1 << target); 1416 break; 1417 } 1418 } 1419 1420 int __init smp_mpic_probe(void) 1421 { 1422 int nr_cpus; 1423 1424 DBG("smp_mpic_probe()...\n"); 1425 1426 nr_cpus = cpus_weight(cpu_possible_map); 1427 1428 DBG("nr_cpus: %d\n", nr_cpus); 1429 1430 if (nr_cpus > 1) 1431 mpic_request_ipis(); 1432 1433 return nr_cpus; 1434 } 1435 1436 void __devinit smp_mpic_setup_cpu(int cpu) 1437 { 1438 mpic_setup_this_cpu(); 1439 } 1440 #endif /* CONFIG_SMP */ 1441 1442 #ifdef CONFIG_PM 1443 static int mpic_suspend(struct sys_device *dev, pm_message_t state) 1444 { 1445 struct mpic *mpic = container_of(dev, struct mpic, sysdev); 1446 int i; 1447 1448 for (i = 0; i < mpic->num_sources; i++) { 1449 mpic->save_data[i].vecprio = 1450 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); 1451 mpic->save_data[i].dest = 1452 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); 1453 } 1454 1455 return 0; 1456 } 1457 1458 static int mpic_resume(struct sys_device *dev) 1459 { 1460 struct mpic *mpic = container_of(dev, struct mpic, sysdev); 1461 int i; 1462 1463 for (i = 0; i < mpic->num_sources; i++) { 1464 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), 1465 mpic->save_data[i].vecprio); 1466 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1467 mpic->save_data[i].dest); 1468 1469 #ifdef CONFIG_MPIC_U3_HT_IRQS 1470 { 1471 struct mpic_irq_fixup *fixup = &mpic->fixups[i]; 1472 1473 if (fixup->base) { 1474 /* we use the lowest bit in an inverted meaning */ 1475 if ((mpic->save_data[i].fixup_data & 1) == 0) 1476 continue; 1477 1478 /* Enable and configure */ 1479 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 1480 1481 writel(mpic->save_data[i].fixup_data & ~1, 1482 fixup->base + 4); 1483 } 1484 } 1485 #endif 1486 } /* end for loop */ 1487 1488 return 0; 1489 } 1490 #endif 1491 1492 static struct sysdev_class mpic_sysclass = { 1493 #ifdef CONFIG_PM 1494 .resume = mpic_resume, 1495 .suspend = mpic_suspend, 1496 #endif 1497 set_kset_name("mpic"), 1498 }; 1499 1500 static int mpic_init_sys(void) 1501 { 1502 struct mpic *mpic = mpics; 1503 int error, id = 0; 1504 1505 error = sysdev_class_register(&mpic_sysclass); 1506 1507 while (mpic && !error) { 1508 mpic->sysdev.cls = &mpic_sysclass; 1509 mpic->sysdev.id = id++; 1510 error = sysdev_register(&mpic->sysdev); 1511 mpic = mpic->next; 1512 } 1513 return error; 1514 } 1515 1516 device_initcall(mpic_init_sys); 1517