1 /* 2 * arch/powerpc/kernel/mpic.c 3 * 4 * Driver for interrupt controllers following the OpenPIC standard, the 5 * common implementation beeing IBM's MPIC. This driver also can deal 6 * with various broken implementations of this HW. 7 * 8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file COPYING in the main directory of this archive 12 * for more details. 13 */ 14 15 #undef DEBUG 16 17 #include <linux/config.h> 18 #include <linux/types.h> 19 #include <linux/kernel.h> 20 #include <linux/init.h> 21 #include <linux/irq.h> 22 #include <linux/smp.h> 23 #include <linux/interrupt.h> 24 #include <linux/bootmem.h> 25 #include <linux/spinlock.h> 26 #include <linux/pci.h> 27 28 #include <asm/ptrace.h> 29 #include <asm/signal.h> 30 #include <asm/io.h> 31 #include <asm/pgtable.h> 32 #include <asm/irq.h> 33 #include <asm/machdep.h> 34 #include <asm/mpic.h> 35 #include <asm/smp.h> 36 37 #ifdef DEBUG 38 #define DBG(fmt...) printk(fmt) 39 #else 40 #define DBG(fmt...) 41 #endif 42 43 static struct mpic *mpics; 44 static struct mpic *mpic_primary; 45 static DEFINE_SPINLOCK(mpic_lock); 46 47 48 /* 49 * Register accessor functions 50 */ 51 52 53 static inline u32 _mpic_read(unsigned int be, volatile u32 __iomem *base, 54 unsigned int reg) 55 { 56 if (be) 57 return in_be32(base + (reg >> 2)); 58 else 59 return in_le32(base + (reg >> 2)); 60 } 61 62 static inline void _mpic_write(unsigned int be, volatile u32 __iomem *base, 63 unsigned int reg, u32 value) 64 { 65 if (be) 66 out_be32(base + (reg >> 2), value); 67 else 68 out_le32(base + (reg >> 2), value); 69 } 70 71 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) 72 { 73 unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0; 74 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10); 75 76 if (mpic->flags & MPIC_BROKEN_IPI) 77 be = !be; 78 return _mpic_read(be, mpic->gregs, offset); 79 } 80 81 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) 82 { 83 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10); 84 85 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value); 86 } 87 88 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) 89 { 90 unsigned int cpu = 0; 91 92 if (mpic->flags & MPIC_PRIMARY) 93 cpu = hard_smp_processor_id(); 94 95 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg); 96 } 97 98 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) 99 { 100 unsigned int cpu = 0; 101 102 if (mpic->flags & MPIC_PRIMARY) 103 cpu = hard_smp_processor_id(); 104 105 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg, value); 106 } 107 108 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) 109 { 110 unsigned int isu = src_no >> mpic->isu_shift; 111 unsigned int idx = src_no & mpic->isu_mask; 112 113 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu], 114 reg + (idx * MPIC_IRQ_STRIDE)); 115 } 116 117 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, 118 unsigned int reg, u32 value) 119 { 120 unsigned int isu = src_no >> mpic->isu_shift; 121 unsigned int idx = src_no & mpic->isu_mask; 122 123 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu], 124 reg + (idx * MPIC_IRQ_STRIDE), value); 125 } 126 127 #define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r)) 128 #define mpic_write(b,r,v) _mpic_write(mpic->flags & MPIC_BIG_ENDIAN,(b),(r),(v)) 129 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) 130 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) 131 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) 132 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) 133 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) 134 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) 135 136 137 /* 138 * Low level utility functions 139 */ 140 141 142 143 /* Check if we have one of those nice broken MPICs with a flipped endian on 144 * reads from IPI registers 145 */ 146 static void __init mpic_test_broken_ipi(struct mpic *mpic) 147 { 148 u32 r; 149 150 mpic_write(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0, MPIC_VECPRI_MASK); 151 r = mpic_read(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0); 152 153 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { 154 printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); 155 mpic->flags |= MPIC_BROKEN_IPI; 156 } 157 } 158 159 #ifdef CONFIG_MPIC_BROKEN_U3 160 161 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) 162 * to force the edge setting on the MPIC and do the ack workaround. 163 */ 164 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source_no) 165 { 166 if (source_no >= 128 || !mpic->fixups) 167 return 0; 168 return mpic->fixups[source_no].base != NULL; 169 } 170 171 static inline void mpic_apic_end_irq(struct mpic *mpic, unsigned int source_no) 172 { 173 struct mpic_irq_fixup *fixup = &mpic->fixups[source_no]; 174 u32 tmp; 175 176 spin_lock(&mpic->fixup_lock); 177 writeb(0x11 + 2 * fixup->irq, fixup->base); 178 tmp = readl(fixup->base + 2); 179 writel(tmp | 0x80000000ul, fixup->base + 2); 180 /* config writes shouldn't be posted but let's be safe ... */ 181 (void)readl(fixup->base + 2); 182 spin_unlock(&mpic->fixup_lock); 183 } 184 185 186 static void __init mpic_amd8111_read_irq(struct mpic *mpic, u8 __iomem *devbase) 187 { 188 int i, irq; 189 u32 tmp; 190 191 printk(KERN_INFO "mpic: - Workarounds on AMD 8111 @ %p\n", devbase); 192 193 for (i=0; i < 24; i++) { 194 writeb(0x10 + 2*i, devbase + 0xf2); 195 tmp = readl(devbase + 0xf4); 196 if ((tmp & 0x1) || !(tmp & 0x20)) 197 continue; 198 irq = (tmp >> 16) & 0xff; 199 mpic->fixups[irq].irq = i; 200 mpic->fixups[irq].base = devbase + 0xf2; 201 } 202 } 203 204 static void __init mpic_amd8131_read_irq(struct mpic *mpic, u8 __iomem *devbase) 205 { 206 int i, irq; 207 u32 tmp; 208 209 printk(KERN_INFO "mpic: - Workarounds on AMD 8131 @ %p\n", devbase); 210 211 for (i=0; i < 4; i++) { 212 writeb(0x10 + 2*i, devbase + 0xba); 213 tmp = readl(devbase + 0xbc); 214 if ((tmp & 0x1) || !(tmp & 0x20)) 215 continue; 216 irq = (tmp >> 16) & 0xff; 217 mpic->fixups[irq].irq = i; 218 mpic->fixups[irq].base = devbase + 0xba; 219 } 220 } 221 222 static void __init mpic_scan_ioapics(struct mpic *mpic) 223 { 224 unsigned int devfn; 225 u8 __iomem *cfgspace; 226 227 printk(KERN_INFO "mpic: Setting up IO-APICs workarounds for U3\n"); 228 229 /* Allocate fixups array */ 230 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup)); 231 BUG_ON(mpic->fixups == NULL); 232 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup)); 233 234 /* Init spinlock */ 235 spin_lock_init(&mpic->fixup_lock); 236 237 /* Map u3 config space. We assume all IO-APICs are on the primary bus 238 * and slot will never be above "0xf" so we only need to map 32k 239 */ 240 cfgspace = (unsigned char __iomem *)ioremap(0xf2000000, 0x8000); 241 BUG_ON(cfgspace == NULL); 242 243 /* Now we scan all slots. We do a very quick scan, we read the header type, 244 * vendor ID and device ID only, that's plenty enough 245 */ 246 for (devfn = 0; devfn < PCI_DEVFN(0x10,0); devfn ++) { 247 u8 __iomem *devbase = cfgspace + (devfn << 8); 248 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); 249 u32 l = readl(devbase + PCI_VENDOR_ID); 250 u16 vendor_id, device_id; 251 int multifunc = 0; 252 253 DBG("devfn %x, l: %x\n", devfn, l); 254 255 /* If no device, skip */ 256 if (l == 0xffffffff || l == 0x00000000 || 257 l == 0x0000ffff || l == 0xffff0000) 258 goto next; 259 260 /* Check if it's a multifunction device (only really used 261 * to function 0 though 262 */ 263 multifunc = !!(hdr_type & 0x80); 264 vendor_id = l & 0xffff; 265 device_id = (l >> 16) & 0xffff; 266 267 /* If a known device, go to fixup setup code */ 268 if (vendor_id == PCI_VENDOR_ID_AMD && device_id == 0x7460) 269 mpic_amd8111_read_irq(mpic, devbase); 270 if (vendor_id == PCI_VENDOR_ID_AMD && device_id == 0x7450) 271 mpic_amd8131_read_irq(mpic, devbase); 272 next: 273 /* next device, if function 0 */ 274 if ((PCI_FUNC(devfn) == 0) && !multifunc) 275 devfn += 7; 276 } 277 } 278 279 #endif /* CONFIG_MPIC_BROKEN_U3 */ 280 281 282 /* Find an mpic associated with a given linux interrupt */ 283 static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi) 284 { 285 struct mpic *mpic = mpics; 286 287 while(mpic) { 288 /* search IPIs first since they may override the main interrupts */ 289 if (irq >= mpic->ipi_offset && irq < (mpic->ipi_offset + 4)) { 290 if (is_ipi) 291 *is_ipi = 1; 292 return mpic; 293 } 294 if (irq >= mpic->irq_offset && 295 irq < (mpic->irq_offset + mpic->irq_count)) { 296 if (is_ipi) 297 *is_ipi = 0; 298 return mpic; 299 } 300 mpic = mpic -> next; 301 } 302 return NULL; 303 } 304 305 /* Convert a cpu mask from logical to physical cpu numbers. */ 306 static inline u32 mpic_physmask(u32 cpumask) 307 { 308 int i; 309 u32 mask = 0; 310 311 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1) 312 mask |= (cpumask & 1) << get_hard_smp_processor_id(i); 313 return mask; 314 } 315 316 #ifdef CONFIG_SMP 317 /* Get the mpic structure from the IPI number */ 318 static inline struct mpic * mpic_from_ipi(unsigned int ipi) 319 { 320 return container_of(irq_desc[ipi].handler, struct mpic, hc_ipi); 321 } 322 #endif 323 324 /* Get the mpic structure from the irq number */ 325 static inline struct mpic * mpic_from_irq(unsigned int irq) 326 { 327 return container_of(irq_desc[irq].handler, struct mpic, hc_irq); 328 } 329 330 /* Send an EOI */ 331 static inline void mpic_eoi(struct mpic *mpic) 332 { 333 mpic_cpu_write(MPIC_CPU_EOI, 0); 334 (void)mpic_cpu_read(MPIC_CPU_WHOAMI); 335 } 336 337 #ifdef CONFIG_SMP 338 static irqreturn_t mpic_ipi_action(int irq, void *dev_id, struct pt_regs *regs) 339 { 340 struct mpic *mpic = dev_id; 341 342 smp_message_recv(irq - mpic->ipi_offset, regs); 343 return IRQ_HANDLED; 344 } 345 #endif /* CONFIG_SMP */ 346 347 /* 348 * Linux descriptor level callbacks 349 */ 350 351 352 static void mpic_enable_irq(unsigned int irq) 353 { 354 unsigned int loops = 100000; 355 struct mpic *mpic = mpic_from_irq(irq); 356 unsigned int src = irq - mpic->irq_offset; 357 358 DBG("%s: enable_irq: %d (src %d)\n", mpic->name, irq, src); 359 360 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, 361 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & ~MPIC_VECPRI_MASK); 362 363 /* make sure mask gets to controller before we return to user */ 364 do { 365 if (!loops--) { 366 printk(KERN_ERR "mpic_enable_irq timeout\n"); 367 break; 368 } 369 } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK); 370 } 371 372 static void mpic_disable_irq(unsigned int irq) 373 { 374 unsigned int loops = 100000; 375 struct mpic *mpic = mpic_from_irq(irq); 376 unsigned int src = irq - mpic->irq_offset; 377 378 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); 379 380 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, 381 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) | MPIC_VECPRI_MASK); 382 383 /* make sure mask gets to controller before we return to user */ 384 do { 385 if (!loops--) { 386 printk(KERN_ERR "mpic_enable_irq timeout\n"); 387 break; 388 } 389 } while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK)); 390 } 391 392 static void mpic_end_irq(unsigned int irq) 393 { 394 struct mpic *mpic = mpic_from_irq(irq); 395 396 DBG("%s: end_irq: %d\n", mpic->name, irq); 397 398 /* We always EOI on end_irq() even for edge interrupts since that 399 * should only lower the priority, the MPIC should have properly 400 * latched another edge interrupt coming in anyway 401 */ 402 403 #ifdef CONFIG_MPIC_BROKEN_U3 404 if (mpic->flags & MPIC_BROKEN_U3) { 405 unsigned int src = irq - mpic->irq_offset; 406 if (mpic_is_ht_interrupt(mpic, src)) 407 mpic_apic_end_irq(mpic, src); 408 } 409 #endif /* CONFIG_MPIC_BROKEN_U3 */ 410 411 mpic_eoi(mpic); 412 } 413 414 #ifdef CONFIG_SMP 415 416 static void mpic_enable_ipi(unsigned int irq) 417 { 418 struct mpic *mpic = mpic_from_ipi(irq); 419 unsigned int src = irq - mpic->ipi_offset; 420 421 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src); 422 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); 423 } 424 425 static void mpic_disable_ipi(unsigned int irq) 426 { 427 /* NEVER disable an IPI... that's just plain wrong! */ 428 } 429 430 static void mpic_end_ipi(unsigned int irq) 431 { 432 struct mpic *mpic = mpic_from_ipi(irq); 433 434 /* 435 * IPIs are marked IRQ_PER_CPU. This has the side effect of 436 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from 437 * applying to them. We EOI them late to avoid re-entering. 438 * We mark IPI's with SA_INTERRUPT as they must run with 439 * irqs disabled. 440 */ 441 mpic_eoi(mpic); 442 } 443 444 #endif /* CONFIG_SMP */ 445 446 static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask) 447 { 448 struct mpic *mpic = mpic_from_irq(irq); 449 450 cpumask_t tmp; 451 452 cpus_and(tmp, cpumask, cpu_online_map); 453 454 mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_DESTINATION, 455 mpic_physmask(cpus_addr(tmp)[0])); 456 } 457 458 459 /* 460 * Exported functions 461 */ 462 463 464 struct mpic * __init mpic_alloc(unsigned long phys_addr, 465 unsigned int flags, 466 unsigned int isu_size, 467 unsigned int irq_offset, 468 unsigned int irq_count, 469 unsigned int ipi_offset, 470 unsigned char *senses, 471 unsigned int senses_count, 472 const char *name) 473 { 474 struct mpic *mpic; 475 u32 reg; 476 const char *vers; 477 int i; 478 479 mpic = alloc_bootmem(sizeof(struct mpic)); 480 if (mpic == NULL) 481 return NULL; 482 483 484 memset(mpic, 0, sizeof(struct mpic)); 485 mpic->name = name; 486 487 mpic->hc_irq.typename = name; 488 mpic->hc_irq.enable = mpic_enable_irq; 489 mpic->hc_irq.disable = mpic_disable_irq; 490 mpic->hc_irq.end = mpic_end_irq; 491 if (flags & MPIC_PRIMARY) 492 mpic->hc_irq.set_affinity = mpic_set_affinity; 493 #ifdef CONFIG_SMP 494 mpic->hc_ipi.typename = name; 495 mpic->hc_ipi.enable = mpic_enable_ipi; 496 mpic->hc_ipi.disable = mpic_disable_ipi; 497 mpic->hc_ipi.end = mpic_end_ipi; 498 #endif /* CONFIG_SMP */ 499 500 mpic->flags = flags; 501 mpic->isu_size = isu_size; 502 mpic->irq_offset = irq_offset; 503 mpic->irq_count = irq_count; 504 mpic->ipi_offset = ipi_offset; 505 mpic->num_sources = 0; /* so far */ 506 mpic->senses = senses; 507 mpic->senses_count = senses_count; 508 509 /* Map the global registers */ 510 mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000); 511 mpic->tmregs = mpic->gregs + (MPIC_TIMER_BASE >> 2); 512 BUG_ON(mpic->gregs == NULL); 513 514 /* Reset */ 515 if (flags & MPIC_WANTS_RESET) { 516 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0, 517 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) 518 | MPIC_GREG_GCONF_RESET); 519 while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) 520 & MPIC_GREG_GCONF_RESET) 521 mb(); 522 } 523 524 /* Read feature register, calculate num CPUs and, for non-ISU 525 * MPICs, num sources as well. On ISU MPICs, sources are counted 526 * as ISUs are added 527 */ 528 reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0); 529 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK) 530 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; 531 if (isu_size == 0) 532 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK) 533 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; 534 535 /* Map the per-CPU registers */ 536 for (i = 0; i < mpic->num_cpus; i++) { 537 mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE + 538 i * MPIC_CPU_STRIDE, 0x1000); 539 BUG_ON(mpic->cpuregs[i] == NULL); 540 } 541 542 /* Initialize main ISU if none provided */ 543 if (mpic->isu_size == 0) { 544 mpic->isu_size = mpic->num_sources; 545 mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE, 546 MPIC_IRQ_STRIDE * mpic->isu_size); 547 BUG_ON(mpic->isus[0] == NULL); 548 } 549 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 550 mpic->isu_mask = (1 << mpic->isu_shift) - 1; 551 552 /* Display version */ 553 switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) { 554 case 1: 555 vers = "1.0"; 556 break; 557 case 2: 558 vers = "1.2"; 559 break; 560 case 3: 561 vers = "1.3"; 562 break; 563 default: 564 vers = "<unknown>"; 565 break; 566 } 567 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %lx, max %d CPUs\n", 568 name, vers, phys_addr, mpic->num_cpus); 569 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", mpic->isu_size, 570 mpic->isu_shift, mpic->isu_mask); 571 572 mpic->next = mpics; 573 mpics = mpic; 574 575 if (flags & MPIC_PRIMARY) 576 mpic_primary = mpic; 577 578 return mpic; 579 } 580 581 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, 582 unsigned long phys_addr) 583 { 584 unsigned int isu_first = isu_num * mpic->isu_size; 585 586 BUG_ON(isu_num >= MPIC_MAX_ISU); 587 588 mpic->isus[isu_num] = ioremap(phys_addr, MPIC_IRQ_STRIDE * mpic->isu_size); 589 if ((isu_first + mpic->isu_size) > mpic->num_sources) 590 mpic->num_sources = isu_first + mpic->isu_size; 591 } 592 593 void __init mpic_setup_cascade(unsigned int irq, mpic_cascade_t handler, 594 void *data) 595 { 596 struct mpic *mpic = mpic_find(irq, NULL); 597 unsigned long flags; 598 599 /* Synchronization here is a bit dodgy, so don't try to replace cascade 600 * interrupts on the fly too often ... but normally it's set up at boot. 601 */ 602 spin_lock_irqsave(&mpic_lock, flags); 603 if (mpic->cascade) 604 mpic_disable_irq(mpic->cascade_vec + mpic->irq_offset); 605 mpic->cascade = NULL; 606 wmb(); 607 mpic->cascade_vec = irq - mpic->irq_offset; 608 mpic->cascade_data = data; 609 wmb(); 610 mpic->cascade = handler; 611 mpic_enable_irq(irq); 612 spin_unlock_irqrestore(&mpic_lock, flags); 613 } 614 615 void __init mpic_init(struct mpic *mpic) 616 { 617 int i; 618 619 BUG_ON(mpic->num_sources == 0); 620 621 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); 622 623 /* Set current processor priority to max */ 624 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf); 625 626 /* Initialize timers: just disable them all */ 627 for (i = 0; i < 4; i++) { 628 mpic_write(mpic->tmregs, 629 i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0); 630 mpic_write(mpic->tmregs, 631 i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI, 632 MPIC_VECPRI_MASK | 633 (MPIC_VEC_TIMER_0 + i)); 634 } 635 636 /* Initialize IPIs to our reserved vectors and mark them disabled for now */ 637 mpic_test_broken_ipi(mpic); 638 for (i = 0; i < 4; i++) { 639 mpic_ipi_write(i, 640 MPIC_VECPRI_MASK | 641 (10 << MPIC_VECPRI_PRIORITY_SHIFT) | 642 (MPIC_VEC_IPI_0 + i)); 643 #ifdef CONFIG_SMP 644 if (!(mpic->flags & MPIC_PRIMARY)) 645 continue; 646 irq_desc[mpic->ipi_offset+i].status |= IRQ_PER_CPU; 647 irq_desc[mpic->ipi_offset+i].handler = &mpic->hc_ipi; 648 649 #endif /* CONFIG_SMP */ 650 } 651 652 /* Initialize interrupt sources */ 653 if (mpic->irq_count == 0) 654 mpic->irq_count = mpic->num_sources; 655 656 #ifdef CONFIG_MPIC_BROKEN_U3 657 /* Do the ioapic fixups on U3 broken mpic */ 658 DBG("MPIC flags: %x\n", mpic->flags); 659 if ((mpic->flags & MPIC_BROKEN_U3) && (mpic->flags & MPIC_PRIMARY)) 660 mpic_scan_ioapics(mpic); 661 #endif /* CONFIG_MPIC_BROKEN_U3 */ 662 663 for (i = 0; i < mpic->num_sources; i++) { 664 /* start with vector = source number, and masked */ 665 u32 vecpri = MPIC_VECPRI_MASK | i | (8 << MPIC_VECPRI_PRIORITY_SHIFT); 666 int level = 0; 667 668 /* if it's an IPI, we skip it */ 669 if ((mpic->irq_offset + i) >= (mpic->ipi_offset + i) && 670 (mpic->irq_offset + i) < (mpic->ipi_offset + i + 4)) 671 continue; 672 673 /* do senses munging */ 674 if (mpic->senses && i < mpic->senses_count) { 675 if (mpic->senses[i] & IRQ_SENSE_LEVEL) 676 vecpri |= MPIC_VECPRI_SENSE_LEVEL; 677 if (mpic->senses[i] & IRQ_POLARITY_POSITIVE) 678 vecpri |= MPIC_VECPRI_POLARITY_POSITIVE; 679 } else 680 vecpri |= MPIC_VECPRI_SENSE_LEVEL; 681 682 /* remember if it was a level interrupts */ 683 level = (vecpri & MPIC_VECPRI_SENSE_LEVEL); 684 685 /* deal with broken U3 */ 686 if (mpic->flags & MPIC_BROKEN_U3) { 687 #ifdef CONFIG_MPIC_BROKEN_U3 688 if (mpic_is_ht_interrupt(mpic, i)) { 689 vecpri &= ~(MPIC_VECPRI_SENSE_MASK | 690 MPIC_VECPRI_POLARITY_MASK); 691 vecpri |= MPIC_VECPRI_POLARITY_POSITIVE; 692 } 693 #else 694 printk(KERN_ERR "mpic: BROKEN_U3 set, but CONFIG doesn't match\n"); 695 #endif 696 } 697 698 DBG("setup source %d, vecpri: %08x, level: %d\n", i, vecpri, 699 (level != 0)); 700 701 /* init hw */ 702 mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri); 703 mpic_irq_write(i, MPIC_IRQ_DESTINATION, 704 1 << hard_smp_processor_id()); 705 706 /* init linux descriptors */ 707 if (i < mpic->irq_count) { 708 irq_desc[mpic->irq_offset+i].status = level ? IRQ_LEVEL : 0; 709 irq_desc[mpic->irq_offset+i].handler = &mpic->hc_irq; 710 } 711 } 712 713 /* Init spurrious vector */ 714 mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS); 715 716 /* Disable 8259 passthrough */ 717 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0, 718 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) 719 | MPIC_GREG_GCONF_8259_PTHROU_DIS); 720 721 /* Set current processor priority to 0 */ 722 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0); 723 } 724 725 726 727 void mpic_irq_set_priority(unsigned int irq, unsigned int pri) 728 { 729 int is_ipi; 730 struct mpic *mpic = mpic_find(irq, &is_ipi); 731 unsigned long flags; 732 u32 reg; 733 734 spin_lock_irqsave(&mpic_lock, flags); 735 if (is_ipi) { 736 reg = mpic_ipi_read(irq - mpic->ipi_offset) & MPIC_VECPRI_PRIORITY_MASK; 737 mpic_ipi_write(irq - mpic->ipi_offset, 738 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 739 } else { 740 reg = mpic_irq_read(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI) 741 & MPIC_VECPRI_PRIORITY_MASK; 742 mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI, 743 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 744 } 745 spin_unlock_irqrestore(&mpic_lock, flags); 746 } 747 748 unsigned int mpic_irq_get_priority(unsigned int irq) 749 { 750 int is_ipi; 751 struct mpic *mpic = mpic_find(irq, &is_ipi); 752 unsigned long flags; 753 u32 reg; 754 755 spin_lock_irqsave(&mpic_lock, flags); 756 if (is_ipi) 757 reg = mpic_ipi_read(irq - mpic->ipi_offset); 758 else 759 reg = mpic_irq_read(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI); 760 spin_unlock_irqrestore(&mpic_lock, flags); 761 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT; 762 } 763 764 void mpic_setup_this_cpu(void) 765 { 766 #ifdef CONFIG_SMP 767 struct mpic *mpic = mpic_primary; 768 unsigned long flags; 769 u32 msk = 1 << hard_smp_processor_id(); 770 unsigned int i; 771 772 BUG_ON(mpic == NULL); 773 774 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 775 776 spin_lock_irqsave(&mpic_lock, flags); 777 778 /* let the mpic know we want intrs. default affinity is 0xffffffff 779 * until changed via /proc. That's how it's done on x86. If we want 780 * it differently, then we should make sure we also change the default 781 * values of irq_affinity in irq.c. 782 */ 783 if (distribute_irqs) { 784 for (i = 0; i < mpic->num_sources ; i++) 785 mpic_irq_write(i, MPIC_IRQ_DESTINATION, 786 mpic_irq_read(i, MPIC_IRQ_DESTINATION) | msk); 787 } 788 789 /* Set current processor priority to 0 */ 790 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0); 791 792 spin_unlock_irqrestore(&mpic_lock, flags); 793 #endif /* CONFIG_SMP */ 794 } 795 796 int mpic_cpu_get_priority(void) 797 { 798 struct mpic *mpic = mpic_primary; 799 800 return mpic_cpu_read(MPIC_CPU_CURRENT_TASK_PRI); 801 } 802 803 void mpic_cpu_set_priority(int prio) 804 { 805 struct mpic *mpic = mpic_primary; 806 807 prio &= MPIC_CPU_TASKPRI_MASK; 808 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, prio); 809 } 810 811 /* 812 * XXX: someone who knows mpic should check this. 813 * do we need to eoi the ipi including for kexec cpu here (see xics comments)? 814 * or can we reset the mpic in the new kernel? 815 */ 816 void mpic_teardown_this_cpu(int secondary) 817 { 818 struct mpic *mpic = mpic_primary; 819 unsigned long flags; 820 u32 msk = 1 << hard_smp_processor_id(); 821 unsigned int i; 822 823 BUG_ON(mpic == NULL); 824 825 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 826 spin_lock_irqsave(&mpic_lock, flags); 827 828 /* let the mpic know we don't want intrs. */ 829 for (i = 0; i < mpic->num_sources ; i++) 830 mpic_irq_write(i, MPIC_IRQ_DESTINATION, 831 mpic_irq_read(i, MPIC_IRQ_DESTINATION) & ~msk); 832 833 /* Set current processor priority to max */ 834 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf); 835 836 spin_unlock_irqrestore(&mpic_lock, flags); 837 } 838 839 840 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask) 841 { 842 struct mpic *mpic = mpic_primary; 843 844 BUG_ON(mpic == NULL); 845 846 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); 847 848 mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0 + ipi_no * 0x10, 849 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); 850 } 851 852 int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs) 853 { 854 u32 irq; 855 856 irq = mpic_cpu_read(MPIC_CPU_INTACK) & MPIC_VECPRI_VECTOR_MASK; 857 DBG("%s: get_one_irq(): %d\n", mpic->name, irq); 858 859 if (mpic->cascade && irq == mpic->cascade_vec) { 860 DBG("%s: cascading ...\n", mpic->name); 861 irq = mpic->cascade(regs, mpic->cascade_data); 862 mpic_eoi(mpic); 863 return irq; 864 } 865 if (unlikely(irq == MPIC_VEC_SPURRIOUS)) 866 return -1; 867 if (irq < MPIC_VEC_IPI_0) 868 return irq + mpic->irq_offset; 869 DBG("%s: ipi %d !\n", mpic->name, irq - MPIC_VEC_IPI_0); 870 return irq - MPIC_VEC_IPI_0 + mpic->ipi_offset; 871 } 872 873 int mpic_get_irq(struct pt_regs *regs) 874 { 875 struct mpic *mpic = mpic_primary; 876 877 BUG_ON(mpic == NULL); 878 879 return mpic_get_one_irq(mpic, regs); 880 } 881 882 883 #ifdef CONFIG_SMP 884 void mpic_request_ipis(void) 885 { 886 struct mpic *mpic = mpic_primary; 887 888 BUG_ON(mpic == NULL); 889 890 printk("requesting IPIs ... \n"); 891 892 /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */ 893 request_irq(mpic->ipi_offset+0, mpic_ipi_action, SA_INTERRUPT, 894 "IPI0 (call function)", mpic); 895 request_irq(mpic->ipi_offset+1, mpic_ipi_action, SA_INTERRUPT, 896 "IPI1 (reschedule)", mpic); 897 request_irq(mpic->ipi_offset+2, mpic_ipi_action, SA_INTERRUPT, 898 "IPI2 (unused)", mpic); 899 request_irq(mpic->ipi_offset+3, mpic_ipi_action, SA_INTERRUPT, 900 "IPI3 (debugger break)", mpic); 901 902 printk("IPIs requested... \n"); 903 } 904 #endif /* CONFIG_SMP */ 905