1 /* 2 * arch/powerpc/kernel/mpic.c 3 * 4 * Driver for interrupt controllers following the OpenPIC standard, the 5 * common implementation beeing IBM's MPIC. This driver also can deal 6 * with various broken implementations of this HW. 7 * 8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file COPYING in the main directory of this archive 12 * for more details. 13 */ 14 15 #undef DEBUG 16 #undef DEBUG_IPI 17 #undef DEBUG_IRQ 18 #undef DEBUG_LOW 19 20 #include <linux/types.h> 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/irq.h> 24 #include <linux/smp.h> 25 #include <linux/interrupt.h> 26 #include <linux/bootmem.h> 27 #include <linux/spinlock.h> 28 #include <linux/pci.h> 29 30 #include <asm/ptrace.h> 31 #include <asm/signal.h> 32 #include <asm/io.h> 33 #include <asm/pgtable.h> 34 #include <asm/irq.h> 35 #include <asm/machdep.h> 36 #include <asm/mpic.h> 37 #include <asm/smp.h> 38 39 #ifdef DEBUG 40 #define DBG(fmt...) printk(fmt) 41 #else 42 #define DBG(fmt...) 43 #endif 44 45 static struct mpic *mpics; 46 static struct mpic *mpic_primary; 47 static DEFINE_SPINLOCK(mpic_lock); 48 49 #ifdef CONFIG_PPC32 /* XXX for now */ 50 #ifdef CONFIG_IRQ_ALL_CPUS 51 #define distribute_irqs (1) 52 #else 53 #define distribute_irqs (0) 54 #endif 55 #endif 56 57 /* 58 * Register accessor functions 59 */ 60 61 62 static inline u32 _mpic_read(unsigned int be, volatile u32 __iomem *base, 63 unsigned int reg) 64 { 65 if (be) 66 return in_be32(base + (reg >> 2)); 67 else 68 return in_le32(base + (reg >> 2)); 69 } 70 71 static inline void _mpic_write(unsigned int be, volatile u32 __iomem *base, 72 unsigned int reg, u32 value) 73 { 74 if (be) 75 out_be32(base + (reg >> 2), value); 76 else 77 out_le32(base + (reg >> 2), value); 78 } 79 80 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) 81 { 82 unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0; 83 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10); 84 85 if (mpic->flags & MPIC_BROKEN_IPI) 86 be = !be; 87 return _mpic_read(be, mpic->gregs, offset); 88 } 89 90 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) 91 { 92 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10); 93 94 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value); 95 } 96 97 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) 98 { 99 unsigned int cpu = 0; 100 101 if (mpic->flags & MPIC_PRIMARY) 102 cpu = hard_smp_processor_id(); 103 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, 104 mpic->cpuregs[cpu], reg); 105 } 106 107 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) 108 { 109 unsigned int cpu = 0; 110 111 if (mpic->flags & MPIC_PRIMARY) 112 cpu = hard_smp_processor_id(); 113 114 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg, value); 115 } 116 117 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) 118 { 119 unsigned int isu = src_no >> mpic->isu_shift; 120 unsigned int idx = src_no & mpic->isu_mask; 121 122 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu], 123 reg + (idx * MPIC_IRQ_STRIDE)); 124 } 125 126 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, 127 unsigned int reg, u32 value) 128 { 129 unsigned int isu = src_no >> mpic->isu_shift; 130 unsigned int idx = src_no & mpic->isu_mask; 131 132 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu], 133 reg + (idx * MPIC_IRQ_STRIDE), value); 134 } 135 136 #define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r)) 137 #define mpic_write(b,r,v) _mpic_write(mpic->flags & MPIC_BIG_ENDIAN,(b),(r),(v)) 138 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) 139 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) 140 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) 141 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) 142 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) 143 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) 144 145 146 /* 147 * Low level utility functions 148 */ 149 150 151 152 /* Check if we have one of those nice broken MPICs with a flipped endian on 153 * reads from IPI registers 154 */ 155 static void __init mpic_test_broken_ipi(struct mpic *mpic) 156 { 157 u32 r; 158 159 mpic_write(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0, MPIC_VECPRI_MASK); 160 r = mpic_read(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0); 161 162 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { 163 printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); 164 mpic->flags |= MPIC_BROKEN_IPI; 165 } 166 } 167 168 #ifdef CONFIG_MPIC_BROKEN_U3 169 170 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) 171 * to force the edge setting on the MPIC and do the ack workaround. 172 */ 173 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 174 { 175 if (source >= 128 || !mpic->fixups) 176 return 0; 177 return mpic->fixups[source].base != NULL; 178 } 179 180 181 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) 182 { 183 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 184 185 if (fixup->applebase) { 186 unsigned int soff = (fixup->index >> 3) & ~3; 187 unsigned int mask = 1U << (fixup->index & 0x1f); 188 writel(mask, fixup->applebase + soff); 189 } else { 190 spin_lock(&mpic->fixup_lock); 191 writeb(0x11 + 2 * fixup->index, fixup->base + 2); 192 writel(fixup->data, fixup->base + 4); 193 spin_unlock(&mpic->fixup_lock); 194 } 195 } 196 197 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, 198 unsigned int irqflags) 199 { 200 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 201 unsigned long flags; 202 u32 tmp; 203 204 if (fixup->base == NULL) 205 return; 206 207 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n", 208 source, irqflags, fixup->index); 209 spin_lock_irqsave(&mpic->fixup_lock, flags); 210 /* Enable and configure */ 211 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 212 tmp = readl(fixup->base + 4); 213 tmp &= ~(0x23U); 214 if (irqflags & IRQ_LEVEL) 215 tmp |= 0x22; 216 writel(tmp, fixup->base + 4); 217 spin_unlock_irqrestore(&mpic->fixup_lock, flags); 218 } 219 220 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, 221 unsigned int irqflags) 222 { 223 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 224 unsigned long flags; 225 u32 tmp; 226 227 if (fixup->base == NULL) 228 return; 229 230 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags); 231 232 /* Disable */ 233 spin_lock_irqsave(&mpic->fixup_lock, flags); 234 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 235 tmp = readl(fixup->base + 4); 236 tmp |= 1; 237 writel(tmp, fixup->base + 4); 238 spin_unlock_irqrestore(&mpic->fixup_lock, flags); 239 } 240 241 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, 242 unsigned int devfn, u32 vdid) 243 { 244 int i, irq, n; 245 u8 __iomem *base; 246 u32 tmp; 247 u8 pos; 248 249 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 250 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 251 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 252 if (id == PCI_CAP_ID_HT_IRQCONF) { 253 id = readb(devbase + pos + 3); 254 if (id == 0x80) 255 break; 256 } 257 } 258 if (pos == 0) 259 return; 260 261 base = devbase + pos; 262 writeb(0x01, base + 2); 263 n = (readl(base + 4) >> 16) & 0xff; 264 265 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" 266 " has %d irqs\n", 267 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); 268 269 for (i = 0; i <= n; i++) { 270 writeb(0x10 + 2 * i, base + 2); 271 tmp = readl(base + 4); 272 irq = (tmp >> 16) & 0xff; 273 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); 274 /* mask it , will be unmasked later */ 275 tmp |= 0x1; 276 writel(tmp, base + 4); 277 mpic->fixups[irq].index = i; 278 mpic->fixups[irq].base = base; 279 /* Apple HT PIC has a non-standard way of doing EOIs */ 280 if ((vdid & 0xffff) == 0x106b) 281 mpic->fixups[irq].applebase = devbase + 0x60; 282 else 283 mpic->fixups[irq].applebase = NULL; 284 writeb(0x11 + 2 * i, base + 2); 285 mpic->fixups[irq].data = readl(base + 4) | 0x80000000; 286 } 287 } 288 289 290 static void __init mpic_scan_ht_pics(struct mpic *mpic) 291 { 292 unsigned int devfn; 293 u8 __iomem *cfgspace; 294 295 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); 296 297 /* Allocate fixups array */ 298 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup)); 299 BUG_ON(mpic->fixups == NULL); 300 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup)); 301 302 /* Init spinlock */ 303 spin_lock_init(&mpic->fixup_lock); 304 305 /* Map U3 config space. We assume all IO-APICs are on the primary bus 306 * so we only need to map 64kB. 307 */ 308 cfgspace = ioremap(0xf2000000, 0x10000); 309 BUG_ON(cfgspace == NULL); 310 311 /* Now we scan all slots. We do a very quick scan, we read the header 312 * type, vendor ID and device ID only, that's plenty enough 313 */ 314 for (devfn = 0; devfn < 0x100; devfn++) { 315 u8 __iomem *devbase = cfgspace + (devfn << 8); 316 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); 317 u32 l = readl(devbase + PCI_VENDOR_ID); 318 u16 s; 319 320 DBG("devfn %x, l: %x\n", devfn, l); 321 322 /* If no device, skip */ 323 if (l == 0xffffffff || l == 0x00000000 || 324 l == 0x0000ffff || l == 0xffff0000) 325 goto next; 326 /* Check if is supports capability lists */ 327 s = readw(devbase + PCI_STATUS); 328 if (!(s & PCI_STATUS_CAP_LIST)) 329 goto next; 330 331 mpic_scan_ht_pic(mpic, devbase, devfn, l); 332 333 next: 334 /* next device, if function 0 */ 335 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) 336 devfn += 7; 337 } 338 } 339 340 #else /* CONFIG_MPIC_BROKEN_U3 */ 341 342 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 343 { 344 return 0; 345 } 346 347 static void __init mpic_scan_ht_pics(struct mpic *mpic) 348 { 349 } 350 351 #endif /* CONFIG_MPIC_BROKEN_U3 */ 352 353 354 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) 355 356 /* Find an mpic associated with a given linux interrupt */ 357 static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi) 358 { 359 unsigned int src = mpic_irq_to_hw(irq); 360 361 if (irq < NUM_ISA_INTERRUPTS) 362 return NULL; 363 if (is_ipi) 364 *is_ipi = (src >= MPIC_VEC_IPI_0 && src <= MPIC_VEC_IPI_3); 365 366 return irq_desc[irq].chip_data; 367 } 368 369 /* Convert a cpu mask from logical to physical cpu numbers. */ 370 static inline u32 mpic_physmask(u32 cpumask) 371 { 372 int i; 373 u32 mask = 0; 374 375 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1) 376 mask |= (cpumask & 1) << get_hard_smp_processor_id(i); 377 return mask; 378 } 379 380 #ifdef CONFIG_SMP 381 /* Get the mpic structure from the IPI number */ 382 static inline struct mpic * mpic_from_ipi(unsigned int ipi) 383 { 384 return irq_desc[ipi].chip_data; 385 } 386 #endif 387 388 /* Get the mpic structure from the irq number */ 389 static inline struct mpic * mpic_from_irq(unsigned int irq) 390 { 391 return irq_desc[irq].chip_data; 392 } 393 394 /* Send an EOI */ 395 static inline void mpic_eoi(struct mpic *mpic) 396 { 397 mpic_cpu_write(MPIC_CPU_EOI, 0); 398 (void)mpic_cpu_read(MPIC_CPU_WHOAMI); 399 } 400 401 #ifdef CONFIG_SMP 402 static irqreturn_t mpic_ipi_action(int irq, void *dev_id, struct pt_regs *regs) 403 { 404 smp_message_recv(mpic_irq_to_hw(irq) - MPIC_VEC_IPI_0, regs); 405 return IRQ_HANDLED; 406 } 407 #endif /* CONFIG_SMP */ 408 409 /* 410 * Linux descriptor level callbacks 411 */ 412 413 414 static void mpic_unmask_irq(unsigned int irq) 415 { 416 unsigned int loops = 100000; 417 struct mpic *mpic = mpic_from_irq(irq); 418 unsigned int src = mpic_irq_to_hw(irq); 419 420 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src); 421 422 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, 423 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & 424 ~MPIC_VECPRI_MASK); 425 /* make sure mask gets to controller before we return to user */ 426 do { 427 if (!loops--) { 428 printk(KERN_ERR "mpic_enable_irq timeout\n"); 429 break; 430 } 431 } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK); 432 } 433 434 static void mpic_mask_irq(unsigned int irq) 435 { 436 unsigned int loops = 100000; 437 struct mpic *mpic = mpic_from_irq(irq); 438 unsigned int src = mpic_irq_to_hw(irq); 439 440 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); 441 442 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, 443 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) | 444 MPIC_VECPRI_MASK); 445 446 /* make sure mask gets to controller before we return to user */ 447 do { 448 if (!loops--) { 449 printk(KERN_ERR "mpic_enable_irq timeout\n"); 450 break; 451 } 452 } while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK)); 453 } 454 455 static void mpic_end_irq(unsigned int irq) 456 { 457 struct mpic *mpic = mpic_from_irq(irq); 458 459 #ifdef DEBUG_IRQ 460 DBG("%s: end_irq: %d\n", mpic->name, irq); 461 #endif 462 /* We always EOI on end_irq() even for edge interrupts since that 463 * should only lower the priority, the MPIC should have properly 464 * latched another edge interrupt coming in anyway 465 */ 466 467 mpic_eoi(mpic); 468 } 469 470 #ifdef CONFIG_MPIC_BROKEN_U3 471 472 static void mpic_unmask_ht_irq(unsigned int irq) 473 { 474 struct mpic *mpic = mpic_from_irq(irq); 475 unsigned int src = mpic_irq_to_hw(irq); 476 477 mpic_unmask_irq(irq); 478 479 if (irq_desc[irq].status & IRQ_LEVEL) 480 mpic_ht_end_irq(mpic, src); 481 } 482 483 static unsigned int mpic_startup_ht_irq(unsigned int irq) 484 { 485 struct mpic *mpic = mpic_from_irq(irq); 486 unsigned int src = mpic_irq_to_hw(irq); 487 488 mpic_unmask_irq(irq); 489 mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status); 490 491 return 0; 492 } 493 494 static void mpic_shutdown_ht_irq(unsigned int irq) 495 { 496 struct mpic *mpic = mpic_from_irq(irq); 497 unsigned int src = mpic_irq_to_hw(irq); 498 499 mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status); 500 mpic_mask_irq(irq); 501 } 502 503 static void mpic_end_ht_irq(unsigned int irq) 504 { 505 struct mpic *mpic = mpic_from_irq(irq); 506 unsigned int src = mpic_irq_to_hw(irq); 507 508 #ifdef DEBUG_IRQ 509 DBG("%s: end_irq: %d\n", mpic->name, irq); 510 #endif 511 /* We always EOI on end_irq() even for edge interrupts since that 512 * should only lower the priority, the MPIC should have properly 513 * latched another edge interrupt coming in anyway 514 */ 515 516 if (irq_desc[irq].status & IRQ_LEVEL) 517 mpic_ht_end_irq(mpic, src); 518 mpic_eoi(mpic); 519 } 520 #endif /* !CONFIG_MPIC_BROKEN_U3 */ 521 522 #ifdef CONFIG_SMP 523 524 static void mpic_unmask_ipi(unsigned int irq) 525 { 526 struct mpic *mpic = mpic_from_ipi(irq); 527 unsigned int src = mpic_irq_to_hw(irq) - MPIC_VEC_IPI_0; 528 529 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src); 530 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); 531 } 532 533 static void mpic_mask_ipi(unsigned int irq) 534 { 535 /* NEVER disable an IPI... that's just plain wrong! */ 536 } 537 538 static void mpic_end_ipi(unsigned int irq) 539 { 540 struct mpic *mpic = mpic_from_ipi(irq); 541 542 /* 543 * IPIs are marked IRQ_PER_CPU. This has the side effect of 544 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from 545 * applying to them. We EOI them late to avoid re-entering. 546 * We mark IPI's with IRQF_DISABLED as they must run with 547 * irqs disabled. 548 */ 549 mpic_eoi(mpic); 550 } 551 552 #endif /* CONFIG_SMP */ 553 554 static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask) 555 { 556 struct mpic *mpic = mpic_from_irq(irq); 557 unsigned int src = mpic_irq_to_hw(irq); 558 559 cpumask_t tmp; 560 561 cpus_and(tmp, cpumask, cpu_online_map); 562 563 mpic_irq_write(src, MPIC_IRQ_DESTINATION, 564 mpic_physmask(cpus_addr(tmp)[0])); 565 } 566 567 static unsigned int mpic_type_to_vecpri(unsigned int type) 568 { 569 /* Now convert sense value */ 570 switch(type & IRQ_TYPE_SENSE_MASK) { 571 case IRQ_TYPE_EDGE_RISING: 572 return MPIC_VECPRI_SENSE_EDGE | MPIC_VECPRI_POLARITY_POSITIVE; 573 case IRQ_TYPE_EDGE_FALLING: 574 case IRQ_TYPE_EDGE_BOTH: 575 return MPIC_VECPRI_SENSE_EDGE | MPIC_VECPRI_POLARITY_NEGATIVE; 576 case IRQ_TYPE_LEVEL_HIGH: 577 return MPIC_VECPRI_SENSE_LEVEL | MPIC_VECPRI_POLARITY_POSITIVE; 578 case IRQ_TYPE_LEVEL_LOW: 579 default: 580 return MPIC_VECPRI_SENSE_LEVEL | MPIC_VECPRI_POLARITY_NEGATIVE; 581 } 582 } 583 584 static int mpic_set_irq_type(unsigned int virq, unsigned int flow_type) 585 { 586 struct mpic *mpic = mpic_from_irq(virq); 587 unsigned int src = mpic_irq_to_hw(virq); 588 struct irq_desc *desc = get_irq_desc(virq); 589 unsigned int vecpri, vold, vnew; 590 591 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", 592 mpic, virq, src, flow_type); 593 594 if (src >= mpic->irq_count) 595 return -EINVAL; 596 597 if (flow_type == IRQ_TYPE_NONE) 598 if (mpic->senses && src < mpic->senses_count) 599 flow_type = mpic->senses[src]; 600 if (flow_type == IRQ_TYPE_NONE) 601 flow_type = IRQ_TYPE_LEVEL_LOW; 602 603 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 604 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; 605 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 606 desc->status |= IRQ_LEVEL; 607 608 if (mpic_is_ht_interrupt(mpic, src)) 609 vecpri = MPIC_VECPRI_POLARITY_POSITIVE | 610 MPIC_VECPRI_SENSE_EDGE; 611 else 612 vecpri = mpic_type_to_vecpri(flow_type); 613 614 vold = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI); 615 vnew = vold & ~(MPIC_VECPRI_POLARITY_MASK | MPIC_VECPRI_SENSE_MASK); 616 vnew |= vecpri; 617 if (vold != vnew) 618 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, vnew); 619 620 return 0; 621 } 622 623 static struct irq_chip mpic_irq_chip = { 624 .mask = mpic_mask_irq, 625 .unmask = mpic_unmask_irq, 626 .eoi = mpic_end_irq, 627 .set_type = mpic_set_irq_type, 628 }; 629 630 #ifdef CONFIG_SMP 631 static struct irq_chip mpic_ipi_chip = { 632 .mask = mpic_mask_ipi, 633 .unmask = mpic_unmask_ipi, 634 .eoi = mpic_end_ipi, 635 }; 636 #endif /* CONFIG_SMP */ 637 638 #ifdef CONFIG_MPIC_BROKEN_U3 639 static struct irq_chip mpic_irq_ht_chip = { 640 .startup = mpic_startup_ht_irq, 641 .shutdown = mpic_shutdown_ht_irq, 642 .mask = mpic_mask_irq, 643 .unmask = mpic_unmask_ht_irq, 644 .eoi = mpic_end_ht_irq, 645 .set_type = mpic_set_irq_type, 646 }; 647 #endif /* CONFIG_MPIC_BROKEN_U3 */ 648 649 650 static int mpic_host_match(struct irq_host *h, struct device_node *node) 651 { 652 struct mpic *mpic = h->host_data; 653 654 /* Exact match, unless mpic node is NULL */ 655 return mpic->of_node == NULL || mpic->of_node == node; 656 } 657 658 static int mpic_host_map(struct irq_host *h, unsigned int virq, 659 irq_hw_number_t hw) 660 { 661 struct mpic *mpic = h->host_data; 662 struct irq_chip *chip; 663 664 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); 665 666 if (hw == MPIC_VEC_SPURRIOUS) 667 return -EINVAL; 668 669 #ifdef CONFIG_SMP 670 else if (hw >= MPIC_VEC_IPI_0) { 671 WARN_ON(!(mpic->flags & MPIC_PRIMARY)); 672 673 DBG("mpic: mapping as IPI\n"); 674 set_irq_chip_data(virq, mpic); 675 set_irq_chip_and_handler(virq, &mpic->hc_ipi, 676 handle_percpu_irq); 677 return 0; 678 } 679 #endif /* CONFIG_SMP */ 680 681 if (hw >= mpic->irq_count) 682 return -EINVAL; 683 684 /* Default chip */ 685 chip = &mpic->hc_irq; 686 687 #ifdef CONFIG_MPIC_BROKEN_U3 688 /* Check for HT interrupts, override vecpri */ 689 if (mpic_is_ht_interrupt(mpic, hw)) 690 chip = &mpic->hc_ht_irq; 691 #endif /* CONFIG_MPIC_BROKEN_U3 */ 692 693 DBG("mpic: mapping to irq chip @%p\n", chip); 694 695 set_irq_chip_data(virq, mpic); 696 set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq); 697 698 /* Set default irq type */ 699 set_irq_type(virq, IRQ_TYPE_NONE); 700 701 return 0; 702 } 703 704 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, 705 u32 *intspec, unsigned int intsize, 706 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 707 708 { 709 static unsigned char map_mpic_senses[4] = { 710 IRQ_TYPE_EDGE_RISING, 711 IRQ_TYPE_LEVEL_LOW, 712 IRQ_TYPE_LEVEL_HIGH, 713 IRQ_TYPE_EDGE_FALLING, 714 }; 715 716 *out_hwirq = intspec[0]; 717 if (intsize > 1) { 718 u32 mask = 0x3; 719 720 /* Apple invented a new race of encoding on machines with 721 * an HT APIC. They encode, among others, the index within 722 * the HT APIC. We don't care about it here since thankfully, 723 * it appears that they have the APIC already properly 724 * configured, and thus our current fixup code that reads the 725 * APIC config works fine. However, we still need to mask out 726 * bits in the specifier to make sure we only get bit 0 which 727 * is the level/edge bit (the only sense bit exposed by Apple), 728 * as their bit 1 means something else. 729 */ 730 if (machine_is(powermac)) 731 mask = 0x1; 732 *out_flags = map_mpic_senses[intspec[1] & mask]; 733 } else 734 *out_flags = IRQ_TYPE_NONE; 735 736 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", 737 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); 738 739 return 0; 740 } 741 742 static struct irq_host_ops mpic_host_ops = { 743 .match = mpic_host_match, 744 .map = mpic_host_map, 745 .xlate = mpic_host_xlate, 746 }; 747 748 /* 749 * Exported functions 750 */ 751 752 struct mpic * __init mpic_alloc(struct device_node *node, 753 unsigned long phys_addr, 754 unsigned int flags, 755 unsigned int isu_size, 756 unsigned int irq_count, 757 const char *name) 758 { 759 struct mpic *mpic; 760 u32 reg; 761 const char *vers; 762 int i; 763 764 mpic = alloc_bootmem(sizeof(struct mpic)); 765 if (mpic == NULL) 766 return NULL; 767 768 memset(mpic, 0, sizeof(struct mpic)); 769 mpic->name = name; 770 mpic->of_node = node ? of_node_get(node) : NULL; 771 772 mpic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, 256, 773 &mpic_host_ops, 774 MPIC_VEC_SPURRIOUS); 775 if (mpic->irqhost == NULL) { 776 of_node_put(node); 777 return NULL; 778 } 779 780 mpic->irqhost->host_data = mpic; 781 mpic->hc_irq = mpic_irq_chip; 782 mpic->hc_irq.typename = name; 783 if (flags & MPIC_PRIMARY) 784 mpic->hc_irq.set_affinity = mpic_set_affinity; 785 #ifdef CONFIG_MPIC_BROKEN_U3 786 mpic->hc_ht_irq = mpic_irq_ht_chip; 787 mpic->hc_ht_irq.typename = name; 788 if (flags & MPIC_PRIMARY) 789 mpic->hc_ht_irq.set_affinity = mpic_set_affinity; 790 #endif /* CONFIG_MPIC_BROKEN_U3 */ 791 #ifdef CONFIG_SMP 792 mpic->hc_ipi = mpic_ipi_chip; 793 mpic->hc_ipi.typename = name; 794 #endif /* CONFIG_SMP */ 795 796 mpic->flags = flags; 797 mpic->isu_size = isu_size; 798 mpic->irq_count = irq_count; 799 mpic->num_sources = 0; /* so far */ 800 801 /* Map the global registers */ 802 mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000); 803 mpic->tmregs = mpic->gregs + ((MPIC_TIMER_BASE - MPIC_GREG_BASE) >> 2); 804 BUG_ON(mpic->gregs == NULL); 805 806 /* Reset */ 807 if (flags & MPIC_WANTS_RESET) { 808 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0, 809 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) 810 | MPIC_GREG_GCONF_RESET); 811 while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) 812 & MPIC_GREG_GCONF_RESET) 813 mb(); 814 } 815 816 /* Read feature register, calculate num CPUs and, for non-ISU 817 * MPICs, num sources as well. On ISU MPICs, sources are counted 818 * as ISUs are added 819 */ 820 reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0); 821 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK) 822 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; 823 if (isu_size == 0) 824 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK) 825 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; 826 827 /* Map the per-CPU registers */ 828 for (i = 0; i < mpic->num_cpus; i++) { 829 mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE + 830 i * MPIC_CPU_STRIDE, 0x1000); 831 BUG_ON(mpic->cpuregs[i] == NULL); 832 } 833 834 /* Initialize main ISU if none provided */ 835 if (mpic->isu_size == 0) { 836 mpic->isu_size = mpic->num_sources; 837 mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE, 838 MPIC_IRQ_STRIDE * mpic->isu_size); 839 BUG_ON(mpic->isus[0] == NULL); 840 } 841 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 842 mpic->isu_mask = (1 << mpic->isu_shift) - 1; 843 844 /* Display version */ 845 switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) { 846 case 1: 847 vers = "1.0"; 848 break; 849 case 2: 850 vers = "1.2"; 851 break; 852 case 3: 853 vers = "1.3"; 854 break; 855 default: 856 vers = "<unknown>"; 857 break; 858 } 859 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %lx, max %d CPUs\n", 860 name, vers, phys_addr, mpic->num_cpus); 861 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", mpic->isu_size, 862 mpic->isu_shift, mpic->isu_mask); 863 864 mpic->next = mpics; 865 mpics = mpic; 866 867 if (flags & MPIC_PRIMARY) { 868 mpic_primary = mpic; 869 irq_set_default_host(mpic->irqhost); 870 } 871 872 return mpic; 873 } 874 875 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, 876 unsigned long phys_addr) 877 { 878 unsigned int isu_first = isu_num * mpic->isu_size; 879 880 BUG_ON(isu_num >= MPIC_MAX_ISU); 881 882 mpic->isus[isu_num] = ioremap(phys_addr, MPIC_IRQ_STRIDE * mpic->isu_size); 883 if ((isu_first + mpic->isu_size) > mpic->num_sources) 884 mpic->num_sources = isu_first + mpic->isu_size; 885 } 886 887 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) 888 { 889 mpic->senses = senses; 890 mpic->senses_count = count; 891 } 892 893 void __init mpic_init(struct mpic *mpic) 894 { 895 int i; 896 897 BUG_ON(mpic->num_sources == 0); 898 WARN_ON(mpic->num_sources > MPIC_VEC_IPI_0); 899 900 /* Sanitize source count */ 901 if (mpic->num_sources > MPIC_VEC_IPI_0) 902 mpic->num_sources = MPIC_VEC_IPI_0; 903 904 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); 905 906 /* Set current processor priority to max */ 907 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf); 908 909 /* Initialize timers: just disable them all */ 910 for (i = 0; i < 4; i++) { 911 mpic_write(mpic->tmregs, 912 i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0); 913 mpic_write(mpic->tmregs, 914 i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI, 915 MPIC_VECPRI_MASK | 916 (MPIC_VEC_TIMER_0 + i)); 917 } 918 919 /* Initialize IPIs to our reserved vectors and mark them disabled for now */ 920 mpic_test_broken_ipi(mpic); 921 for (i = 0; i < 4; i++) { 922 mpic_ipi_write(i, 923 MPIC_VECPRI_MASK | 924 (10 << MPIC_VECPRI_PRIORITY_SHIFT) | 925 (MPIC_VEC_IPI_0 + i)); 926 } 927 928 /* Initialize interrupt sources */ 929 if (mpic->irq_count == 0) 930 mpic->irq_count = mpic->num_sources; 931 932 /* Do the HT PIC fixups on U3 broken mpic */ 933 DBG("MPIC flags: %x\n", mpic->flags); 934 if ((mpic->flags & MPIC_BROKEN_U3) && (mpic->flags & MPIC_PRIMARY)) 935 mpic_scan_ht_pics(mpic); 936 937 for (i = 0; i < mpic->num_sources; i++) { 938 /* start with vector = source number, and masked */ 939 u32 vecpri = MPIC_VECPRI_MASK | i | 940 (8 << MPIC_VECPRI_PRIORITY_SHIFT); 941 942 /* init hw */ 943 mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri); 944 mpic_irq_write(i, MPIC_IRQ_DESTINATION, 945 1 << hard_smp_processor_id()); 946 } 947 948 /* Init spurrious vector */ 949 mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS); 950 951 /* Disable 8259 passthrough */ 952 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0, 953 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) 954 | MPIC_GREG_GCONF_8259_PTHROU_DIS); 955 956 /* Set current processor priority to 0 */ 957 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0); 958 } 959 960 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) 961 { 962 u32 v; 963 964 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 965 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; 966 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); 967 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 968 } 969 970 void __init mpic_set_serial_int(struct mpic *mpic, int enable) 971 { 972 unsigned long flags; 973 u32 v; 974 975 spin_lock_irqsave(&mpic_lock, flags); 976 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 977 if (enable) 978 v |= MPIC_GREG_GLOBAL_CONF_1_SIE; 979 else 980 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; 981 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 982 spin_unlock_irqrestore(&mpic_lock, flags); 983 } 984 985 void mpic_irq_set_priority(unsigned int irq, unsigned int pri) 986 { 987 int is_ipi; 988 struct mpic *mpic = mpic_find(irq, &is_ipi); 989 unsigned int src = mpic_irq_to_hw(irq); 990 unsigned long flags; 991 u32 reg; 992 993 spin_lock_irqsave(&mpic_lock, flags); 994 if (is_ipi) { 995 reg = mpic_ipi_read(src - MPIC_VEC_IPI_0) & 996 ~MPIC_VECPRI_PRIORITY_MASK; 997 mpic_ipi_write(src - MPIC_VEC_IPI_0, 998 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 999 } else { 1000 reg = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) 1001 & ~MPIC_VECPRI_PRIORITY_MASK; 1002 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, 1003 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1004 } 1005 spin_unlock_irqrestore(&mpic_lock, flags); 1006 } 1007 1008 unsigned int mpic_irq_get_priority(unsigned int irq) 1009 { 1010 int is_ipi; 1011 struct mpic *mpic = mpic_find(irq, &is_ipi); 1012 unsigned int src = mpic_irq_to_hw(irq); 1013 unsigned long flags; 1014 u32 reg; 1015 1016 spin_lock_irqsave(&mpic_lock, flags); 1017 if (is_ipi) 1018 reg = mpic_ipi_read(src = MPIC_VEC_IPI_0); 1019 else 1020 reg = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI); 1021 spin_unlock_irqrestore(&mpic_lock, flags); 1022 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT; 1023 } 1024 1025 void mpic_setup_this_cpu(void) 1026 { 1027 #ifdef CONFIG_SMP 1028 struct mpic *mpic = mpic_primary; 1029 unsigned long flags; 1030 u32 msk = 1 << hard_smp_processor_id(); 1031 unsigned int i; 1032 1033 BUG_ON(mpic == NULL); 1034 1035 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1036 1037 spin_lock_irqsave(&mpic_lock, flags); 1038 1039 /* let the mpic know we want intrs. default affinity is 0xffffffff 1040 * until changed via /proc. That's how it's done on x86. If we want 1041 * it differently, then we should make sure we also change the default 1042 * values of irq_desc[].affinity in irq.c. 1043 */ 1044 if (distribute_irqs) { 1045 for (i = 0; i < mpic->num_sources ; i++) 1046 mpic_irq_write(i, MPIC_IRQ_DESTINATION, 1047 mpic_irq_read(i, MPIC_IRQ_DESTINATION) | msk); 1048 } 1049 1050 /* Set current processor priority to 0 */ 1051 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0); 1052 1053 spin_unlock_irqrestore(&mpic_lock, flags); 1054 #endif /* CONFIG_SMP */ 1055 } 1056 1057 int mpic_cpu_get_priority(void) 1058 { 1059 struct mpic *mpic = mpic_primary; 1060 1061 return mpic_cpu_read(MPIC_CPU_CURRENT_TASK_PRI); 1062 } 1063 1064 void mpic_cpu_set_priority(int prio) 1065 { 1066 struct mpic *mpic = mpic_primary; 1067 1068 prio &= MPIC_CPU_TASKPRI_MASK; 1069 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, prio); 1070 } 1071 1072 /* 1073 * XXX: someone who knows mpic should check this. 1074 * do we need to eoi the ipi including for kexec cpu here (see xics comments)? 1075 * or can we reset the mpic in the new kernel? 1076 */ 1077 void mpic_teardown_this_cpu(int secondary) 1078 { 1079 struct mpic *mpic = mpic_primary; 1080 unsigned long flags; 1081 u32 msk = 1 << hard_smp_processor_id(); 1082 unsigned int i; 1083 1084 BUG_ON(mpic == NULL); 1085 1086 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1087 spin_lock_irqsave(&mpic_lock, flags); 1088 1089 /* let the mpic know we don't want intrs. */ 1090 for (i = 0; i < mpic->num_sources ; i++) 1091 mpic_irq_write(i, MPIC_IRQ_DESTINATION, 1092 mpic_irq_read(i, MPIC_IRQ_DESTINATION) & ~msk); 1093 1094 /* Set current processor priority to max */ 1095 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf); 1096 1097 spin_unlock_irqrestore(&mpic_lock, flags); 1098 } 1099 1100 1101 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask) 1102 { 1103 struct mpic *mpic = mpic_primary; 1104 1105 BUG_ON(mpic == NULL); 1106 1107 #ifdef DEBUG_IPI 1108 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); 1109 #endif 1110 1111 mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0 + ipi_no * 0x10, 1112 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); 1113 } 1114 1115 unsigned int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs) 1116 { 1117 u32 src; 1118 1119 src = mpic_cpu_read(MPIC_CPU_INTACK) & MPIC_VECPRI_VECTOR_MASK; 1120 #ifdef DEBUG_LOW 1121 DBG("%s: get_one_irq(): %d\n", mpic->name, src); 1122 #endif 1123 if (unlikely(src == MPIC_VEC_SPURRIOUS)) 1124 return NO_IRQ; 1125 return irq_linear_revmap(mpic->irqhost, src); 1126 } 1127 1128 unsigned int mpic_get_irq(struct pt_regs *regs) 1129 { 1130 struct mpic *mpic = mpic_primary; 1131 1132 BUG_ON(mpic == NULL); 1133 1134 return mpic_get_one_irq(mpic, regs); 1135 } 1136 1137 1138 #ifdef CONFIG_SMP 1139 void mpic_request_ipis(void) 1140 { 1141 struct mpic *mpic = mpic_primary; 1142 int i; 1143 static char *ipi_names[] = { 1144 "IPI0 (call function)", 1145 "IPI1 (reschedule)", 1146 "IPI2 (unused)", 1147 "IPI3 (debugger break)", 1148 }; 1149 BUG_ON(mpic == NULL); 1150 1151 printk(KERN_INFO "mpic: requesting IPIs ... \n"); 1152 1153 for (i = 0; i < 4; i++) { 1154 unsigned int vipi = irq_create_mapping(mpic->irqhost, 1155 MPIC_VEC_IPI_0 + i); 1156 if (vipi == NO_IRQ) { 1157 printk(KERN_ERR "Failed to map IPI %d\n", i); 1158 break; 1159 } 1160 request_irq(vipi, mpic_ipi_action, IRQF_DISABLED, 1161 ipi_names[i], mpic); 1162 } 1163 } 1164 1165 void smp_mpic_message_pass(int target, int msg) 1166 { 1167 /* make sure we're sending something that translates to an IPI */ 1168 if ((unsigned int)msg > 3) { 1169 printk("SMP %d: smp_message_pass: unknown msg %d\n", 1170 smp_processor_id(), msg); 1171 return; 1172 } 1173 switch (target) { 1174 case MSG_ALL: 1175 mpic_send_ipi(msg, 0xffffffff); 1176 break; 1177 case MSG_ALL_BUT_SELF: 1178 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id())); 1179 break; 1180 default: 1181 mpic_send_ipi(msg, 1 << target); 1182 break; 1183 } 1184 } 1185 #endif /* CONFIG_SMP */ 1186