1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Support for indirect PCI bridges.
4  *
5  * Copyright (C) 1998 Gabriel Paubert.
6  */
7 
8 #include <linux/kernel.h>
9 #include <linux/pci.h>
10 #include <linux/delay.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 
14 #include <asm/io.h>
15 #include <asm/pci-bridge.h>
16 #include <asm/machdep.h>
17 
18 int __indirect_read_config(struct pci_controller *hose,
19 			   unsigned char bus_number, unsigned int devfn,
20 			   int offset, int len, u32 *val)
21 {
22 	volatile void __iomem *cfg_data;
23 	u8 cfg_type = 0;
24 	u32 bus_no, reg;
25 
26 	if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
27 		if (bus_number != hose->first_busno)
28 			return PCIBIOS_DEVICE_NOT_FOUND;
29 		if (devfn != 0)
30 			return PCIBIOS_DEVICE_NOT_FOUND;
31 	}
32 
33 	if (ppc_md.pci_exclude_device)
34 		if (ppc_md.pci_exclude_device(hose, bus_number, devfn))
35 			return PCIBIOS_DEVICE_NOT_FOUND;
36 
37 	if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
38 		if (bus_number != hose->first_busno)
39 			cfg_type = 1;
40 
41 	bus_no = (bus_number == hose->first_busno) ?
42 			hose->self_busno : bus_number;
43 
44 	if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
45 		reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
46 	else
47 		reg = offset & 0xfc;
48 
49 	if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
50 		out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
51 			 (devfn << 8) | reg | cfg_type));
52 	else
53 		out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
54 			 (devfn << 8) | reg | cfg_type));
55 
56 	/*
57 	 * Note: the caller has already checked that offset is
58 	 * suitably aligned and that len is 1, 2 or 4.
59 	 */
60 	cfg_data = hose->cfg_data + (offset & 3);
61 	switch (len) {
62 	case 1:
63 		*val = in_8(cfg_data);
64 		break;
65 	case 2:
66 		*val = in_le16(cfg_data);
67 		break;
68 	default:
69 		*val = in_le32(cfg_data);
70 		break;
71 	}
72 	return PCIBIOS_SUCCESSFUL;
73 }
74 
75 int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
76 			 int offset, int len, u32 *val)
77 {
78 	struct pci_controller *hose = pci_bus_to_host(bus);
79 
80 	return __indirect_read_config(hose, bus->number, devfn, offset, len,
81 				      val);
82 }
83 
84 int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
85 			  int offset, int len, u32 val)
86 {
87 	struct pci_controller *hose = pci_bus_to_host(bus);
88 	volatile void __iomem *cfg_data;
89 	u8 cfg_type = 0;
90 	u32 bus_no, reg;
91 
92 	if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
93 		if (bus->number != hose->first_busno)
94 			return PCIBIOS_DEVICE_NOT_FOUND;
95 		if (devfn != 0)
96 			return PCIBIOS_DEVICE_NOT_FOUND;
97 	}
98 
99 	if (ppc_md.pci_exclude_device)
100 		if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
101 			return PCIBIOS_DEVICE_NOT_FOUND;
102 
103 	if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
104 		if (bus->number != hose->first_busno)
105 			cfg_type = 1;
106 
107 	bus_no = (bus->number == hose->first_busno) ?
108 			hose->self_busno : bus->number;
109 
110 	if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
111 		reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
112 	else
113 		reg = offset & 0xfc;
114 
115 	if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
116 		out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
117 			 (devfn << 8) | reg | cfg_type));
118 	else
119 		out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
120 			 (devfn << 8) | reg | cfg_type));
121 
122 	/* suppress setting of PCI_PRIMARY_BUS */
123 	if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
124 		if ((offset == PCI_PRIMARY_BUS) &&
125 			(bus->number == hose->first_busno))
126 		val &= 0xffffff00;
127 
128 	/* Workaround for PCI_28 Errata in 440EPx/GRx */
129 	if ((hose->indirect_type & PPC_INDIRECT_TYPE_BROKEN_MRM) &&
130 			offset == PCI_CACHE_LINE_SIZE) {
131 		val = 0;
132 	}
133 
134 	/*
135 	 * Note: the caller has already checked that offset is
136 	 * suitably aligned and that len is 1, 2 or 4.
137 	 */
138 	cfg_data = hose->cfg_data + (offset & 3);
139 	switch (len) {
140 	case 1:
141 		out_8(cfg_data, val);
142 		break;
143 	case 2:
144 		out_le16(cfg_data, val);
145 		break;
146 	default:
147 		out_le32(cfg_data, val);
148 		break;
149 	}
150 	return PCIBIOS_SUCCESSFUL;
151 }
152 
153 static struct pci_ops indirect_pci_ops =
154 {
155 	.read = indirect_read_config,
156 	.write = indirect_write_config,
157 };
158 
159 void setup_indirect_pci(struct pci_controller *hose, resource_size_t cfg_addr,
160 			resource_size_t cfg_data, u32 flags)
161 {
162 	resource_size_t base = cfg_addr & PAGE_MASK;
163 	void __iomem *mbase;
164 
165 	mbase = ioremap(base, PAGE_SIZE);
166 	hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
167 	if ((cfg_data & PAGE_MASK) != base)
168 		mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
169 	hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
170 	hose->ops = &indirect_pci_ops;
171 	hose->indirect_type = flags;
172 }
173