1 #ifndef __PPC_FSL_SOC_H 2 #define __PPC_FSL_SOC_H 3 #ifdef __KERNEL__ 4 5 #include <asm/mmu.h> 6 7 struct spi_device; 8 9 extern phys_addr_t get_immrbase(void); 10 #if defined(CONFIG_CPM2) || defined(CONFIG_QUICC_ENGINE) || defined(CONFIG_8xx) 11 extern u32 get_brgfreq(void); 12 extern u32 get_baudrate(void); 13 #else 14 static inline u32 get_brgfreq(void) { return -1; } 15 static inline u32 get_baudrate(void) { return -1; } 16 #endif 17 extern u32 fsl_get_sys_freq(void); 18 19 struct spi_board_info; 20 struct device_node; 21 22 extern void fsl_rstcr_restart(char *cmd); 23 24 /* The different ports that the DIU can be connected to */ 25 enum fsl_diu_monitor_port { 26 FSL_DIU_PORT_DVI, /* DVI */ 27 FSL_DIU_PORT_LVDS, /* Single-link LVDS */ 28 FSL_DIU_PORT_DLVDS /* Dual-link LVDS */ 29 }; 30 31 struct platform_diu_data_ops { 32 u32 (*get_pixel_format)(enum fsl_diu_monitor_port port, 33 unsigned int bpp); 34 void (*set_gamma_table)(enum fsl_diu_monitor_port port, 35 char *gamma_table_base); 36 void (*set_monitor_port)(enum fsl_diu_monitor_port port); 37 void (*set_pixel_clock)(unsigned int pixclock); 38 enum fsl_diu_monitor_port (*valid_monitor_port) 39 (enum fsl_diu_monitor_port port); 40 void (*release_bootmem)(void); 41 }; 42 43 extern struct platform_diu_data_ops diu_ops; 44 45 void fsl_hv_restart(char *cmd); 46 void fsl_hv_halt(void); 47 48 #endif 49 #endif 50