1 /* 2 * Freescale MPC85xx/MPC86xx RapidIO support 3 * 4 * Copyright 2009 Sysgo AG 5 * Thomas Moll <thomas.moll@sysgo.com> 6 * - fixed maintenance access routines, check for aligned access 7 * 8 * Copyright 2009 Integrated Device Technology, Inc. 9 * Alex Bounine <alexandre.bounine@idt.com> 10 * - Added Port-Write message handling 11 * - Added Machine Check exception handling 12 * 13 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc. 14 * Zhang Wei <wei.zhang@freescale.com> 15 * 16 * Copyright 2005 MontaVista Software, Inc. 17 * Matt Porter <mporter@kernel.crashing.org> 18 * 19 * This program is free software; you can redistribute it and/or modify it 20 * under the terms of the GNU General Public License as published by the 21 * Free Software Foundation; either version 2 of the License, or (at your 22 * option) any later version. 23 */ 24 25 #include <linux/init.h> 26 #include <linux/extable.h> 27 #include <linux/types.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/interrupt.h> 30 #include <linux/device.h> 31 #include <linux/of_address.h> 32 #include <linux/of_irq.h> 33 #include <linux/of_platform.h> 34 #include <linux/delay.h> 35 #include <linux/slab.h> 36 37 #include <linux/io.h> 38 #include <linux/uaccess.h> 39 #include <asm/machdep.h> 40 41 #include "fsl_rio.h" 42 43 #undef DEBUG_PW /* Port-Write debugging */ 44 45 #define RIO_PORT1_EDCSR 0x0640 46 #define RIO_PORT2_EDCSR 0x0680 47 #define RIO_PORT1_IECSR 0x10130 48 #define RIO_PORT2_IECSR 0x101B0 49 50 #define RIO_GCCSR 0x13c 51 #define RIO_ESCSR 0x158 52 #define ESCSR_CLEAR 0x07120204 53 #define RIO_PORT2_ESCSR 0x178 54 #define RIO_CCSR 0x15c 55 #define RIO_LTLEDCSR_IER 0x80000000 56 #define RIO_LTLEDCSR_PRT 0x01000000 57 #define IECSR_CLEAR 0x80000000 58 #define RIO_ISR_AACR 0x10120 59 #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */ 60 61 #define RIWTAR_TRAD_VAL_SHIFT 12 62 #define RIWTAR_TRAD_MASK 0x00FFFFFF 63 #define RIWBAR_BADD_VAL_SHIFT 12 64 #define RIWBAR_BADD_MASK 0x003FFFFF 65 #define RIWAR_ENABLE 0x80000000 66 #define RIWAR_TGINT_LOCAL 0x00F00000 67 #define RIWAR_RDTYP_NO_SNOOP 0x00040000 68 #define RIWAR_RDTYP_SNOOP 0x00050000 69 #define RIWAR_WRTYP_NO_SNOOP 0x00004000 70 #define RIWAR_WRTYP_SNOOP 0x00005000 71 #define RIWAR_WRTYP_ALLOC 0x00006000 72 #define RIWAR_SIZE_MASK 0x0000003F 73 74 #define __fsl_read_rio_config(x, addr, err, op) \ 75 __asm__ __volatile__( \ 76 "1: "op" %1,0(%2)\n" \ 77 " eieio\n" \ 78 "2:\n" \ 79 ".section .fixup,\"ax\"\n" \ 80 "3: li %1,-1\n" \ 81 " li %0,%3\n" \ 82 " b 2b\n" \ 83 ".previous\n" \ 84 EX_TABLE(1b, 3b) \ 85 : "=r" (err), "=r" (x) \ 86 : "b" (addr), "i" (-EFAULT), "0" (err)) 87 88 void __iomem *rio_regs_win; 89 void __iomem *rmu_regs_win; 90 resource_size_t rio_law_start; 91 92 struct fsl_rio_dbell *dbell; 93 struct fsl_rio_pw *pw; 94 95 #ifdef CONFIG_E500 96 int fsl_rio_mcheck_exception(struct pt_regs *regs) 97 { 98 const struct exception_table_entry *entry; 99 unsigned long reason; 100 101 if (!rio_regs_win) 102 return 0; 103 104 reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR)); 105 if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) { 106 /* Check if we are prepared to handle this fault */ 107 entry = search_exception_tables(regs->nip); 108 if (entry) { 109 pr_debug("RIO: %s - MC Exception handled\n", 110 __func__); 111 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 112 0); 113 regs->msr |= MSR_RI; 114 regs->nip = extable_fixup(entry); 115 return 1; 116 } 117 } 118 119 return 0; 120 } 121 EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception); 122 #endif 123 124 /** 125 * fsl_local_config_read - Generate a MPC85xx local config space read 126 * @mport: RapidIO master port info 127 * @index: ID of RapdiIO interface 128 * @offset: Offset into configuration space 129 * @len: Length (in bytes) of the maintenance transaction 130 * @data: Value to be read into 131 * 132 * Generates a MPC85xx local configuration space read. Returns %0 on 133 * success or %-EINVAL on failure. 134 */ 135 static int fsl_local_config_read(struct rio_mport *mport, 136 int index, u32 offset, int len, u32 *data) 137 { 138 struct rio_priv *priv = mport->priv; 139 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index, 140 offset); 141 *data = in_be32(priv->regs_win + offset); 142 143 return 0; 144 } 145 146 /** 147 * fsl_local_config_write - Generate a MPC85xx local config space write 148 * @mport: RapidIO master port info 149 * @index: ID of RapdiIO interface 150 * @offset: Offset into configuration space 151 * @len: Length (in bytes) of the maintenance transaction 152 * @data: Value to be written 153 * 154 * Generates a MPC85xx local configuration space write. Returns %0 on 155 * success or %-EINVAL on failure. 156 */ 157 static int fsl_local_config_write(struct rio_mport *mport, 158 int index, u32 offset, int len, u32 data) 159 { 160 struct rio_priv *priv = mport->priv; 161 pr_debug 162 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n", 163 index, offset, data); 164 out_be32(priv->regs_win + offset, data); 165 166 return 0; 167 } 168 169 /** 170 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction 171 * @mport: RapidIO master port info 172 * @index: ID of RapdiIO interface 173 * @destid: Destination ID of transaction 174 * @hopcount: Number of hops to target device 175 * @offset: Offset into configuration space 176 * @len: Length (in bytes) of the maintenance transaction 177 * @val: Location to be read into 178 * 179 * Generates a MPC85xx read maintenance transaction. Returns %0 on 180 * success or %-EINVAL on failure. 181 */ 182 static int 183 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid, 184 u8 hopcount, u32 offset, int len, u32 *val) 185 { 186 struct rio_priv *priv = mport->priv; 187 u8 *data; 188 u32 rval, err = 0; 189 190 pr_debug 191 ("fsl_rio_config_read:" 192 " index %d destid %d hopcount %d offset %8.8x len %d\n", 193 index, destid, hopcount, offset, len); 194 195 /* 16MB maintenance window possible */ 196 /* allow only aligned access to maintenance registers */ 197 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len)) 198 return -EINVAL; 199 200 out_be32(&priv->maint_atmu_regs->rowtar, 201 (destid << 22) | (hopcount << 12) | (offset >> 12)); 202 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); 203 204 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); 205 switch (len) { 206 case 1: 207 __fsl_read_rio_config(rval, data, err, "lbz"); 208 break; 209 case 2: 210 __fsl_read_rio_config(rval, data, err, "lhz"); 211 break; 212 case 4: 213 __fsl_read_rio_config(rval, data, err, "lwz"); 214 break; 215 default: 216 return -EINVAL; 217 } 218 219 if (err) { 220 pr_debug("RIO: cfg_read error %d for %x:%x:%x\n", 221 err, destid, hopcount, offset); 222 } 223 224 *val = rval; 225 226 return err; 227 } 228 229 /** 230 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction 231 * @mport: RapidIO master port info 232 * @index: ID of RapdiIO interface 233 * @destid: Destination ID of transaction 234 * @hopcount: Number of hops to target device 235 * @offset: Offset into configuration space 236 * @len: Length (in bytes) of the maintenance transaction 237 * @val: Value to be written 238 * 239 * Generates an MPC85xx write maintenance transaction. Returns %0 on 240 * success or %-EINVAL on failure. 241 */ 242 static int 243 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid, 244 u8 hopcount, u32 offset, int len, u32 val) 245 { 246 struct rio_priv *priv = mport->priv; 247 u8 *data; 248 pr_debug 249 ("fsl_rio_config_write:" 250 " index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n", 251 index, destid, hopcount, offset, len, val); 252 253 /* 16MB maintenance windows possible */ 254 /* allow only aligned access to maintenance registers */ 255 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len)) 256 return -EINVAL; 257 258 out_be32(&priv->maint_atmu_regs->rowtar, 259 (destid << 22) | (hopcount << 12) | (offset >> 12)); 260 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); 261 262 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); 263 switch (len) { 264 case 1: 265 out_8((u8 *) data, val); 266 break; 267 case 2: 268 out_be16((u16 *) data, val); 269 break; 270 case 4: 271 out_be32((u32 *) data, val); 272 break; 273 default: 274 return -EINVAL; 275 } 276 277 return 0; 278 } 279 280 static void fsl_rio_inbound_mem_init(struct rio_priv *priv) 281 { 282 int i; 283 284 /* close inbound windows */ 285 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) 286 out_be32(&priv->inb_atmu_regs[i].riwar, 0); 287 } 288 289 int fsl_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart, 290 u64 rstart, u64 size, u32 flags) 291 { 292 struct rio_priv *priv = mport->priv; 293 u32 base_size; 294 unsigned int base_size_log; 295 u64 win_start, win_end; 296 u32 riwar; 297 int i; 298 299 if ((size & (size - 1)) != 0 || size > 0x400000000ULL) 300 return -EINVAL; 301 302 base_size_log = ilog2(size); 303 base_size = 1 << base_size_log; 304 305 /* check if addresses are aligned with the window size */ 306 if (lstart & (base_size - 1)) 307 return -EINVAL; 308 if (rstart & (base_size - 1)) 309 return -EINVAL; 310 311 /* check for conflicting ranges */ 312 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) { 313 riwar = in_be32(&priv->inb_atmu_regs[i].riwar); 314 if ((riwar & RIWAR_ENABLE) == 0) 315 continue; 316 win_start = ((u64)(in_be32(&priv->inb_atmu_regs[i].riwbar) & RIWBAR_BADD_MASK)) 317 << RIWBAR_BADD_VAL_SHIFT; 318 win_end = win_start + ((1 << ((riwar & RIWAR_SIZE_MASK) + 1)) - 1); 319 if (rstart < win_end && (rstart + size) > win_start) 320 return -EINVAL; 321 } 322 323 /* find unused atmu */ 324 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) { 325 riwar = in_be32(&priv->inb_atmu_regs[i].riwar); 326 if ((riwar & RIWAR_ENABLE) == 0) 327 break; 328 } 329 if (i >= RIO_INB_ATMU_COUNT) 330 return -ENOMEM; 331 332 out_be32(&priv->inb_atmu_regs[i].riwtar, lstart >> RIWTAR_TRAD_VAL_SHIFT); 333 out_be32(&priv->inb_atmu_regs[i].riwbar, rstart >> RIWBAR_BADD_VAL_SHIFT); 334 out_be32(&priv->inb_atmu_regs[i].riwar, RIWAR_ENABLE | RIWAR_TGINT_LOCAL | 335 RIWAR_RDTYP_SNOOP | RIWAR_WRTYP_SNOOP | (base_size_log - 1)); 336 337 return 0; 338 } 339 340 void fsl_unmap_inb_mem(struct rio_mport *mport, dma_addr_t lstart) 341 { 342 u32 win_start_shift, base_start_shift; 343 struct rio_priv *priv = mport->priv; 344 u32 riwar, riwtar; 345 int i; 346 347 /* skip default window */ 348 base_start_shift = lstart >> RIWTAR_TRAD_VAL_SHIFT; 349 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) { 350 riwar = in_be32(&priv->inb_atmu_regs[i].riwar); 351 if ((riwar & RIWAR_ENABLE) == 0) 352 continue; 353 354 riwtar = in_be32(&priv->inb_atmu_regs[i].riwtar); 355 win_start_shift = riwtar & RIWTAR_TRAD_MASK; 356 if (win_start_shift == base_start_shift) { 357 out_be32(&priv->inb_atmu_regs[i].riwar, riwar & ~RIWAR_ENABLE); 358 return; 359 } 360 } 361 } 362 363 void fsl_rio_port_error_handler(int offset) 364 { 365 /*XXX: Error recovery is not implemented, we just clear errors */ 366 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0); 367 368 if (offset == 0) { 369 out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0); 370 out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR); 371 out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR); 372 } else { 373 out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0); 374 out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR); 375 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR); 376 } 377 } 378 static inline void fsl_rio_info(struct device *dev, u32 ccsr) 379 { 380 const char *str; 381 if (ccsr & 1) { 382 /* Serial phy */ 383 switch (ccsr >> 30) { 384 case 0: 385 str = "1"; 386 break; 387 case 1: 388 str = "4"; 389 break; 390 default: 391 str = "Unknown"; 392 break; 393 } 394 dev_info(dev, "Hardware port width: %s\n", str); 395 396 switch ((ccsr >> 27) & 7) { 397 case 0: 398 str = "Single-lane 0"; 399 break; 400 case 1: 401 str = "Single-lane 2"; 402 break; 403 case 2: 404 str = "Four-lane"; 405 break; 406 default: 407 str = "Unknown"; 408 break; 409 } 410 dev_info(dev, "Training connection status: %s\n", str); 411 } else { 412 /* Parallel phy */ 413 if (!(ccsr & 0x80000000)) 414 dev_info(dev, "Output port operating in 8-bit mode\n"); 415 if (!(ccsr & 0x08000000)) 416 dev_info(dev, "Input port operating in 8-bit mode\n"); 417 } 418 } 419 420 /** 421 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface 422 * @dev: platform_device pointer 423 * 424 * Initializes MPC85xx RapidIO hardware interface, configures 425 * master port with system-specific info, and registers the 426 * master port with the RapidIO subsystem. 427 */ 428 int fsl_rio_setup(struct platform_device *dev) 429 { 430 struct rio_ops *ops; 431 struct rio_mport *port; 432 struct rio_priv *priv; 433 int rc = 0; 434 const u32 *dt_range, *cell, *port_index; 435 u32 active_ports = 0; 436 struct resource regs, rmu_regs; 437 struct device_node *np, *rmu_node; 438 int rlen; 439 u32 ccsr; 440 u64 range_start, range_size; 441 int paw, aw, sw; 442 u32 i; 443 static int tmp; 444 struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL}; 445 446 if (!dev->dev.of_node) { 447 dev_err(&dev->dev, "Device OF-Node is NULL"); 448 return -ENODEV; 449 } 450 451 rc = of_address_to_resource(dev->dev.of_node, 0, ®s); 452 if (rc) { 453 dev_err(&dev->dev, "Can't get %s property 'reg'\n", 454 dev->dev.of_node->full_name); 455 return -EFAULT; 456 } 457 dev_info(&dev->dev, "Of-device full name %s\n", 458 dev->dev.of_node->full_name); 459 dev_info(&dev->dev, "Regs: %pR\n", ®s); 460 461 rio_regs_win = ioremap(regs.start, resource_size(®s)); 462 if (!rio_regs_win) { 463 dev_err(&dev->dev, "Unable to map rio register window\n"); 464 rc = -ENOMEM; 465 goto err_rio_regs; 466 } 467 468 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL); 469 if (!ops) { 470 rc = -ENOMEM; 471 goto err_ops; 472 } 473 ops->lcread = fsl_local_config_read; 474 ops->lcwrite = fsl_local_config_write; 475 ops->cread = fsl_rio_config_read; 476 ops->cwrite = fsl_rio_config_write; 477 ops->dsend = fsl_rio_doorbell_send; 478 ops->pwenable = fsl_rio_pw_enable; 479 ops->open_outb_mbox = fsl_open_outb_mbox; 480 ops->open_inb_mbox = fsl_open_inb_mbox; 481 ops->close_outb_mbox = fsl_close_outb_mbox; 482 ops->close_inb_mbox = fsl_close_inb_mbox; 483 ops->add_outb_message = fsl_add_outb_message; 484 ops->add_inb_buffer = fsl_add_inb_buffer; 485 ops->get_inb_message = fsl_get_inb_message; 486 ops->map_inb = fsl_map_inb_mem; 487 ops->unmap_inb = fsl_unmap_inb_mem; 488 489 rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0); 490 if (!rmu_node) { 491 dev_err(&dev->dev, "No valid fsl,srio-rmu-handle property\n"); 492 rc = -ENOENT; 493 goto err_rmu; 494 } 495 rc = of_address_to_resource(rmu_node, 0, &rmu_regs); 496 if (rc) { 497 dev_err(&dev->dev, "Can't get %s property 'reg'\n", 498 rmu_node->full_name); 499 goto err_rmu; 500 } 501 rmu_regs_win = ioremap(rmu_regs.start, resource_size(&rmu_regs)); 502 if (!rmu_regs_win) { 503 dev_err(&dev->dev, "Unable to map rmu register window\n"); 504 rc = -ENOMEM; 505 goto err_rmu; 506 } 507 for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") { 508 rmu_np[tmp] = np; 509 tmp++; 510 } 511 512 /*set up doobell node*/ 513 np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit"); 514 if (!np) { 515 dev_err(&dev->dev, "No fsl,srio-dbell-unit node\n"); 516 rc = -ENODEV; 517 goto err_dbell; 518 } 519 dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL); 520 if (!(dbell)) { 521 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n"); 522 rc = -ENOMEM; 523 goto err_dbell; 524 } 525 dbell->dev = &dev->dev; 526 dbell->bellirq = irq_of_parse_and_map(np, 1); 527 dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq); 528 529 aw = of_n_addr_cells(np); 530 dt_range = of_get_property(np, "reg", &rlen); 531 if (!dt_range) { 532 pr_err("%s: unable to find 'reg' property\n", 533 np->full_name); 534 rc = -ENOMEM; 535 goto err_pw; 536 } 537 range_start = of_read_number(dt_range, aw); 538 dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win + 539 (u32)range_start); 540 541 /*set up port write node*/ 542 np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit"); 543 if (!np) { 544 dev_err(&dev->dev, "No fsl,srio-port-write-unit node\n"); 545 rc = -ENODEV; 546 goto err_pw; 547 } 548 pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL); 549 if (!(pw)) { 550 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n"); 551 rc = -ENOMEM; 552 goto err_pw; 553 } 554 pw->dev = &dev->dev; 555 pw->pwirq = irq_of_parse_and_map(np, 0); 556 dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq); 557 aw = of_n_addr_cells(np); 558 dt_range = of_get_property(np, "reg", &rlen); 559 if (!dt_range) { 560 pr_err("%s: unable to find 'reg' property\n", 561 np->full_name); 562 rc = -ENOMEM; 563 goto err; 564 } 565 range_start = of_read_number(dt_range, aw); 566 pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start); 567 568 /*set up ports node*/ 569 for_each_child_of_node(dev->dev.of_node, np) { 570 port_index = of_get_property(np, "cell-index", NULL); 571 if (!port_index) { 572 dev_err(&dev->dev, "Can't get %s property 'cell-index'\n", 573 np->full_name); 574 continue; 575 } 576 577 dt_range = of_get_property(np, "ranges", &rlen); 578 if (!dt_range) { 579 dev_err(&dev->dev, "Can't get %s property 'ranges'\n", 580 np->full_name); 581 continue; 582 } 583 584 /* Get node address wide */ 585 cell = of_get_property(np, "#address-cells", NULL); 586 if (cell) 587 aw = *cell; 588 else 589 aw = of_n_addr_cells(np); 590 /* Get node size wide */ 591 cell = of_get_property(np, "#size-cells", NULL); 592 if (cell) 593 sw = *cell; 594 else 595 sw = of_n_size_cells(np); 596 /* Get parent address wide wide */ 597 paw = of_n_addr_cells(np); 598 range_start = of_read_number(dt_range + aw, paw); 599 range_size = of_read_number(dt_range + aw + paw, sw); 600 601 dev_info(&dev->dev, "%s: LAW start 0x%016llx, size 0x%016llx.\n", 602 np->full_name, range_start, range_size); 603 604 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL); 605 if (!port) 606 continue; 607 608 rc = rio_mport_initialize(port); 609 if (rc) { 610 kfree(port); 611 continue; 612 } 613 614 i = *port_index - 1; 615 port->index = (unsigned char)i; 616 617 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL); 618 if (!priv) { 619 dev_err(&dev->dev, "Can't alloc memory for 'priv'\n"); 620 kfree(port); 621 continue; 622 } 623 624 INIT_LIST_HEAD(&port->dbells); 625 port->iores.start = range_start; 626 port->iores.end = port->iores.start + range_size - 1; 627 port->iores.flags = IORESOURCE_MEM; 628 port->iores.name = "rio_io_win"; 629 630 if (request_resource(&iomem_resource, &port->iores) < 0) { 631 dev_err(&dev->dev, "RIO: Error requesting master port region" 632 " 0x%016llx-0x%016llx\n", 633 (u64)port->iores.start, (u64)port->iores.end); 634 kfree(priv); 635 kfree(port); 636 continue; 637 } 638 sprintf(port->name, "RIO mport %d", i); 639 640 priv->dev = &dev->dev; 641 port->dev.parent = &dev->dev; 642 port->ops = ops; 643 port->priv = priv; 644 port->phys_efptr = 0x100; 645 port->phys_rmap = 1; 646 priv->regs_win = rio_regs_win; 647 648 ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20); 649 650 /* Checking the port training status */ 651 if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) { 652 dev_err(&dev->dev, "Port %d is not ready. " 653 "Try to restart connection...\n", i); 654 /* Disable ports */ 655 out_be32(priv->regs_win 656 + RIO_CCSR + i*0x20, 0); 657 /* Set 1x lane */ 658 setbits32(priv->regs_win 659 + RIO_CCSR + i*0x20, 0x02000000); 660 /* Enable ports */ 661 setbits32(priv->regs_win 662 + RIO_CCSR + i*0x20, 0x00600000); 663 msleep(100); 664 if (in_be32((priv->regs_win 665 + RIO_ESCSR + i*0x20)) & 1) { 666 dev_err(&dev->dev, 667 "Port %d restart failed.\n", i); 668 release_resource(&port->iores); 669 kfree(priv); 670 kfree(port); 671 continue; 672 } 673 dev_info(&dev->dev, "Port %d restart success!\n", i); 674 } 675 fsl_rio_info(&dev->dev, ccsr); 676 677 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR)) 678 & RIO_PEF_CTLS) >> 4; 679 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n", 680 port->sys_size ? 65536 : 256); 681 682 if (port->host_deviceid >= 0) 683 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST | 684 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED); 685 else 686 out_be32(priv->regs_win + RIO_GCCSR, 687 RIO_PORT_GEN_MASTER); 688 689 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win 690 + ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET : 691 RIO_ATMU_REGS_PORT2_OFFSET)); 692 693 priv->maint_atmu_regs = priv->atmu_regs + 1; 694 priv->inb_atmu_regs = (struct rio_inb_atmu_regs __iomem *) 695 (priv->regs_win + 696 ((i == 0) ? RIO_INB_ATMU_REGS_PORT1_OFFSET : 697 RIO_INB_ATMU_REGS_PORT2_OFFSET)); 698 699 /* Set to receive packets with any dest ID */ 700 out_be32((priv->regs_win + RIO_ISR_AACR + i*0x80), 701 RIO_ISR_AACR_AA); 702 703 /* Configure maintenance transaction window */ 704 out_be32(&priv->maint_atmu_regs->rowbar, 705 port->iores.start >> 12); 706 out_be32(&priv->maint_atmu_regs->rowar, 707 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1)); 708 709 priv->maint_win = ioremap(port->iores.start, 710 RIO_MAINT_WIN_SIZE); 711 712 rio_law_start = range_start; 713 714 fsl_rio_setup_rmu(port, rmu_np[i]); 715 fsl_rio_inbound_mem_init(priv); 716 717 dbell->mport[i] = port; 718 pw->mport[i] = port; 719 720 if (rio_register_mport(port)) { 721 release_resource(&port->iores); 722 kfree(priv); 723 kfree(port); 724 continue; 725 } 726 active_ports++; 727 } 728 729 if (!active_ports) { 730 rc = -ENOLINK; 731 goto err; 732 } 733 734 fsl_rio_doorbell_init(dbell); 735 fsl_rio_port_write_init(pw); 736 737 return 0; 738 err: 739 kfree(pw); 740 pw = NULL; 741 err_pw: 742 kfree(dbell); 743 dbell = NULL; 744 err_dbell: 745 iounmap(rmu_regs_win); 746 rmu_regs_win = NULL; 747 err_rmu: 748 kfree(ops); 749 err_ops: 750 iounmap(rio_regs_win); 751 rio_regs_win = NULL; 752 err_rio_regs: 753 return rc; 754 } 755 756 /* The probe function for RapidIO peer-to-peer network. 757 */ 758 static int fsl_of_rio_rpn_probe(struct platform_device *dev) 759 { 760 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n", 761 dev->dev.of_node->full_name); 762 763 return fsl_rio_setup(dev); 764 }; 765 766 static const struct of_device_id fsl_of_rio_rpn_ids[] = { 767 { 768 .compatible = "fsl,srio", 769 }, 770 {}, 771 }; 772 773 static struct platform_driver fsl_of_rio_rpn_driver = { 774 .driver = { 775 .name = "fsl-of-rio", 776 .of_match_table = fsl_of_rio_rpn_ids, 777 }, 778 .probe = fsl_of_rio_rpn_probe, 779 }; 780 781 static __init int fsl_of_rio_rpn_init(void) 782 { 783 return platform_driver_register(&fsl_of_rio_rpn_driver); 784 } 785 786 subsys_initcall(fsl_of_rio_rpn_init); 787