xref: /openbmc/linux/arch/powerpc/sysdev/fsl_rio.c (revision 4800cd83)
1 /*
2  * Freescale MPC85xx/MPC86xx RapidIO support
3  *
4  * Copyright 2009 Sysgo AG
5  * Thomas Moll <thomas.moll@sysgo.com>
6  * - fixed maintenance access routines, check for aligned access
7  *
8  * Copyright 2009 Integrated Device Technology, Inc.
9  * Alex Bounine <alexandre.bounine@idt.com>
10  * - Added Port-Write message handling
11  * - Added Machine Check exception handling
12  *
13  * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc.
14  * Zhang Wei <wei.zhang@freescale.com>
15  *
16  * Copyright 2005 MontaVista Software, Inc.
17  * Matt Porter <mporter@kernel.crashing.org>
18  *
19  * This program is free software; you can redistribute  it and/or modify it
20  * under  the terms of  the GNU General  Public License as published by the
21  * Free Software Foundation;  either version 2 of the  License, or (at your
22  * option) any later version.
23  */
24 
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/interrupt.h>
30 #include <linux/device.h>
31 #include <linux/rio.h>
32 #include <linux/rio_drv.h>
33 #include <linux/of_platform.h>
34 #include <linux/delay.h>
35 #include <linux/slab.h>
36 #include <linux/kfifo.h>
37 
38 #include <asm/io.h>
39 #include <asm/machdep.h>
40 #include <asm/uaccess.h>
41 
42 #undef DEBUG_PW	/* Port-Write debugging */
43 
44 /* RapidIO definition irq, which read from OF-tree */
45 #define IRQ_RIO_BELL(m)		(((struct rio_priv *)(m->priv))->bellirq)
46 #define IRQ_RIO_TX(m)		(((struct rio_priv *)(m->priv))->txirq)
47 #define IRQ_RIO_RX(m)		(((struct rio_priv *)(m->priv))->rxirq)
48 #define IRQ_RIO_PW(m)		(((struct rio_priv *)(m->priv))->pwirq)
49 
50 #define RIO_ATMU_REGS_OFFSET	0x10c00
51 #define RIO_P_MSG_REGS_OFFSET	0x11000
52 #define RIO_S_MSG_REGS_OFFSET	0x13000
53 #define RIO_GCCSR		0x13c
54 #define RIO_ESCSR		0x158
55 #define RIO_CCSR		0x15c
56 #define RIO_LTLEDCSR		0x0608
57 #define  RIO_LTLEDCSR_IER	0x80000000
58 #define  RIO_LTLEDCSR_PRT	0x01000000
59 #define RIO_LTLEECSR		0x060c
60 #define RIO_EPWISR		0x10010
61 #define RIO_ISR_AACR		0x10120
62 #define RIO_ISR_AACR_AA		0x1	/* Accept All ID */
63 #define RIO_MAINT_WIN_SIZE	0x400000
64 #define RIO_DBELL_WIN_SIZE	0x1000
65 
66 #define RIO_MSG_OMR_MUI		0x00000002
67 #define RIO_MSG_OSR_TE		0x00000080
68 #define RIO_MSG_OSR_QOI		0x00000020
69 #define RIO_MSG_OSR_QFI		0x00000010
70 #define RIO_MSG_OSR_MUB		0x00000004
71 #define RIO_MSG_OSR_EOMI	0x00000002
72 #define RIO_MSG_OSR_QEI		0x00000001
73 
74 #define RIO_MSG_IMR_MI		0x00000002
75 #define RIO_MSG_ISR_TE		0x00000080
76 #define RIO_MSG_ISR_QFI		0x00000010
77 #define RIO_MSG_ISR_DIQI	0x00000001
78 
79 #define RIO_IPWMR_SEN		0x00100000
80 #define RIO_IPWMR_QFIE		0x00000100
81 #define RIO_IPWMR_EIE		0x00000020
82 #define RIO_IPWMR_CQ		0x00000002
83 #define RIO_IPWMR_PWE		0x00000001
84 
85 #define RIO_IPWSR_QF		0x00100000
86 #define RIO_IPWSR_TE		0x00000080
87 #define RIO_IPWSR_QFI		0x00000010
88 #define RIO_IPWSR_PWD		0x00000008
89 #define RIO_IPWSR_PWB		0x00000004
90 
91 #define RIO_EPWISR_PINT		0x80000000
92 #define RIO_EPWISR_PW		0x00000001
93 
94 #define RIO_MSG_DESC_SIZE	32
95 #define RIO_MSG_BUFFER_SIZE	4096
96 #define RIO_MIN_TX_RING_SIZE	2
97 #define RIO_MAX_TX_RING_SIZE	2048
98 #define RIO_MIN_RX_RING_SIZE	2
99 #define RIO_MAX_RX_RING_SIZE	2048
100 
101 #define DOORBELL_DMR_DI		0x00000002
102 #define DOORBELL_DSR_TE		0x00000080
103 #define DOORBELL_DSR_QFI	0x00000010
104 #define DOORBELL_DSR_DIQI	0x00000001
105 #define DOORBELL_TID_OFFSET	0x02
106 #define DOORBELL_SID_OFFSET	0x04
107 #define DOORBELL_INFO_OFFSET	0x06
108 
109 #define DOORBELL_MESSAGE_SIZE	0x08
110 #define DBELL_SID(x)		(*(u16 *)(x + DOORBELL_SID_OFFSET))
111 #define DBELL_TID(x)		(*(u16 *)(x + DOORBELL_TID_OFFSET))
112 #define DBELL_INF(x)		(*(u16 *)(x + DOORBELL_INFO_OFFSET))
113 
114 struct rio_atmu_regs {
115 	u32 rowtar;
116 	u32 rowtear;
117 	u32 rowbar;
118 	u32 pad2;
119 	u32 rowar;
120 	u32 pad3[3];
121 };
122 
123 struct rio_msg_regs {
124 	u32 omr;	/* 0xD_3000 - Outbound message 0 mode register */
125 	u32 osr;	/* 0xD_3004 - Outbound message 0 status register */
126 	u32 pad1;
127 	u32 odqdpar;	/* 0xD_300C - Outbound message 0 descriptor queue
128 			   dequeue pointer address register */
129 	u32 pad2;
130 	u32 osar;	/* 0xD_3014 - Outbound message 0 source address
131 			   register */
132 	u32 odpr;	/* 0xD_3018 - Outbound message 0 destination port
133 			   register */
134 	u32 odatr;	/* 0xD_301C - Outbound message 0 destination attributes
135 			   Register*/
136 	u32 odcr;	/* 0xD_3020 - Outbound message 0 double-word count
137 			   register */
138 	u32 pad3;
139 	u32 odqepar;	/* 0xD_3028 - Outbound message 0 descriptor queue
140 			   enqueue pointer address register */
141 	u32 pad4[13];
142 	u32 imr;	/* 0xD_3060 - Inbound message 0 mode register */
143 	u32 isr;	/* 0xD_3064 - Inbound message 0 status register */
144 	u32 pad5;
145 	u32 ifqdpar;	/* 0xD_306C - Inbound message 0 frame queue dequeue
146 			   pointer address register*/
147 	u32 pad6;
148 	u32 ifqepar;	/* 0xD_3074 - Inbound message 0 frame queue enqueue
149 			   pointer address register */
150 	u32 pad7[226];
151 	u32 odmr;	/* 0xD_3400 - Outbound doorbell mode register */
152 	u32 odsr;	/* 0xD_3404 - Outbound doorbell status register */
153 	u32 res0[4];
154 	u32 oddpr;	/* 0xD_3418 - Outbound doorbell destination port
155 			   register */
156 	u32 oddatr;	/* 0xD_341c - Outbound doorbell destination attributes
157 			   register */
158 	u32 res1[3];
159 	u32 odretcr;	/* 0xD_342C - Outbound doorbell retry error threshold
160 			   configuration register */
161 	u32 res2[12];
162 	u32 dmr;	/* 0xD_3460 - Inbound doorbell mode register */
163 	u32 dsr;	/* 0xD_3464 - Inbound doorbell status register */
164 	u32 pad8;
165 	u32 dqdpar;	/* 0xD_346C - Inbound doorbell queue dequeue Pointer
166 			   address register */
167 	u32 pad9;
168 	u32 dqepar;	/* 0xD_3474 - Inbound doorbell Queue enqueue pointer
169 			   address register */
170 	u32 pad10[26];
171 	u32 pwmr;	/* 0xD_34E0 - Inbound port-write mode register */
172 	u32 pwsr;	/* 0xD_34E4 - Inbound port-write status register */
173 	u32 epwqbar;	/* 0xD_34E8 - Extended Port-Write Queue Base Address
174 			   register */
175 	u32 pwqbar;	/* 0xD_34EC - Inbound port-write queue base address
176 			   register */
177 };
178 
179 struct rio_tx_desc {
180 	u32 res1;
181 	u32 saddr;
182 	u32 dport;
183 	u32 dattr;
184 	u32 res2;
185 	u32 res3;
186 	u32 dwcnt;
187 	u32 res4;
188 };
189 
190 struct rio_dbell_ring {
191 	void *virt;
192 	dma_addr_t phys;
193 };
194 
195 struct rio_msg_tx_ring {
196 	void *virt;
197 	dma_addr_t phys;
198 	void *virt_buffer[RIO_MAX_TX_RING_SIZE];
199 	dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
200 	int tx_slot;
201 	int size;
202 	void *dev_id;
203 };
204 
205 struct rio_msg_rx_ring {
206 	void *virt;
207 	dma_addr_t phys;
208 	void *virt_buffer[RIO_MAX_RX_RING_SIZE];
209 	int rx_slot;
210 	int size;
211 	void *dev_id;
212 };
213 
214 struct rio_port_write_msg {
215 	void *virt;
216 	dma_addr_t phys;
217 	u32 msg_count;
218 	u32 err_count;
219 	u32 discard_count;
220 };
221 
222 struct rio_priv {
223 	struct device *dev;
224 	void __iomem *regs_win;
225 	struct rio_atmu_regs __iomem *atmu_regs;
226 	struct rio_atmu_regs __iomem *maint_atmu_regs;
227 	struct rio_atmu_regs __iomem *dbell_atmu_regs;
228 	void __iomem *dbell_win;
229 	void __iomem *maint_win;
230 	struct rio_msg_regs __iomem *msg_regs;
231 	struct rio_dbell_ring dbell_ring;
232 	struct rio_msg_tx_ring msg_tx_ring;
233 	struct rio_msg_rx_ring msg_rx_ring;
234 	struct rio_port_write_msg port_write_msg;
235 	int bellirq;
236 	int txirq;
237 	int rxirq;
238 	int pwirq;
239 	struct work_struct pw_work;
240 	struct kfifo pw_fifo;
241 	spinlock_t pw_fifo_lock;
242 };
243 
244 #define __fsl_read_rio_config(x, addr, err, op)		\
245 	__asm__ __volatile__(				\
246 		"1:	"op" %1,0(%2)\n"		\
247 		"	eieio\n"			\
248 		"2:\n"					\
249 		".section .fixup,\"ax\"\n"		\
250 		"3:	li %1,-1\n"			\
251 		"	li %0,%3\n"			\
252 		"	b 2b\n"				\
253 		".section __ex_table,\"a\"\n"		\
254 		"	.align 2\n"			\
255 		"	.long 1b,3b\n"			\
256 		".text"					\
257 		: "=r" (err), "=r" (x)			\
258 		: "b" (addr), "i" (-EFAULT), "0" (err))
259 
260 static void __iomem *rio_regs_win;
261 
262 #ifdef CONFIG_E500
263 static int (*saved_mcheck_exception)(struct pt_regs *regs);
264 
265 static int fsl_rio_mcheck_exception(struct pt_regs *regs)
266 {
267 	const struct exception_table_entry *entry = NULL;
268 	unsigned long reason = mfspr(SPRN_MCSR);
269 
270 	if (reason & MCSR_BUS_RBERR) {
271 		reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
272 		if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
273 			/* Check if we are prepared to handle this fault */
274 			entry = search_exception_tables(regs->nip);
275 			if (entry) {
276 				pr_debug("RIO: %s - MC Exception handled\n",
277 					 __func__);
278 				out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
279 					 0);
280 				regs->msr |= MSR_RI;
281 				regs->nip = entry->fixup;
282 				return 1;
283 			}
284 		}
285 	}
286 
287 	if (saved_mcheck_exception)
288 		return saved_mcheck_exception(regs);
289 	else
290 		return cur_cpu_spec->machine_check(regs);
291 }
292 #endif
293 
294 /**
295  * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
296  * @mport: RapidIO master port info
297  * @index: ID of RapidIO interface
298  * @destid: Destination ID of target device
299  * @data: 16-bit info field of RapidIO doorbell message
300  *
301  * Sends a MPC85xx doorbell message. Returns %0 on success or
302  * %-EINVAL on failure.
303  */
304 static int fsl_rio_doorbell_send(struct rio_mport *mport,
305 				int index, u16 destid, u16 data)
306 {
307 	struct rio_priv *priv = mport->priv;
308 	pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
309 		 index, destid, data);
310 	switch (mport->phy_type) {
311 	case RIO_PHY_PARALLEL:
312 		out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22);
313 		out_be16(priv->dbell_win, data);
314 		break;
315 	case RIO_PHY_SERIAL:
316 		/* In the serial version silicons, such as MPC8548, MPC8641,
317 		 * below operations is must be.
318 		 */
319 		out_be32(&priv->msg_regs->odmr, 0x00000000);
320 		out_be32(&priv->msg_regs->odretcr, 0x00000004);
321 		out_be32(&priv->msg_regs->oddpr, destid << 16);
322 		out_be32(&priv->msg_regs->oddatr, data);
323 		out_be32(&priv->msg_regs->odmr, 0x00000001);
324 		break;
325 	}
326 
327 	return 0;
328 }
329 
330 /**
331  * fsl_local_config_read - Generate a MPC85xx local config space read
332  * @mport: RapidIO master port info
333  * @index: ID of RapdiIO interface
334  * @offset: Offset into configuration space
335  * @len: Length (in bytes) of the maintenance transaction
336  * @data: Value to be read into
337  *
338  * Generates a MPC85xx local configuration space read. Returns %0 on
339  * success or %-EINVAL on failure.
340  */
341 static int fsl_local_config_read(struct rio_mport *mport,
342 				int index, u32 offset, int len, u32 *data)
343 {
344 	struct rio_priv *priv = mport->priv;
345 	pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
346 		 offset);
347 	*data = in_be32(priv->regs_win + offset);
348 
349 	return 0;
350 }
351 
352 /**
353  * fsl_local_config_write - Generate a MPC85xx local config space write
354  * @mport: RapidIO master port info
355  * @index: ID of RapdiIO interface
356  * @offset: Offset into configuration space
357  * @len: Length (in bytes) of the maintenance transaction
358  * @data: Value to be written
359  *
360  * Generates a MPC85xx local configuration space write. Returns %0 on
361  * success or %-EINVAL on failure.
362  */
363 static int fsl_local_config_write(struct rio_mport *mport,
364 				int index, u32 offset, int len, u32 data)
365 {
366 	struct rio_priv *priv = mport->priv;
367 	pr_debug
368 	    ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
369 	     index, offset, data);
370 	out_be32(priv->regs_win + offset, data);
371 
372 	return 0;
373 }
374 
375 /**
376  * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
377  * @mport: RapidIO master port info
378  * @index: ID of RapdiIO interface
379  * @destid: Destination ID of transaction
380  * @hopcount: Number of hops to target device
381  * @offset: Offset into configuration space
382  * @len: Length (in bytes) of the maintenance transaction
383  * @val: Location to be read into
384  *
385  * Generates a MPC85xx read maintenance transaction. Returns %0 on
386  * success or %-EINVAL on failure.
387  */
388 static int
389 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
390 			u8 hopcount, u32 offset, int len, u32 *val)
391 {
392 	struct rio_priv *priv = mport->priv;
393 	u8 *data;
394 	u32 rval, err = 0;
395 
396 	pr_debug
397 	    ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
398 	     index, destid, hopcount, offset, len);
399 
400 	/* 16MB maintenance window possible */
401 	/* allow only aligned access to maintenance registers */
402 	if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
403 		return -EINVAL;
404 
405 	out_be32(&priv->maint_atmu_regs->rowtar,
406 		 (destid << 22) | (hopcount << 12) | (offset >> 12));
407 	out_be32(&priv->maint_atmu_regs->rowtear,  (destid >> 10));
408 
409 	data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
410 	switch (len) {
411 	case 1:
412 		__fsl_read_rio_config(rval, data, err, "lbz");
413 		break;
414 	case 2:
415 		__fsl_read_rio_config(rval, data, err, "lhz");
416 		break;
417 	case 4:
418 		__fsl_read_rio_config(rval, data, err, "lwz");
419 		break;
420 	default:
421 		return -EINVAL;
422 	}
423 
424 	if (err) {
425 		pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
426 			 err, destid, hopcount, offset);
427 	}
428 
429 	*val = rval;
430 
431 	return err;
432 }
433 
434 /**
435  * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
436  * @mport: RapidIO master port info
437  * @index: ID of RapdiIO interface
438  * @destid: Destination ID of transaction
439  * @hopcount: Number of hops to target device
440  * @offset: Offset into configuration space
441  * @len: Length (in bytes) of the maintenance transaction
442  * @val: Value to be written
443  *
444  * Generates an MPC85xx write maintenance transaction. Returns %0 on
445  * success or %-EINVAL on failure.
446  */
447 static int
448 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
449 			u8 hopcount, u32 offset, int len, u32 val)
450 {
451 	struct rio_priv *priv = mport->priv;
452 	u8 *data;
453 	pr_debug
454 	    ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
455 	     index, destid, hopcount, offset, len, val);
456 
457 	/* 16MB maintenance windows possible */
458 	/* allow only aligned access to maintenance registers */
459 	if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
460 		return -EINVAL;
461 
462 	out_be32(&priv->maint_atmu_regs->rowtar,
463 		 (destid << 22) | (hopcount << 12) | (offset >> 12));
464 	out_be32(&priv->maint_atmu_regs->rowtear,  (destid >> 10));
465 
466 	data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
467 	switch (len) {
468 	case 1:
469 		out_8((u8 *) data, val);
470 		break;
471 	case 2:
472 		out_be16((u16 *) data, val);
473 		break;
474 	case 4:
475 		out_be32((u32 *) data, val);
476 		break;
477 	default:
478 		return -EINVAL;
479 	}
480 
481 	return 0;
482 }
483 
484 /**
485  * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue
486  * @mport: Master port with outbound message queue
487  * @rdev: Target of outbound message
488  * @mbox: Outbound mailbox
489  * @buffer: Message to add to outbound queue
490  * @len: Length of message
491  *
492  * Adds the @buffer message to the MPC85xx outbound message queue. Returns
493  * %0 on success or %-EINVAL on failure.
494  */
495 int
496 rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
497 			void *buffer, size_t len)
498 {
499 	struct rio_priv *priv = mport->priv;
500 	u32 omr;
501 	struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt
502 					+ priv->msg_tx_ring.tx_slot;
503 	int ret = 0;
504 
505 	pr_debug
506 	    ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n",
507 	     rdev->destid, mbox, (int)buffer, len);
508 
509 	if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
510 		ret = -EINVAL;
511 		goto out;
512 	}
513 
514 	/* Copy and clear rest of buffer */
515 	memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer,
516 			len);
517 	if (len < (RIO_MAX_MSG_SIZE - 4))
518 		memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot]
519 				+ len, 0, RIO_MAX_MSG_SIZE - len);
520 
521 	switch (mport->phy_type) {
522 	case RIO_PHY_PARALLEL:
523 		/* Set mbox field for message */
524 		desc->dport = mbox & 0x3;
525 
526 		/* Enable EOMI interrupt, set priority, and set destid */
527 		desc->dattr = 0x28000000 | (rdev->destid << 2);
528 		break;
529 	case RIO_PHY_SERIAL:
530 		/* Set mbox field for message, and set destid */
531 		desc->dport = (rdev->destid << 16) | (mbox & 0x3);
532 
533 		/* Enable EOMI interrupt and priority */
534 		desc->dattr = 0x28000000;
535 		break;
536 	}
537 
538 	/* Set transfer size aligned to next power of 2 (in double words) */
539 	desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
540 
541 	/* Set snooping and source buffer address */
542 	desc->saddr = 0x00000004
543 		| priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot];
544 
545 	/* Increment enqueue pointer */
546 	omr = in_be32(&priv->msg_regs->omr);
547 	out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
548 
549 	/* Go to next descriptor */
550 	if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size)
551 		priv->msg_tx_ring.tx_slot = 0;
552 
553       out:
554 	return ret;
555 }
556 
557 EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);
558 
559 /**
560  * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
561  * @irq: Linux interrupt number
562  * @dev_instance: Pointer to interrupt-specific data
563  *
564  * Handles outbound message interrupts. Executes a register outbound
565  * mailbox event handler and acks the interrupt occurrence.
566  */
567 static irqreturn_t
568 fsl_rio_tx_handler(int irq, void *dev_instance)
569 {
570 	int osr;
571 	struct rio_mport *port = (struct rio_mport *)dev_instance;
572 	struct rio_priv *priv = port->priv;
573 
574 	osr = in_be32(&priv->msg_regs->osr);
575 
576 	if (osr & RIO_MSG_OSR_TE) {
577 		pr_info("RIO: outbound message transmission error\n");
578 		out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE);
579 		goto out;
580 	}
581 
582 	if (osr & RIO_MSG_OSR_QOI) {
583 		pr_info("RIO: outbound message queue overflow\n");
584 		out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI);
585 		goto out;
586 	}
587 
588 	if (osr & RIO_MSG_OSR_EOMI) {
589 		u32 dqp = in_be32(&priv->msg_regs->odqdpar);
590 		int slot = (dqp - priv->msg_tx_ring.phys) >> 5;
591 		port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1,
592 				slot);
593 
594 		/* Ack the end-of-message interrupt */
595 		out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI);
596 	}
597 
598       out:
599 	return IRQ_HANDLED;
600 }
601 
602 /**
603  * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox
604  * @mport: Master port implementing the outbound message unit
605  * @dev_id: Device specific pointer to pass on event
606  * @mbox: Mailbox to open
607  * @entries: Number of entries in the outbound mailbox ring
608  *
609  * Initializes buffer ring, request the outbound message interrupt,
610  * and enables the outbound message unit. Returns %0 on success and
611  * %-EINVAL or %-ENOMEM on failure.
612  */
613 int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
614 {
615 	int i, j, rc = 0;
616 	struct rio_priv *priv = mport->priv;
617 
618 	if ((entries < RIO_MIN_TX_RING_SIZE) ||
619 	    (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
620 		rc = -EINVAL;
621 		goto out;
622 	}
623 
624 	/* Initialize shadow copy ring */
625 	priv->msg_tx_ring.dev_id = dev_id;
626 	priv->msg_tx_ring.size = entries;
627 
628 	for (i = 0; i < priv->msg_tx_ring.size; i++) {
629 		priv->msg_tx_ring.virt_buffer[i] =
630 			dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
631 				&priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
632 		if (!priv->msg_tx_ring.virt_buffer[i]) {
633 			rc = -ENOMEM;
634 			for (j = 0; j < priv->msg_tx_ring.size; j++)
635 				if (priv->msg_tx_ring.virt_buffer[j])
636 					dma_free_coherent(priv->dev,
637 							RIO_MSG_BUFFER_SIZE,
638 							priv->msg_tx_ring.
639 							virt_buffer[j],
640 							priv->msg_tx_ring.
641 							phys_buffer[j]);
642 			goto out;
643 		}
644 	}
645 
646 	/* Initialize outbound message descriptor ring */
647 	priv->msg_tx_ring.virt = dma_alloc_coherent(priv->dev,
648 				priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
649 				&priv->msg_tx_ring.phys, GFP_KERNEL);
650 	if (!priv->msg_tx_ring.virt) {
651 		rc = -ENOMEM;
652 		goto out_dma;
653 	}
654 	memset(priv->msg_tx_ring.virt, 0,
655 			priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
656 	priv->msg_tx_ring.tx_slot = 0;
657 
658 	/* Point dequeue/enqueue pointers at first entry in ring */
659 	out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys);
660 	out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys);
661 
662 	/* Configure for snooping */
663 	out_be32(&priv->msg_regs->osar, 0x00000004);
664 
665 	/* Clear interrupt status */
666 	out_be32(&priv->msg_regs->osr, 0x000000b3);
667 
668 	/* Hook up outbound message handler */
669 	rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
670 			 "msg_tx", (void *)mport);
671 	if (rc < 0)
672 		goto out_irq;
673 
674 	/*
675 	 * Configure outbound message unit
676 	 *      Snooping
677 	 *      Interrupts (all enabled, except QEIE)
678 	 *      Chaining mode
679 	 *      Disable
680 	 */
681 	out_be32(&priv->msg_regs->omr, 0x00100220);
682 
683 	/* Set number of entries */
684 	out_be32(&priv->msg_regs->omr,
685 		 in_be32(&priv->msg_regs->omr) |
686 		 ((get_bitmask_order(entries) - 2) << 12));
687 
688 	/* Now enable the unit */
689 	out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1);
690 
691       out:
692 	return rc;
693 
694       out_irq:
695 	dma_free_coherent(priv->dev,
696 			  priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
697 			  priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
698 
699       out_dma:
700 	for (i = 0; i < priv->msg_tx_ring.size; i++)
701 		dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
702 				  priv->msg_tx_ring.virt_buffer[i],
703 				  priv->msg_tx_ring.phys_buffer[i]);
704 
705 	return rc;
706 }
707 
708 /**
709  * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox
710  * @mport: Master port implementing the outbound message unit
711  * @mbox: Mailbox to close
712  *
713  * Disables the outbound message unit, free all buffers, and
714  * frees the outbound message interrupt.
715  */
716 void rio_close_outb_mbox(struct rio_mport *mport, int mbox)
717 {
718 	struct rio_priv *priv = mport->priv;
719 	/* Disable inbound message unit */
720 	out_be32(&priv->msg_regs->omr, 0);
721 
722 	/* Free ring */
723 	dma_free_coherent(priv->dev,
724 			  priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
725 			  priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
726 
727 	/* Free interrupt */
728 	free_irq(IRQ_RIO_TX(mport), (void *)mport);
729 }
730 
731 /**
732  * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
733  * @irq: Linux interrupt number
734  * @dev_instance: Pointer to interrupt-specific data
735  *
736  * Handles inbound message interrupts. Executes a registered inbound
737  * mailbox event handler and acks the interrupt occurrence.
738  */
739 static irqreturn_t
740 fsl_rio_rx_handler(int irq, void *dev_instance)
741 {
742 	int isr;
743 	struct rio_mport *port = (struct rio_mport *)dev_instance;
744 	struct rio_priv *priv = port->priv;
745 
746 	isr = in_be32(&priv->msg_regs->isr);
747 
748 	if (isr & RIO_MSG_ISR_TE) {
749 		pr_info("RIO: inbound message reception error\n");
750 		out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE);
751 		goto out;
752 	}
753 
754 	/* XXX Need to check/dispatch until queue empty */
755 	if (isr & RIO_MSG_ISR_DIQI) {
756 		/*
757 		 * We implement *only* mailbox 0, but can receive messages
758 		 * for any mailbox/letter to that mailbox destination. So,
759 		 * make the callback with an unknown/invalid mailbox number
760 		 * argument.
761 		 */
762 		port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1);
763 
764 		/* Ack the queueing interrupt */
765 		out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI);
766 	}
767 
768       out:
769 	return IRQ_HANDLED;
770 }
771 
772 /**
773  * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox
774  * @mport: Master port implementing the inbound message unit
775  * @dev_id: Device specific pointer to pass on event
776  * @mbox: Mailbox to open
777  * @entries: Number of entries in the inbound mailbox ring
778  *
779  * Initializes buffer ring, request the inbound message interrupt,
780  * and enables the inbound message unit. Returns %0 on success
781  * and %-EINVAL or %-ENOMEM on failure.
782  */
783 int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
784 {
785 	int i, rc = 0;
786 	struct rio_priv *priv = mport->priv;
787 
788 	if ((entries < RIO_MIN_RX_RING_SIZE) ||
789 	    (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
790 		rc = -EINVAL;
791 		goto out;
792 	}
793 
794 	/* Initialize client buffer ring */
795 	priv->msg_rx_ring.dev_id = dev_id;
796 	priv->msg_rx_ring.size = entries;
797 	priv->msg_rx_ring.rx_slot = 0;
798 	for (i = 0; i < priv->msg_rx_ring.size; i++)
799 		priv->msg_rx_ring.virt_buffer[i] = NULL;
800 
801 	/* Initialize inbound message ring */
802 	priv->msg_rx_ring.virt = dma_alloc_coherent(priv->dev,
803 				priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
804 				&priv->msg_rx_ring.phys, GFP_KERNEL);
805 	if (!priv->msg_rx_ring.virt) {
806 		rc = -ENOMEM;
807 		goto out;
808 	}
809 
810 	/* Point dequeue/enqueue pointers at first entry in ring */
811 	out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys);
812 	out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys);
813 
814 	/* Clear interrupt status */
815 	out_be32(&priv->msg_regs->isr, 0x00000091);
816 
817 	/* Hook up inbound message handler */
818 	rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
819 			 "msg_rx", (void *)mport);
820 	if (rc < 0) {
821 		dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
822 				  priv->msg_tx_ring.virt_buffer[i],
823 				  priv->msg_tx_ring.phys_buffer[i]);
824 		goto out;
825 	}
826 
827 	/*
828 	 * Configure inbound message unit:
829 	 *      Snooping
830 	 *      4KB max message size
831 	 *      Unmask all interrupt sources
832 	 *      Disable
833 	 */
834 	out_be32(&priv->msg_regs->imr, 0x001b0060);
835 
836 	/* Set number of queue entries */
837 	setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
838 
839 	/* Now enable the unit */
840 	setbits32(&priv->msg_regs->imr, 0x1);
841 
842       out:
843 	return rc;
844 }
845 
846 /**
847  * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox
848  * @mport: Master port implementing the inbound message unit
849  * @mbox: Mailbox to close
850  *
851  * Disables the inbound message unit, free all buffers, and
852  * frees the inbound message interrupt.
853  */
854 void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
855 {
856 	struct rio_priv *priv = mport->priv;
857 	/* Disable inbound message unit */
858 	out_be32(&priv->msg_regs->imr, 0);
859 
860 	/* Free ring */
861 	dma_free_coherent(priv->dev, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
862 			  priv->msg_rx_ring.virt, priv->msg_rx_ring.phys);
863 
864 	/* Free interrupt */
865 	free_irq(IRQ_RIO_RX(mport), (void *)mport);
866 }
867 
868 /**
869  * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
870  * @mport: Master port implementing the inbound message unit
871  * @mbox: Inbound mailbox number
872  * @buf: Buffer to add to inbound queue
873  *
874  * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
875  * %0 on success or %-EINVAL on failure.
876  */
877 int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
878 {
879 	int rc = 0;
880 	struct rio_priv *priv = mport->priv;
881 
882 	pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
883 		 priv->msg_rx_ring.rx_slot);
884 
885 	if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) {
886 		printk(KERN_ERR
887 		       "RIO: error adding inbound buffer %d, buffer exists\n",
888 		       priv->msg_rx_ring.rx_slot);
889 		rc = -EINVAL;
890 		goto out;
891 	}
892 
893 	priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf;
894 	if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size)
895 		priv->msg_rx_ring.rx_slot = 0;
896 
897       out:
898 	return rc;
899 }
900 
901 EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
902 
903 /**
904  * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit
905  * @mport: Master port implementing the inbound message unit
906  * @mbox: Inbound mailbox number
907  *
908  * Gets the next available inbound message from the inbound message queue.
909  * A pointer to the message is returned on success or NULL on failure.
910  */
911 void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
912 {
913 	struct rio_priv *priv = mport->priv;
914 	u32 phys_buf, virt_buf;
915 	void *buf = NULL;
916 	int buf_idx;
917 
918 	phys_buf = in_be32(&priv->msg_regs->ifqdpar);
919 
920 	/* If no more messages, then bail out */
921 	if (phys_buf == in_be32(&priv->msg_regs->ifqepar))
922 		goto out2;
923 
924 	virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf
925 						- priv->msg_rx_ring.phys);
926 	buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
927 	buf = priv->msg_rx_ring.virt_buffer[buf_idx];
928 
929 	if (!buf) {
930 		printk(KERN_ERR
931 		       "RIO: inbound message copy failed, no buffers\n");
932 		goto out1;
933 	}
934 
935 	/* Copy max message size, caller is expected to allocate that big */
936 	memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
937 
938 	/* Clear the available buffer */
939 	priv->msg_rx_ring.virt_buffer[buf_idx] = NULL;
940 
941       out1:
942 	setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI);
943 
944       out2:
945 	return buf;
946 }
947 
948 EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);
949 
950 /**
951  * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
952  * @irq: Linux interrupt number
953  * @dev_instance: Pointer to interrupt-specific data
954  *
955  * Handles doorbell interrupts. Parses a list of registered
956  * doorbell event handlers and executes a matching event handler.
957  */
958 static irqreturn_t
959 fsl_rio_dbell_handler(int irq, void *dev_instance)
960 {
961 	int dsr;
962 	struct rio_mport *port = (struct rio_mport *)dev_instance;
963 	struct rio_priv *priv = port->priv;
964 
965 	dsr = in_be32(&priv->msg_regs->dsr);
966 
967 	if (dsr & DOORBELL_DSR_TE) {
968 		pr_info("RIO: doorbell reception error\n");
969 		out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE);
970 		goto out;
971 	}
972 
973 	if (dsr & DOORBELL_DSR_QFI) {
974 		pr_info("RIO: doorbell queue full\n");
975 		out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI);
976 	}
977 
978 	/* XXX Need to check/dispatch until queue empty */
979 	if (dsr & DOORBELL_DSR_DIQI) {
980 		u32 dmsg =
981 		    (u32) priv->dbell_ring.virt +
982 		    (in_be32(&priv->msg_regs->dqdpar) & 0xfff);
983 		struct rio_dbell *dbell;
984 		int found = 0;
985 
986 		pr_debug
987 		    ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
988 		     DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
989 
990 		list_for_each_entry(dbell, &port->dbells, node) {
991 			if ((dbell->res->start <= DBELL_INF(dmsg)) &&
992 			    (dbell->res->end >= DBELL_INF(dmsg))) {
993 				found = 1;
994 				break;
995 			}
996 		}
997 		if (found) {
998 			dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
999 				    DBELL_INF(dmsg));
1000 		} else {
1001 			pr_debug
1002 			    ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
1003 			     DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
1004 		}
1005 		setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI);
1006 		out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI);
1007 	}
1008 
1009       out:
1010 	return IRQ_HANDLED;
1011 }
1012 
1013 /**
1014  * fsl_rio_doorbell_init - MPC85xx doorbell interface init
1015  * @mport: Master port implementing the inbound doorbell unit
1016  *
1017  * Initializes doorbell unit hardware and inbound DMA buffer
1018  * ring. Called from fsl_rio_setup(). Returns %0 on success
1019  * or %-ENOMEM on failure.
1020  */
1021 static int fsl_rio_doorbell_init(struct rio_mport *mport)
1022 {
1023 	struct rio_priv *priv = mport->priv;
1024 	int rc = 0;
1025 
1026 	/* Map outbound doorbell window immediately after maintenance window */
1027 	priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
1028 			    RIO_DBELL_WIN_SIZE);
1029 	if (!priv->dbell_win) {
1030 		printk(KERN_ERR
1031 		       "RIO: unable to map outbound doorbell window\n");
1032 		rc = -ENOMEM;
1033 		goto out;
1034 	}
1035 
1036 	/* Initialize inbound doorbells */
1037 	priv->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 *
1038 		    DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL);
1039 	if (!priv->dbell_ring.virt) {
1040 		printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
1041 		rc = -ENOMEM;
1042 		iounmap(priv->dbell_win);
1043 		goto out;
1044 	}
1045 
1046 	/* Point dequeue/enqueue pointers at first entry in ring */
1047 	out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys);
1048 	out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys);
1049 
1050 	/* Clear interrupt status */
1051 	out_be32(&priv->msg_regs->dsr, 0x00000091);
1052 
1053 	/* Hook up doorbell handler */
1054 	rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0,
1055 			 "dbell_rx", (void *)mport);
1056 	if (rc < 0) {
1057 		iounmap(priv->dbell_win);
1058 		dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE,
1059 				  priv->dbell_ring.virt, priv->dbell_ring.phys);
1060 		printk(KERN_ERR
1061 		       "MPC85xx RIO: unable to request inbound doorbell irq");
1062 		goto out;
1063 	}
1064 
1065 	/* Configure doorbells for snooping, 512 entries, and enable */
1066 	out_be32(&priv->msg_regs->dmr, 0x00108161);
1067 
1068       out:
1069 	return rc;
1070 }
1071 
1072 /**
1073  * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
1074  * @irq: Linux interrupt number
1075  * @dev_instance: Pointer to interrupt-specific data
1076  *
1077  * Handles port write interrupts. Parses a list of registered
1078  * port write event handlers and executes a matching event handler.
1079  */
1080 static irqreturn_t
1081 fsl_rio_port_write_handler(int irq, void *dev_instance)
1082 {
1083 	u32 ipwmr, ipwsr;
1084 	struct rio_mport *port = (struct rio_mport *)dev_instance;
1085 	struct rio_priv *priv = port->priv;
1086 	u32 epwisr, tmp;
1087 
1088 	epwisr = in_be32(priv->regs_win + RIO_EPWISR);
1089 	if (!(epwisr & RIO_EPWISR_PW))
1090 		goto pw_done;
1091 
1092 	ipwmr = in_be32(&priv->msg_regs->pwmr);
1093 	ipwsr = in_be32(&priv->msg_regs->pwsr);
1094 
1095 #ifdef DEBUG_PW
1096 	pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
1097 	if (ipwsr & RIO_IPWSR_QF)
1098 		pr_debug(" QF");
1099 	if (ipwsr & RIO_IPWSR_TE)
1100 		pr_debug(" TE");
1101 	if (ipwsr & RIO_IPWSR_QFI)
1102 		pr_debug(" QFI");
1103 	if (ipwsr & RIO_IPWSR_PWD)
1104 		pr_debug(" PWD");
1105 	if (ipwsr & RIO_IPWSR_PWB)
1106 		pr_debug(" PWB");
1107 	pr_debug(" )\n");
1108 #endif
1109 	/* Schedule deferred processing if PW was received */
1110 	if (ipwsr & RIO_IPWSR_QFI) {
1111 		/* Save PW message (if there is room in FIFO),
1112 		 * otherwise discard it.
1113 		 */
1114 		if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) {
1115 			priv->port_write_msg.msg_count++;
1116 			kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt,
1117 				 RIO_PW_MSG_SIZE);
1118 		} else {
1119 			priv->port_write_msg.discard_count++;
1120 			pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n",
1121 				 priv->port_write_msg.discard_count);
1122 		}
1123 		/* Clear interrupt and issue Clear Queue command. This allows
1124 		 * another port-write to be received.
1125 		 */
1126 		out_be32(&priv->msg_regs->pwsr,	RIO_IPWSR_QFI);
1127 		out_be32(&priv->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ);
1128 
1129 		schedule_work(&priv->pw_work);
1130 	}
1131 
1132 	if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) {
1133 		priv->port_write_msg.err_count++;
1134 		pr_debug("RIO: Port-Write Transaction Err (%d)\n",
1135 			 priv->port_write_msg.err_count);
1136 		/* Clear Transaction Error: port-write controller should be
1137 		 * disabled when clearing this error
1138 		 */
1139 		out_be32(&priv->msg_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE);
1140 		out_be32(&priv->msg_regs->pwsr,	RIO_IPWSR_TE);
1141 		out_be32(&priv->msg_regs->pwmr, ipwmr);
1142 	}
1143 
1144 	if (ipwsr & RIO_IPWSR_PWD) {
1145 		priv->port_write_msg.discard_count++;
1146 		pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n",
1147 			 priv->port_write_msg.discard_count);
1148 		out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_PWD);
1149 	}
1150 
1151 pw_done:
1152 	if (epwisr & RIO_EPWISR_PINT) {
1153 		tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
1154 		pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
1155 		out_be32(priv->regs_win + RIO_LTLEDCSR, 0);
1156 	}
1157 
1158 	return IRQ_HANDLED;
1159 }
1160 
1161 static void fsl_pw_dpc(struct work_struct *work)
1162 {
1163 	struct rio_priv *priv = container_of(work, struct rio_priv, pw_work);
1164 	unsigned long flags;
1165 	u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)];
1166 
1167 	/*
1168 	 * Process port-write messages
1169 	 */
1170 	spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1171 	while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer,
1172 			 RIO_PW_MSG_SIZE)) {
1173 		/* Process one message */
1174 		spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1175 #ifdef DEBUG_PW
1176 		{
1177 		u32 i;
1178 		pr_debug("%s : Port-Write Message:", __func__);
1179 		for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) {
1180 			if ((i%4) == 0)
1181 				pr_debug("\n0x%02x: 0x%08x", i*4,
1182 					 msg_buffer[i]);
1183 			else
1184 				pr_debug(" 0x%08x", msg_buffer[i]);
1185 		}
1186 		pr_debug("\n");
1187 		}
1188 #endif
1189 		/* Pass the port-write message to RIO core for processing */
1190 		rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
1191 		spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1192 	}
1193 	spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1194 }
1195 
1196 /**
1197  * fsl_rio_pw_enable - enable/disable port-write interface init
1198  * @mport: Master port implementing the port write unit
1199  * @enable:    1=enable; 0=disable port-write message handling
1200  */
1201 static int fsl_rio_pw_enable(struct rio_mport *mport, int enable)
1202 {
1203 	struct rio_priv *priv = mport->priv;
1204 	u32 rval;
1205 
1206 	rval = in_be32(&priv->msg_regs->pwmr);
1207 
1208 	if (enable)
1209 		rval |= RIO_IPWMR_PWE;
1210 	else
1211 		rval &= ~RIO_IPWMR_PWE;
1212 
1213 	out_be32(&priv->msg_regs->pwmr, rval);
1214 
1215 	return 0;
1216 }
1217 
1218 /**
1219  * fsl_rio_port_write_init - MPC85xx port write interface init
1220  * @mport: Master port implementing the port write unit
1221  *
1222  * Initializes port write unit hardware and DMA buffer
1223  * ring. Called from fsl_rio_setup(). Returns %0 on success
1224  * or %-ENOMEM on failure.
1225  */
1226 static int fsl_rio_port_write_init(struct rio_mport *mport)
1227 {
1228 	struct rio_priv *priv = mport->priv;
1229 	int rc = 0;
1230 
1231 	/* Following configurations require a disabled port write controller */
1232 	out_be32(&priv->msg_regs->pwmr,
1233 		 in_be32(&priv->msg_regs->pwmr) & ~RIO_IPWMR_PWE);
1234 
1235 	/* Initialize port write */
1236 	priv->port_write_msg.virt = dma_alloc_coherent(priv->dev,
1237 					RIO_PW_MSG_SIZE,
1238 					&priv->port_write_msg.phys, GFP_KERNEL);
1239 	if (!priv->port_write_msg.virt) {
1240 		pr_err("RIO: unable allocate port write queue\n");
1241 		return -ENOMEM;
1242 	}
1243 
1244 	priv->port_write_msg.err_count = 0;
1245 	priv->port_write_msg.discard_count = 0;
1246 
1247 	/* Point dequeue/enqueue pointers at first entry */
1248 	out_be32(&priv->msg_regs->epwqbar, 0);
1249 	out_be32(&priv->msg_regs->pwqbar, (u32) priv->port_write_msg.phys);
1250 
1251 	pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n",
1252 		 in_be32(&priv->msg_regs->epwqbar),
1253 		 in_be32(&priv->msg_regs->pwqbar));
1254 
1255 	/* Clear interrupt status IPWSR */
1256 	out_be32(&priv->msg_regs->pwsr,
1257 		 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
1258 
1259 	/* Configure port write contoller for snooping enable all reporting,
1260 	   clear queue full */
1261 	out_be32(&priv->msg_regs->pwmr,
1262 		 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ);
1263 
1264 
1265 	/* Hook up port-write handler */
1266 	rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, 0,
1267 			 "port-write", (void *)mport);
1268 	if (rc < 0) {
1269 		pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
1270 		goto err_out;
1271 	}
1272 
1273 	INIT_WORK(&priv->pw_work, fsl_pw_dpc);
1274 	spin_lock_init(&priv->pw_fifo_lock);
1275 	if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
1276 		pr_err("FIFO allocation failed\n");
1277 		rc = -ENOMEM;
1278 		goto err_out_irq;
1279 	}
1280 
1281 	pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n",
1282 		 in_be32(&priv->msg_regs->pwmr),
1283 		 in_be32(&priv->msg_regs->pwsr));
1284 
1285 	return rc;
1286 
1287 err_out_irq:
1288 	free_irq(IRQ_RIO_PW(mport), (void *)mport);
1289 err_out:
1290 	dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE,
1291 			  priv->port_write_msg.virt,
1292 			  priv->port_write_msg.phys);
1293 	return rc;
1294 }
1295 
1296 static char *cmdline = NULL;
1297 
1298 static int fsl_rio_get_hdid(int index)
1299 {
1300 	/* XXX Need to parse multiple entries in some format */
1301 	if (!cmdline)
1302 		return -1;
1303 
1304 	return simple_strtol(cmdline, NULL, 0);
1305 }
1306 
1307 static int fsl_rio_get_cmdline(char *s)
1308 {
1309 	if (!s)
1310 		return 0;
1311 
1312 	cmdline = s;
1313 	return 1;
1314 }
1315 
1316 __setup("riohdid=", fsl_rio_get_cmdline);
1317 
1318 static inline void fsl_rio_info(struct device *dev, u32 ccsr)
1319 {
1320 	const char *str;
1321 	if (ccsr & 1) {
1322 		/* Serial phy */
1323 		switch (ccsr >> 30) {
1324 		case 0:
1325 			str = "1";
1326 			break;
1327 		case 1:
1328 			str = "4";
1329 			break;
1330 		default:
1331 			str = "Unknown";
1332 			break;
1333 		}
1334 		dev_info(dev, "Hardware port width: %s\n", str);
1335 
1336 		switch ((ccsr >> 27) & 7) {
1337 		case 0:
1338 			str = "Single-lane 0";
1339 			break;
1340 		case 1:
1341 			str = "Single-lane 2";
1342 			break;
1343 		case 2:
1344 			str = "Four-lane";
1345 			break;
1346 		default:
1347 			str = "Unknown";
1348 			break;
1349 		}
1350 		dev_info(dev, "Training connection status: %s\n", str);
1351 	} else {
1352 		/* Parallel phy */
1353 		if (!(ccsr & 0x80000000))
1354 			dev_info(dev, "Output port operating in 8-bit mode\n");
1355 		if (!(ccsr & 0x08000000))
1356 			dev_info(dev, "Input port operating in 8-bit mode\n");
1357 	}
1358 }
1359 
1360 /**
1361  * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
1362  * @dev: platform_device pointer
1363  *
1364  * Initializes MPC85xx RapidIO hardware interface, configures
1365  * master port with system-specific info, and registers the
1366  * master port with the RapidIO subsystem.
1367  */
1368 int fsl_rio_setup(struct platform_device *dev)
1369 {
1370 	struct rio_ops *ops;
1371 	struct rio_mport *port;
1372 	struct rio_priv *priv;
1373 	int rc = 0;
1374 	const u32 *dt_range, *cell;
1375 	struct resource regs;
1376 	int rlen;
1377 	u32 ccsr;
1378 	u64 law_start, law_size;
1379 	int paw, aw, sw;
1380 
1381 	if (!dev->dev.of_node) {
1382 		dev_err(&dev->dev, "Device OF-Node is NULL");
1383 		return -EFAULT;
1384 	}
1385 
1386 	rc = of_address_to_resource(dev->dev.of_node, 0, &regs);
1387 	if (rc) {
1388 		dev_err(&dev->dev, "Can't get %s property 'reg'\n",
1389 				dev->dev.of_node->full_name);
1390 		return -EFAULT;
1391 	}
1392 	dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name);
1393 	dev_info(&dev->dev, "Regs: %pR\n", &regs);
1394 
1395 	dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen);
1396 	if (!dt_range) {
1397 		dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
1398 				dev->dev.of_node->full_name);
1399 		return -EFAULT;
1400 	}
1401 
1402 	/* Get node address wide */
1403 	cell = of_get_property(dev->dev.of_node, "#address-cells", NULL);
1404 	if (cell)
1405 		aw = *cell;
1406 	else
1407 		aw = of_n_addr_cells(dev->dev.of_node);
1408 	/* Get node size wide */
1409 	cell = of_get_property(dev->dev.of_node, "#size-cells", NULL);
1410 	if (cell)
1411 		sw = *cell;
1412 	else
1413 		sw = of_n_size_cells(dev->dev.of_node);
1414 	/* Get parent address wide wide */
1415 	paw = of_n_addr_cells(dev->dev.of_node);
1416 
1417 	law_start = of_read_number(dt_range + aw, paw);
1418 	law_size = of_read_number(dt_range + aw + paw, sw);
1419 
1420 	dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n",
1421 			law_start, law_size);
1422 
1423 	ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
1424 	if (!ops) {
1425 		rc = -ENOMEM;
1426 		goto err_ops;
1427 	}
1428 	ops->lcread = fsl_local_config_read;
1429 	ops->lcwrite = fsl_local_config_write;
1430 	ops->cread = fsl_rio_config_read;
1431 	ops->cwrite = fsl_rio_config_write;
1432 	ops->dsend = fsl_rio_doorbell_send;
1433 	ops->pwenable = fsl_rio_pw_enable;
1434 
1435 	port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
1436 	if (!port) {
1437 		rc = -ENOMEM;
1438 		goto err_port;
1439 	}
1440 	port->id = 0;
1441 	port->index = 0;
1442 
1443 	priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
1444 	if (!priv) {
1445 		printk(KERN_ERR "Can't alloc memory for 'priv'\n");
1446 		rc = -ENOMEM;
1447 		goto err_priv;
1448 	}
1449 
1450 	INIT_LIST_HEAD(&port->dbells);
1451 	port->iores.start = law_start;
1452 	port->iores.end = law_start + law_size - 1;
1453 	port->iores.flags = IORESOURCE_MEM;
1454 	port->iores.name = "rio_io_win";
1455 
1456 	priv->pwirq   = irq_of_parse_and_map(dev->dev.of_node, 0);
1457 	priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2);
1458 	priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3);
1459 	priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4);
1460 	dev_info(&dev->dev, "pwirq: %d, bellirq: %d, txirq: %d, rxirq %d\n",
1461 		 priv->pwirq, priv->bellirq, priv->txirq, priv->rxirq);
1462 
1463 	rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
1464 	rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
1465 	rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
1466 	strcpy(port->name, "RIO0 mport");
1467 
1468 	priv->dev = &dev->dev;
1469 
1470 	port->ops = ops;
1471 	port->host_deviceid = fsl_rio_get_hdid(port->id);
1472 
1473 	port->priv = priv;
1474 	port->phys_efptr = 0x100;
1475 	rio_register_mport(port);
1476 
1477 	priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1);
1478 	rio_regs_win = priv->regs_win;
1479 
1480 	/* Probe the master port phy type */
1481 	ccsr = in_be32(priv->regs_win + RIO_CCSR);
1482 	port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
1483 	dev_info(&dev->dev, "RapidIO PHY type: %s\n",
1484 			(port->phy_type == RIO_PHY_PARALLEL) ? "parallel" :
1485 			((port->phy_type == RIO_PHY_SERIAL) ? "serial" :
1486 			 "unknown"));
1487 	/* Checking the port training status */
1488 	if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1489 		dev_err(&dev->dev, "Port is not ready. "
1490 				   "Try to restart connection...\n");
1491 		switch (port->phy_type) {
1492 		case RIO_PHY_SERIAL:
1493 			/* Disable ports */
1494 			out_be32(priv->regs_win + RIO_CCSR, 0);
1495 			/* Set 1x lane */
1496 			setbits32(priv->regs_win + RIO_CCSR, 0x02000000);
1497 			/* Enable ports */
1498 			setbits32(priv->regs_win + RIO_CCSR, 0x00600000);
1499 			break;
1500 		case RIO_PHY_PARALLEL:
1501 			/* Disable ports */
1502 			out_be32(priv->regs_win + RIO_CCSR, 0x22000000);
1503 			/* Enable ports */
1504 			out_be32(priv->regs_win + RIO_CCSR, 0x44000000);
1505 			break;
1506 		}
1507 		msleep(100);
1508 		if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1509 			dev_err(&dev->dev, "Port restart failed.\n");
1510 			rc = -ENOLINK;
1511 			goto err;
1512 		}
1513 		dev_info(&dev->dev, "Port restart success!\n");
1514 	}
1515 	fsl_rio_info(&dev->dev, ccsr);
1516 
1517 	port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
1518 					& RIO_PEF_CTLS) >> 4;
1519 	dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
1520 			port->sys_size ? 65536 : 256);
1521 
1522 	if (port->host_deviceid >= 0)
1523 		out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
1524 			RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
1525 	else
1526 		out_be32(priv->regs_win + RIO_GCCSR, 0x00000000);
1527 
1528 	priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
1529 					+ RIO_ATMU_REGS_OFFSET);
1530 	priv->maint_atmu_regs = priv->atmu_regs + 1;
1531 	priv->dbell_atmu_regs = priv->atmu_regs + 2;
1532 	priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win +
1533 				((port->phy_type == RIO_PHY_SERIAL) ?
1534 				RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET));
1535 
1536 	/* Set to receive any dist ID for serial RapidIO controller. */
1537 	if (port->phy_type == RIO_PHY_SERIAL)
1538 		out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA);
1539 
1540 	/* Configure maintenance transaction window */
1541 	out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12);
1542 	out_be32(&priv->maint_atmu_regs->rowar,
1543 		 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
1544 
1545 	priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE);
1546 
1547 	/* Configure outbound doorbell window */
1548 	out_be32(&priv->dbell_atmu_regs->rowbar,
1549 			(law_start + RIO_MAINT_WIN_SIZE) >> 12);
1550 	out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b);	/* 4k */
1551 	fsl_rio_doorbell_init(port);
1552 	fsl_rio_port_write_init(port);
1553 
1554 #ifdef CONFIG_E500
1555 	saved_mcheck_exception = ppc_md.machine_check_exception;
1556 	ppc_md.machine_check_exception = fsl_rio_mcheck_exception;
1557 #endif
1558 
1559 	return 0;
1560 err:
1561 	iounmap(priv->regs_win);
1562 	kfree(priv);
1563 err_priv:
1564 	kfree(port);
1565 err_port:
1566 	kfree(ops);
1567 err_ops:
1568 	return rc;
1569 }
1570 
1571 /* The probe function for RapidIO peer-to-peer network.
1572  */
1573 static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev,
1574 				     const struct of_device_id *match)
1575 {
1576 	int rc;
1577 	printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
1578 			dev->dev.of_node->full_name);
1579 
1580 	rc = fsl_rio_setup(dev);
1581 	if (rc)
1582 		goto out;
1583 
1584 	/* Enumerate all registered ports */
1585 	rc = rio_init_mports();
1586 out:
1587 	return rc;
1588 };
1589 
1590 static const struct of_device_id fsl_of_rio_rpn_ids[] = {
1591 	{
1592 		.compatible = "fsl,rapidio-delta",
1593 	},
1594 	{},
1595 };
1596 
1597 static struct of_platform_driver fsl_of_rio_rpn_driver = {
1598 	.driver = {
1599 		.name = "fsl-of-rio",
1600 		.owner = THIS_MODULE,
1601 		.of_match_table = fsl_of_rio_rpn_ids,
1602 	},
1603 	.probe = fsl_of_rio_rpn_probe,
1604 };
1605 
1606 static __init int fsl_of_rio_rpn_init(void)
1607 {
1608 	return of_register_platform_driver(&fsl_of_rio_rpn_driver);
1609 }
1610 
1611 subsys_initcall(fsl_of_rio_rpn_init);
1612