12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2de3c8d41SKumar Gala /*
3d02443a6SZhang Wei * Freescale MPC85xx/MPC86xx RapidIO support
4de3c8d41SKumar Gala *
5bd4fb654SThomas Moll * Copyright 2009 Sysgo AG
6bd4fb654SThomas Moll * Thomas Moll <thomas.moll@sysgo.com>
7bd4fb654SThomas Moll * - fixed maintenance access routines, check for aligned access
8bd4fb654SThomas Moll *
95b2074aeSAlexandre Bounine * Copyright 2009 Integrated Device Technology, Inc.
105b2074aeSAlexandre Bounine * Alex Bounine <alexandre.bounine@idt.com>
115b2074aeSAlexandre Bounine * - Added Port-Write message handling
125b2074aeSAlexandre Bounine * - Added Machine Check exception handling
135b2074aeSAlexandre Bounine *
146ec4bedbSLiu Gang * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
15ad1e9380SZhang Wei * Zhang Wei <wei.zhang@freescale.com>
16ad1e9380SZhang Wei *
17de3c8d41SKumar Gala * Copyright 2005 MontaVista Software, Inc.
18de3c8d41SKumar Gala * Matt Porter <mporter@kernel.crashing.org>
19de3c8d41SKumar Gala */
20de3c8d41SKumar Gala
21de3c8d41SKumar Gala #include <linux/init.h>
228a39b05fSPaul Gortmaker #include <linux/extable.h>
23de3c8d41SKumar Gala #include <linux/types.h>
24de3c8d41SKumar Gala #include <linux/dma-mapping.h>
25de3c8d41SKumar Gala #include <linux/interrupt.h>
2681d7cac4SRob Herring #include <linux/of.h>
2726a2056eSRob Herring #include <linux/of_address.h>
2826a2056eSRob Herring #include <linux/of_irq.h>
2981d7cac4SRob Herring #include <linux/platform_device.h>
3061b26917SZhang Wei #include <linux/delay.h>
315a0e3ad6STejun Heo #include <linux/slab.h>
32de3c8d41SKumar Gala
336ec4bedbSLiu Gang #include <linux/io.h>
346ec4bedbSLiu Gang #include <linux/uaccess.h>
35a52c8f52SAlexandre Bounine #include <asm/machdep.h>
36*c265735fSChristophe Leroy #include <asm/rio.h>
376ec4bedbSLiu Gang
386ec4bedbSLiu Gang #include "fsl_rio.h"
39de3c8d41SKumar Gala
405b2074aeSAlexandre Bounine #undef DEBUG_PW /* Port-Write debugging */
415b2074aeSAlexandre Bounine
426ff31453SShaohui Xie #define RIO_PORT1_EDCSR 0x0640
436ff31453SShaohui Xie #define RIO_PORT2_EDCSR 0x0680
446ff31453SShaohui Xie #define RIO_PORT1_IECSR 0x10130
456ff31453SShaohui Xie #define RIO_PORT2_IECSR 0x101B0
466ff31453SShaohui Xie
47af84ca38SAlexandre Bounine #define RIO_GCCSR 0x13c
4861b26917SZhang Wei #define RIO_ESCSR 0x158
496ec4bedbSLiu Gang #define ESCSR_CLEAR 0x07120204
506ff31453SShaohui Xie #define RIO_PORT2_ESCSR 0x178
5161b26917SZhang Wei #define RIO_CCSR 0x15c
52a52c8f52SAlexandre Bounine #define RIO_LTLEDCSR_IER 0x80000000
53a52c8f52SAlexandre Bounine #define RIO_LTLEDCSR_PRT 0x01000000
546ec4bedbSLiu Gang #define IECSR_CLEAR 0x80000000
5561b26917SZhang Wei #define RIO_ISR_AACR 0x10120
5661b26917SZhang Wei #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
57de3c8d41SKumar Gala
58e6a546fdSMartijn de Gouw #define RIWTAR_TRAD_VAL_SHIFT 12
59e6a546fdSMartijn de Gouw #define RIWTAR_TRAD_MASK 0x00FFFFFF
60e6a546fdSMartijn de Gouw #define RIWBAR_BADD_VAL_SHIFT 12
61e6a546fdSMartijn de Gouw #define RIWBAR_BADD_MASK 0x003FFFFF
62e6a546fdSMartijn de Gouw #define RIWAR_ENABLE 0x80000000
63e6a546fdSMartijn de Gouw #define RIWAR_TGINT_LOCAL 0x00F00000
64e6a546fdSMartijn de Gouw #define RIWAR_RDTYP_NO_SNOOP 0x00040000
65e6a546fdSMartijn de Gouw #define RIWAR_RDTYP_SNOOP 0x00050000
66e6a546fdSMartijn de Gouw #define RIWAR_WRTYP_NO_SNOOP 0x00004000
67e6a546fdSMartijn de Gouw #define RIWAR_WRTYP_SNOOP 0x00005000
68e6a546fdSMartijn de Gouw #define RIWAR_WRTYP_ALLOC 0x00006000
69e6a546fdSMartijn de Gouw #define RIWAR_SIZE_MASK 0x0000003F
70e6a546fdSMartijn de Gouw
7131d1e130SIoan Nicu static DEFINE_SPINLOCK(fsl_rio_config_lock);
7231d1e130SIoan Nicu
732255411dSChristophe Leroy #define ___fsl_read_rio_config(x, addr, err, op, barrier) \
74a52c8f52SAlexandre Bounine __asm__ __volatile__( \
75a52c8f52SAlexandre Bounine "1: "op" %1,0(%2)\n" \
762255411dSChristophe Leroy " "barrier"\n" \
77a52c8f52SAlexandre Bounine "2:\n" \
78a52c8f52SAlexandre Bounine ".section .fixup,\"ax\"\n" \
79a52c8f52SAlexandre Bounine "3: li %1,-1\n" \
80a52c8f52SAlexandre Bounine " li %0,%3\n" \
81a52c8f52SAlexandre Bounine " b 2b\n" \
8224bfa6a9SNicholas Piggin ".previous\n" \
8324bfa6a9SNicholas Piggin EX_TABLE(1b, 3b) \
84a52c8f52SAlexandre Bounine : "=r" (err), "=r" (x) \
85a52c8f52SAlexandre Bounine : "b" (addr), "i" (-EFAULT), "0" (err))
86a52c8f52SAlexandre Bounine
872255411dSChristophe Leroy #ifdef CONFIG_BOOKE
882255411dSChristophe Leroy #define __fsl_read_rio_config(x, addr, err, op) \
892255411dSChristophe Leroy ___fsl_read_rio_config(x, addr, err, op, "mbar")
902255411dSChristophe Leroy #else
912255411dSChristophe Leroy #define __fsl_read_rio_config(x, addr, err, op) \
922255411dSChristophe Leroy ___fsl_read_rio_config(x, addr, err, op, "eieio")
932255411dSChristophe Leroy #endif
942255411dSChristophe Leroy
956ec4bedbSLiu Gang void __iomem *rio_regs_win;
96abc3aeaeSLiu Gang void __iomem *rmu_regs_win;
97abc3aeaeSLiu Gang resource_size_t rio_law_start;
98abc3aeaeSLiu Gang
99abc3aeaeSLiu Gang struct fsl_rio_dbell *dbell;
100abc3aeaeSLiu Gang struct fsl_rio_pw *pw;
101a52c8f52SAlexandre Bounine
102688de017SChristophe Leroy #ifdef CONFIG_PPC_E500
fsl_rio_mcheck_exception(struct pt_regs * regs)103cce1f106SShaohui Xie int fsl_rio_mcheck_exception(struct pt_regs *regs)
104a52c8f52SAlexandre Bounine {
10582a9a480SScott Wood const struct exception_table_entry *entry;
10682a9a480SScott Wood unsigned long reason;
107a52c8f52SAlexandre Bounine
10882a9a480SScott Wood if (!rio_regs_win)
10982a9a480SScott Wood return 0;
11082a9a480SScott Wood
111a52c8f52SAlexandre Bounine reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
112a52c8f52SAlexandre Bounine if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
113a52c8f52SAlexandre Bounine /* Check if we are prepared to handle this fault */
114a52c8f52SAlexandre Bounine entry = search_exception_tables(regs->nip);
115a52c8f52SAlexandre Bounine if (entry) {
116a52c8f52SAlexandre Bounine pr_debug("RIO: %s - MC Exception handled\n",
117a52c8f52SAlexandre Bounine __func__);
118a52c8f52SAlexandre Bounine out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
119a52c8f52SAlexandre Bounine 0);
120806c0e6eSChristophe Leroy regs_set_recoverable(regs);
12159dc5bfcSNicholas Piggin regs_set_return_ip(regs, extable_fixup(entry));
122a52c8f52SAlexandre Bounine return 1;
123a52c8f52SAlexandre Bounine }
124a52c8f52SAlexandre Bounine }
125a52c8f52SAlexandre Bounine
126cce1f106SShaohui Xie return 0;
127a52c8f52SAlexandre Bounine }
128cce1f106SShaohui Xie EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
129ff33f182SLi Yang #endif
130a52c8f52SAlexandre Bounine
131de3c8d41SKumar Gala /**
132d02443a6SZhang Wei * fsl_local_config_read - Generate a MPC85xx local config space read
1339941d945SRandy Dunlap * @mport: RapidIO master port info
134de3c8d41SKumar Gala * @index: ID of RapdiIO interface
135de3c8d41SKumar Gala * @offset: Offset into configuration space
136de3c8d41SKumar Gala * @len: Length (in bytes) of the maintenance transaction
137de3c8d41SKumar Gala * @data: Value to be read into
138de3c8d41SKumar Gala *
139de3c8d41SKumar Gala * Generates a MPC85xx local configuration space read. Returns %0 on
140de3c8d41SKumar Gala * success or %-EINVAL on failure.
141de3c8d41SKumar Gala */
fsl_local_config_read(struct rio_mport * mport,int index,u32 offset,int len,u32 * data)142ad1e9380SZhang Wei static int fsl_local_config_read(struct rio_mport *mport,
143ad1e9380SZhang Wei int index, u32 offset, int len, u32 *data)
144de3c8d41SKumar Gala {
145ad1e9380SZhang Wei struct rio_priv *priv = mport->priv;
146d02443a6SZhang Wei pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
147de3c8d41SKumar Gala offset);
148ad1e9380SZhang Wei *data = in_be32(priv->regs_win + offset);
149de3c8d41SKumar Gala
150de3c8d41SKumar Gala return 0;
151de3c8d41SKumar Gala }
152de3c8d41SKumar Gala
153de3c8d41SKumar Gala /**
154d02443a6SZhang Wei * fsl_local_config_write - Generate a MPC85xx local config space write
1559941d945SRandy Dunlap * @mport: RapidIO master port info
156de3c8d41SKumar Gala * @index: ID of RapdiIO interface
157de3c8d41SKumar Gala * @offset: Offset into configuration space
158de3c8d41SKumar Gala * @len: Length (in bytes) of the maintenance transaction
159de3c8d41SKumar Gala * @data: Value to be written
160de3c8d41SKumar Gala *
161de3c8d41SKumar Gala * Generates a MPC85xx local configuration space write. Returns %0 on
162de3c8d41SKumar Gala * success or %-EINVAL on failure.
163de3c8d41SKumar Gala */
fsl_local_config_write(struct rio_mport * mport,int index,u32 offset,int len,u32 data)164ad1e9380SZhang Wei static int fsl_local_config_write(struct rio_mport *mport,
165ad1e9380SZhang Wei int index, u32 offset, int len, u32 data)
166de3c8d41SKumar Gala {
167ad1e9380SZhang Wei struct rio_priv *priv = mport->priv;
168de3c8d41SKumar Gala pr_debug
169d02443a6SZhang Wei ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
170de3c8d41SKumar Gala index, offset, data);
171ad1e9380SZhang Wei out_be32(priv->regs_win + offset, data);
172de3c8d41SKumar Gala
173de3c8d41SKumar Gala return 0;
174de3c8d41SKumar Gala }
175de3c8d41SKumar Gala
176de3c8d41SKumar Gala /**
177d02443a6SZhang Wei * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
1789941d945SRandy Dunlap * @mport: RapidIO master port info
179de3c8d41SKumar Gala * @index: ID of RapdiIO interface
180de3c8d41SKumar Gala * @destid: Destination ID of transaction
181de3c8d41SKumar Gala * @hopcount: Number of hops to target device
182de3c8d41SKumar Gala * @offset: Offset into configuration space
183de3c8d41SKumar Gala * @len: Length (in bytes) of the maintenance transaction
184de3c8d41SKumar Gala * @val: Location to be read into
185de3c8d41SKumar Gala *
186de3c8d41SKumar Gala * Generates a MPC85xx read maintenance transaction. Returns %0 on
187de3c8d41SKumar Gala * success or %-EINVAL on failure.
188de3c8d41SKumar Gala */
189de3c8d41SKumar Gala static int
fsl_rio_config_read(struct rio_mport * mport,int index,u16 destid,u8 hopcount,u32 offset,int len,u32 * val)190ad1e9380SZhang Wei fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
191ad1e9380SZhang Wei u8 hopcount, u32 offset, int len, u32 *val)
192de3c8d41SKumar Gala {
193ad1e9380SZhang Wei struct rio_priv *priv = mport->priv;
19431d1e130SIoan Nicu unsigned long flags;
195de3c8d41SKumar Gala u8 *data;
196a52c8f52SAlexandre Bounine u32 rval, err = 0;
197de3c8d41SKumar Gala
198de3c8d41SKumar Gala pr_debug
1996ec4bedbSLiu Gang ("fsl_rio_config_read:"
2006ec4bedbSLiu Gang " index %d destid %d hopcount %d offset %8.8x len %d\n",
201de3c8d41SKumar Gala index, destid, hopcount, offset, len);
202de3c8d41SKumar Gala
203bd4fb654SThomas Moll /* 16MB maintenance window possible */
204bd4fb654SThomas Moll /* allow only aligned access to maintenance registers */
205bd4fb654SThomas Moll if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
206bd4fb654SThomas Moll return -EINVAL;
207bd4fb654SThomas Moll
20831d1e130SIoan Nicu spin_lock_irqsave(&fsl_rio_config_lock, flags);
20931d1e130SIoan Nicu
210bd4fb654SThomas Moll out_be32(&priv->maint_atmu_regs->rowtar,
211bd4fb654SThomas Moll (destid << 22) | (hopcount << 12) | (offset >> 12));
212bd4fb654SThomas Moll out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
213bd4fb654SThomas Moll
214bd4fb654SThomas Moll data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
215de3c8d41SKumar Gala switch (len) {
216de3c8d41SKumar Gala case 1:
217a52c8f52SAlexandre Bounine __fsl_read_rio_config(rval, data, err, "lbz");
218de3c8d41SKumar Gala break;
219de3c8d41SKumar Gala case 2:
220a52c8f52SAlexandre Bounine __fsl_read_rio_config(rval, data, err, "lhz");
221de3c8d41SKumar Gala break;
222bd4fb654SThomas Moll case 4:
223a52c8f52SAlexandre Bounine __fsl_read_rio_config(rval, data, err, "lwz");
224de3c8d41SKumar Gala break;
225bd4fb654SThomas Moll default:
22631d1e130SIoan Nicu spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
227bd4fb654SThomas Moll return -EINVAL;
228de3c8d41SKumar Gala }
229de3c8d41SKumar Gala
230a52c8f52SAlexandre Bounine if (err) {
231a52c8f52SAlexandre Bounine pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
232a52c8f52SAlexandre Bounine err, destid, hopcount, offset);
233a52c8f52SAlexandre Bounine }
234a52c8f52SAlexandre Bounine
23531d1e130SIoan Nicu spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
236a52c8f52SAlexandre Bounine *val = rval;
237a52c8f52SAlexandre Bounine
238a52c8f52SAlexandre Bounine return err;
239de3c8d41SKumar Gala }
240de3c8d41SKumar Gala
241de3c8d41SKumar Gala /**
242d02443a6SZhang Wei * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
2439941d945SRandy Dunlap * @mport: RapidIO master port info
244de3c8d41SKumar Gala * @index: ID of RapdiIO interface
245de3c8d41SKumar Gala * @destid: Destination ID of transaction
246de3c8d41SKumar Gala * @hopcount: Number of hops to target device
247de3c8d41SKumar Gala * @offset: Offset into configuration space
248de3c8d41SKumar Gala * @len: Length (in bytes) of the maintenance transaction
249de3c8d41SKumar Gala * @val: Value to be written
250de3c8d41SKumar Gala *
251de3c8d41SKumar Gala * Generates an MPC85xx write maintenance transaction. Returns %0 on
252de3c8d41SKumar Gala * success or %-EINVAL on failure.
253de3c8d41SKumar Gala */
254de3c8d41SKumar Gala static int
fsl_rio_config_write(struct rio_mport * mport,int index,u16 destid,u8 hopcount,u32 offset,int len,u32 val)255ad1e9380SZhang Wei fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
256ad1e9380SZhang Wei u8 hopcount, u32 offset, int len, u32 val)
257de3c8d41SKumar Gala {
258ad1e9380SZhang Wei struct rio_priv *priv = mport->priv;
25931d1e130SIoan Nicu unsigned long flags;
260de3c8d41SKumar Gala u8 *data;
26131d1e130SIoan Nicu int ret = 0;
26231d1e130SIoan Nicu
263de3c8d41SKumar Gala pr_debug
2646ec4bedbSLiu Gang ("fsl_rio_config_write:"
2656ec4bedbSLiu Gang " index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
266de3c8d41SKumar Gala index, destid, hopcount, offset, len, val);
267de3c8d41SKumar Gala
268bd4fb654SThomas Moll /* 16MB maintenance windows possible */
269bd4fb654SThomas Moll /* allow only aligned access to maintenance registers */
270bd4fb654SThomas Moll if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
271bd4fb654SThomas Moll return -EINVAL;
272bd4fb654SThomas Moll
27331d1e130SIoan Nicu spin_lock_irqsave(&fsl_rio_config_lock, flags);
27431d1e130SIoan Nicu
275bd4fb654SThomas Moll out_be32(&priv->maint_atmu_regs->rowtar,
276bd4fb654SThomas Moll (destid << 22) | (hopcount << 12) | (offset >> 12));
277bd4fb654SThomas Moll out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
278bd4fb654SThomas Moll
279bd4fb654SThomas Moll data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
280de3c8d41SKumar Gala switch (len) {
281de3c8d41SKumar Gala case 1:
282de3c8d41SKumar Gala out_8((u8 *) data, val);
283de3c8d41SKumar Gala break;
284de3c8d41SKumar Gala case 2:
285de3c8d41SKumar Gala out_be16((u16 *) data, val);
286de3c8d41SKumar Gala break;
287bd4fb654SThomas Moll case 4:
288de3c8d41SKumar Gala out_be32((u32 *) data, val);
289de3c8d41SKumar Gala break;
290bd4fb654SThomas Moll default:
29131d1e130SIoan Nicu ret = -EINVAL;
292de3c8d41SKumar Gala }
29331d1e130SIoan Nicu spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
294de3c8d41SKumar Gala
29531d1e130SIoan Nicu return ret;
296de3c8d41SKumar Gala }
297de3c8d41SKumar Gala
fsl_rio_inbound_mem_init(struct rio_priv * priv)298e6a546fdSMartijn de Gouw static void fsl_rio_inbound_mem_init(struct rio_priv *priv)
299e6a546fdSMartijn de Gouw {
300e6a546fdSMartijn de Gouw int i;
301e6a546fdSMartijn de Gouw
302e6a546fdSMartijn de Gouw /* close inbound windows */
303e6a546fdSMartijn de Gouw for (i = 0; i < RIO_INB_ATMU_COUNT; i++)
304e6a546fdSMartijn de Gouw out_be32(&priv->inb_atmu_regs[i].riwar, 0);
305e6a546fdSMartijn de Gouw }
306e6a546fdSMartijn de Gouw
fsl_map_inb_mem(struct rio_mport * mport,dma_addr_t lstart,u64 rstart,u64 size,u32 flags)307*c265735fSChristophe Leroy static int fsl_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
308a057a52eSAlexandre Bounine u64 rstart, u64 size, u32 flags)
309e6a546fdSMartijn de Gouw {
310e6a546fdSMartijn de Gouw struct rio_priv *priv = mport->priv;
311e6a546fdSMartijn de Gouw u32 base_size;
312e6a546fdSMartijn de Gouw unsigned int base_size_log;
313e6a546fdSMartijn de Gouw u64 win_start, win_end;
314e6a546fdSMartijn de Gouw u32 riwar;
315e6a546fdSMartijn de Gouw int i;
316e6a546fdSMartijn de Gouw
317a057a52eSAlexandre Bounine if ((size & (size - 1)) != 0 || size > 0x400000000ULL)
318e6a546fdSMartijn de Gouw return -EINVAL;
319e6a546fdSMartijn de Gouw
320e6a546fdSMartijn de Gouw base_size_log = ilog2(size);
321e6a546fdSMartijn de Gouw base_size = 1 << base_size_log;
322e6a546fdSMartijn de Gouw
323e6a546fdSMartijn de Gouw /* check if addresses are aligned with the window size */
324e6a546fdSMartijn de Gouw if (lstart & (base_size - 1))
325e6a546fdSMartijn de Gouw return -EINVAL;
326e6a546fdSMartijn de Gouw if (rstart & (base_size - 1))
327e6a546fdSMartijn de Gouw return -EINVAL;
328e6a546fdSMartijn de Gouw
329e6a546fdSMartijn de Gouw /* check for conflicting ranges */
330e6a546fdSMartijn de Gouw for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
331e6a546fdSMartijn de Gouw riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
332e6a546fdSMartijn de Gouw if ((riwar & RIWAR_ENABLE) == 0)
333e6a546fdSMartijn de Gouw continue;
334e6a546fdSMartijn de Gouw win_start = ((u64)(in_be32(&priv->inb_atmu_regs[i].riwbar) & RIWBAR_BADD_MASK))
335e6a546fdSMartijn de Gouw << RIWBAR_BADD_VAL_SHIFT;
336e6a546fdSMartijn de Gouw win_end = win_start + ((1 << ((riwar & RIWAR_SIZE_MASK) + 1)) - 1);
337e6a546fdSMartijn de Gouw if (rstart < win_end && (rstart + size) > win_start)
338e6a546fdSMartijn de Gouw return -EINVAL;
339e6a546fdSMartijn de Gouw }
340e6a546fdSMartijn de Gouw
341e6a546fdSMartijn de Gouw /* find unused atmu */
342e6a546fdSMartijn de Gouw for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
343e6a546fdSMartijn de Gouw riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
344e6a546fdSMartijn de Gouw if ((riwar & RIWAR_ENABLE) == 0)
345e6a546fdSMartijn de Gouw break;
346e6a546fdSMartijn de Gouw }
347e6a546fdSMartijn de Gouw if (i >= RIO_INB_ATMU_COUNT)
348e6a546fdSMartijn de Gouw return -ENOMEM;
349e6a546fdSMartijn de Gouw
350e6a546fdSMartijn de Gouw out_be32(&priv->inb_atmu_regs[i].riwtar, lstart >> RIWTAR_TRAD_VAL_SHIFT);
351e6a546fdSMartijn de Gouw out_be32(&priv->inb_atmu_regs[i].riwbar, rstart >> RIWBAR_BADD_VAL_SHIFT);
352e6a546fdSMartijn de Gouw out_be32(&priv->inb_atmu_regs[i].riwar, RIWAR_ENABLE | RIWAR_TGINT_LOCAL |
353e6a546fdSMartijn de Gouw RIWAR_RDTYP_SNOOP | RIWAR_WRTYP_SNOOP | (base_size_log - 1));
354e6a546fdSMartijn de Gouw
355e6a546fdSMartijn de Gouw return 0;
356e6a546fdSMartijn de Gouw }
357e6a546fdSMartijn de Gouw
fsl_unmap_inb_mem(struct rio_mport * mport,dma_addr_t lstart)358*c265735fSChristophe Leroy static void fsl_unmap_inb_mem(struct rio_mport *mport, dma_addr_t lstart)
359e6a546fdSMartijn de Gouw {
360e6a546fdSMartijn de Gouw u32 win_start_shift, base_start_shift;
361e6a546fdSMartijn de Gouw struct rio_priv *priv = mport->priv;
362e6a546fdSMartijn de Gouw u32 riwar, riwtar;
363e6a546fdSMartijn de Gouw int i;
364e6a546fdSMartijn de Gouw
365e6a546fdSMartijn de Gouw /* skip default window */
366e6a546fdSMartijn de Gouw base_start_shift = lstart >> RIWTAR_TRAD_VAL_SHIFT;
367e6a546fdSMartijn de Gouw for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
368e6a546fdSMartijn de Gouw riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
369e6a546fdSMartijn de Gouw if ((riwar & RIWAR_ENABLE) == 0)
370e6a546fdSMartijn de Gouw continue;
371e6a546fdSMartijn de Gouw
372e6a546fdSMartijn de Gouw riwtar = in_be32(&priv->inb_atmu_regs[i].riwtar);
373e6a546fdSMartijn de Gouw win_start_shift = riwtar & RIWTAR_TRAD_MASK;
374e6a546fdSMartijn de Gouw if (win_start_shift == base_start_shift) {
375e6a546fdSMartijn de Gouw out_be32(&priv->inb_atmu_regs[i].riwar, riwar & ~RIWAR_ENABLE);
376e6a546fdSMartijn de Gouw return;
377e6a546fdSMartijn de Gouw }
378e6a546fdSMartijn de Gouw }
379e6a546fdSMartijn de Gouw }
380e6a546fdSMartijn de Gouw
fsl_rio_port_error_handler(int offset)381abc3aeaeSLiu Gang void fsl_rio_port_error_handler(int offset)
3826ff31453SShaohui Xie {
3836ff31453SShaohui Xie /*XXX: Error recovery is not implemented, we just clear errors */
3846ff31453SShaohui Xie out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
3856ff31453SShaohui Xie
3866ff31453SShaohui Xie if (offset == 0) {
3876ff31453SShaohui Xie out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);
388671ee7f0SLiu Gang-B34182 out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR);
3896ff31453SShaohui Xie out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
3906ff31453SShaohui Xie } else {
3916ff31453SShaohui Xie out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);
392671ee7f0SLiu Gang-B34182 out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR);
3936ff31453SShaohui Xie out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
3946ff31453SShaohui Xie }
3956ff31453SShaohui Xie }
fsl_rio_info(struct device * dev,u32 ccsr)3967f620df8SZhang Wei static inline void fsl_rio_info(struct device *dev, u32 ccsr)
3977f620df8SZhang Wei {
3987f620df8SZhang Wei const char *str;
3997f620df8SZhang Wei if (ccsr & 1) {
4007f620df8SZhang Wei /* Serial phy */
4017f620df8SZhang Wei switch (ccsr >> 30) {
4027f620df8SZhang Wei case 0:
4037f620df8SZhang Wei str = "1";
4047f620df8SZhang Wei break;
4057f620df8SZhang Wei case 1:
4067f620df8SZhang Wei str = "4";
4077f620df8SZhang Wei break;
4087f620df8SZhang Wei default:
4097f620df8SZhang Wei str = "Unknown";
410d258e64eSJoe Perches break;
4117f620df8SZhang Wei }
4127f620df8SZhang Wei dev_info(dev, "Hardware port width: %s\n", str);
4137f620df8SZhang Wei
4147f620df8SZhang Wei switch ((ccsr >> 27) & 7) {
4157f620df8SZhang Wei case 0:
4167f620df8SZhang Wei str = "Single-lane 0";
4177f620df8SZhang Wei break;
4187f620df8SZhang Wei case 1:
4197f620df8SZhang Wei str = "Single-lane 2";
4207f620df8SZhang Wei break;
4217f620df8SZhang Wei case 2:
4227f620df8SZhang Wei str = "Four-lane";
4237f620df8SZhang Wei break;
4247f620df8SZhang Wei default:
4257f620df8SZhang Wei str = "Unknown";
4267f620df8SZhang Wei break;
4277f620df8SZhang Wei }
4287f620df8SZhang Wei dev_info(dev, "Training connection status: %s\n", str);
4297f620df8SZhang Wei } else {
4307f620df8SZhang Wei /* Parallel phy */
4317f620df8SZhang Wei if (!(ccsr & 0x80000000))
4327f620df8SZhang Wei dev_info(dev, "Output port operating in 8-bit mode\n");
4337f620df8SZhang Wei if (!(ccsr & 0x08000000))
4347f620df8SZhang Wei dev_info(dev, "Input port operating in 8-bit mode\n");
4357f620df8SZhang Wei }
4367f620df8SZhang Wei }
4377f620df8SZhang Wei
438de3c8d41SKumar Gala /**
4399941d945SRandy Dunlap * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
4402dc11581SGrant Likely * @dev: platform_device pointer
441de3c8d41SKumar Gala *
442de3c8d41SKumar Gala * Initializes MPC85xx RapidIO hardware interface, configures
443de3c8d41SKumar Gala * master port with system-specific info, and registers the
444de3c8d41SKumar Gala * master port with the RapidIO subsystem.
445de3c8d41SKumar Gala */
fsl_rio_setup(struct platform_device * dev)446*c265735fSChristophe Leroy static int fsl_rio_setup(struct platform_device *dev)
447de3c8d41SKumar Gala {
448de3c8d41SKumar Gala struct rio_ops *ops;
449de3c8d41SKumar Gala struct rio_mport *port;
450cc2bb696SZhang Wei struct rio_priv *priv;
451cc2bb696SZhang Wei int rc = 0;
452f892ac77SRob Herring const u32 *port_index;
453abc3aeaeSLiu Gang u32 active_ports = 0;
454abc3aeaeSLiu Gang struct device_node *np, *rmu_node;
45561b26917SZhang Wei u32 ccsr;
456c4ae1799SRob Herring u64 range_start;
457abc3aeaeSLiu Gang u32 i;
458abc3aeaeSLiu Gang static int tmp;
459abc3aeaeSLiu Gang struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL};
460cc2bb696SZhang Wei
46161c7a080SGrant Likely if (!dev->dev.of_node) {
462cc2bb696SZhang Wei dev_err(&dev->dev, "Device OF-Node is NULL");
463abc3aeaeSLiu Gang return -ENODEV;
464cc2bb696SZhang Wei }
465cc2bb696SZhang Wei
466de8d11bcSRob Herring rio_regs_win = of_iomap(dev->dev.of_node, 0);
467abc3aeaeSLiu Gang if (!rio_regs_win) {
468abc3aeaeSLiu Gang dev_err(&dev->dev, "Unable to map rio register window\n");
469abc3aeaeSLiu Gang rc = -ENOMEM;
470abc3aeaeSLiu Gang goto err_rio_regs;
471cc2bb696SZhang Wei }
472cc2bb696SZhang Wei
473e5cabeb3SAlexandre Bounine ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
4746c75933cSJulia Lawall if (!ops) {
4756c75933cSJulia Lawall rc = -ENOMEM;
4766c75933cSJulia Lawall goto err_ops;
4776c75933cSJulia Lawall }
478d02443a6SZhang Wei ops->lcread = fsl_local_config_read;
479d02443a6SZhang Wei ops->lcwrite = fsl_local_config_write;
480d02443a6SZhang Wei ops->cread = fsl_rio_config_read;
481d02443a6SZhang Wei ops->cwrite = fsl_rio_config_write;
482abc3aeaeSLiu Gang ops->dsend = fsl_rio_doorbell_send;
4835b2074aeSAlexandre Bounine ops->pwenable = fsl_rio_pw_enable;
484abc3aeaeSLiu Gang ops->open_outb_mbox = fsl_open_outb_mbox;
485abc3aeaeSLiu Gang ops->open_inb_mbox = fsl_open_inb_mbox;
486abc3aeaeSLiu Gang ops->close_outb_mbox = fsl_close_outb_mbox;
487abc3aeaeSLiu Gang ops->close_inb_mbox = fsl_close_inb_mbox;
488abc3aeaeSLiu Gang ops->add_outb_message = fsl_add_outb_message;
489abc3aeaeSLiu Gang ops->add_inb_buffer = fsl_add_inb_buffer;
490abc3aeaeSLiu Gang ops->get_inb_message = fsl_get_inb_message;
491e6a546fdSMartijn de Gouw ops->map_inb = fsl_map_inb_mem;
492e6a546fdSMartijn de Gouw ops->unmap_inb = fsl_unmap_inb_mem;
493abc3aeaeSLiu Gang
494abc3aeaeSLiu Gang rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
495a614db9aSScott Wood if (!rmu_node) {
496a614db9aSScott Wood dev_err(&dev->dev, "No valid fsl,srio-rmu-handle property\n");
497380afa36SDan Carpenter rc = -ENOENT;
498abc3aeaeSLiu Gang goto err_rmu;
499a614db9aSScott Wood }
500de8d11bcSRob Herring rmu_regs_win = of_iomap(rmu_node, 0);
501de8d11bcSRob Herring
502fcee9692SMiaoqian Lin of_node_put(rmu_node);
503abc3aeaeSLiu Gang if (!rmu_regs_win) {
504abc3aeaeSLiu Gang dev_err(&dev->dev, "Unable to map rmu register window\n");
505abc3aeaeSLiu Gang rc = -ENOMEM;
506abc3aeaeSLiu Gang goto err_rmu;
507abc3aeaeSLiu Gang }
508abc3aeaeSLiu Gang for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") {
509abc3aeaeSLiu Gang rmu_np[tmp] = np;
510abc3aeaeSLiu Gang tmp++;
511abc3aeaeSLiu Gang }
512abc3aeaeSLiu Gang
513abc3aeaeSLiu Gang /*set up doobell node*/
514abc3aeaeSLiu Gang np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
515abc3aeaeSLiu Gang if (!np) {
516a614db9aSScott Wood dev_err(&dev->dev, "No fsl,srio-dbell-unit node\n");
517abc3aeaeSLiu Gang rc = -ENODEV;
518abc3aeaeSLiu Gang goto err_dbell;
519abc3aeaeSLiu Gang }
520abc3aeaeSLiu Gang dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL);
521abc3aeaeSLiu Gang if (!(dbell)) {
522abc3aeaeSLiu Gang dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n");
523abc3aeaeSLiu Gang rc = -ENOMEM;
524abc3aeaeSLiu Gang goto err_dbell;
525abc3aeaeSLiu Gang }
526abc3aeaeSLiu Gang dbell->dev = &dev->dev;
527abc3aeaeSLiu Gang dbell->bellirq = irq_of_parse_and_map(np, 1);
528abc3aeaeSLiu Gang dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq);
529abc3aeaeSLiu Gang
530f892ac77SRob Herring if (of_property_read_reg(np, 0, &range_start, NULL)) {
531b7c670d6SRob Herring pr_err("%pOF: unable to find 'reg' property\n",
532b7c670d6SRob Herring np);
533abc3aeaeSLiu Gang rc = -ENOMEM;
534abc3aeaeSLiu Gang goto err_pw;
535abc3aeaeSLiu Gang }
536abc3aeaeSLiu Gang dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win +
537abc3aeaeSLiu Gang (u32)range_start);
538abc3aeaeSLiu Gang
539abc3aeaeSLiu Gang /*set up port write node*/
540abc3aeaeSLiu Gang np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
541abc3aeaeSLiu Gang if (!np) {
542a614db9aSScott Wood dev_err(&dev->dev, "No fsl,srio-port-write-unit node\n");
543abc3aeaeSLiu Gang rc = -ENODEV;
544abc3aeaeSLiu Gang goto err_pw;
545abc3aeaeSLiu Gang }
546abc3aeaeSLiu Gang pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL);
547abc3aeaeSLiu Gang if (!(pw)) {
548abc3aeaeSLiu Gang dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n");
549abc3aeaeSLiu Gang rc = -ENOMEM;
550abc3aeaeSLiu Gang goto err_pw;
551abc3aeaeSLiu Gang }
552abc3aeaeSLiu Gang pw->dev = &dev->dev;
553abc3aeaeSLiu Gang pw->pwirq = irq_of_parse_and_map(np, 0);
554abc3aeaeSLiu Gang dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq);
555f892ac77SRob Herring if (of_property_read_reg(np, 0, &range_start, NULL)) {
556b7c670d6SRob Herring pr_err("%pOF: unable to find 'reg' property\n",
557b7c670d6SRob Herring np);
558abc3aeaeSLiu Gang rc = -ENOMEM;
559abc3aeaeSLiu Gang goto err;
560abc3aeaeSLiu Gang }
561abc3aeaeSLiu Gang pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start);
562abc3aeaeSLiu Gang
563abc3aeaeSLiu Gang /*set up ports node*/
564abc3aeaeSLiu Gang for_each_child_of_node(dev->dev.of_node, np) {
565c4ae1799SRob Herring struct resource res;
566c4ae1799SRob Herring
567abc3aeaeSLiu Gang port_index = of_get_property(np, "cell-index", NULL);
568abc3aeaeSLiu Gang if (!port_index) {
569b7c670d6SRob Herring dev_err(&dev->dev, "Can't get %pOF property 'cell-index'\n",
570b7c670d6SRob Herring np);
571abc3aeaeSLiu Gang continue;
572abc3aeaeSLiu Gang }
573abc3aeaeSLiu Gang
574c4ae1799SRob Herring if (of_range_to_resource(np, 0, &res)) {
575b7c670d6SRob Herring dev_err(&dev->dev, "Can't get %pOF property 'ranges'\n",
576b7c670d6SRob Herring np);
577abc3aeaeSLiu Gang continue;
578abc3aeaeSLiu Gang }
579abc3aeaeSLiu Gang
580c4ae1799SRob Herring dev_info(&dev->dev, "%pOF: LAW %pR\n",
581c4ae1799SRob Herring np, &res);
582de3c8d41SKumar Gala
583ad1e9380SZhang Wei port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
584abc3aeaeSLiu Gang if (!port)
585abc3aeaeSLiu Gang continue;
586abc3aeaeSLiu Gang
587dd64f4feSAlexandre Bounine rc = rio_mport_initialize(port);
588dd64f4feSAlexandre Bounine if (rc) {
589dd64f4feSAlexandre Bounine kfree(port);
590dd64f4feSAlexandre Bounine continue;
591dd64f4feSAlexandre Bounine }
592dd64f4feSAlexandre Bounine
593abc3aeaeSLiu Gang i = *port_index - 1;
594abc3aeaeSLiu Gang port->index = (unsigned char)i;
595ad1e9380SZhang Wei
596ad1e9380SZhang Wei priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
597ad1e9380SZhang Wei if (!priv) {
598abc3aeaeSLiu Gang dev_err(&dev->dev, "Can't alloc memory for 'priv'\n");
599abc3aeaeSLiu Gang kfree(port);
600abc3aeaeSLiu Gang continue;
601ad1e9380SZhang Wei }
602ad1e9380SZhang Wei
603de3c8d41SKumar Gala INIT_LIST_HEAD(&port->dbells);
604c4ae1799SRob Herring port->iores = res; /* struct copy */
605186e74b9SLi Yang port->iores.name = "rio_io_win";
606de3c8d41SKumar Gala
607c1256ebeSAlexandre Bounine if (request_resource(&iomem_resource, &port->iores) < 0) {
608c1256ebeSAlexandre Bounine dev_err(&dev->dev, "RIO: Error requesting master port region"
609c1256ebeSAlexandre Bounine " 0x%016llx-0x%016llx\n",
610c1256ebeSAlexandre Bounine (u64)port->iores.start, (u64)port->iores.end);
611abc3aeaeSLiu Gang kfree(priv);
612abc3aeaeSLiu Gang kfree(port);
613abc3aeaeSLiu Gang continue;
614c1256ebeSAlexandre Bounine }
615abc3aeaeSLiu Gang sprintf(port->name, "RIO mport %d", i);
616de3c8d41SKumar Gala
6170dbbbf1aSAnton Vorontsov priv->dev = &dev->dev;
6182aaf308bSAlexandre Bounine port->dev.parent = &dev->dev;
619de3c8d41SKumar Gala port->ops = ops;
620ad1e9380SZhang Wei port->priv = priv;
621af84ca38SAlexandre Bounine port->phys_efptr = 0x100;
622adff1649SAlexandre Bounine port->phys_rmap = 1;
623abc3aeaeSLiu Gang priv->regs_win = rio_regs_win;
624e0423236SZhang Wei
625abc3aeaeSLiu Gang ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);
626adff1649SAlexandre Bounine
6277f620df8SZhang Wei /* Checking the port training status */
628abc3aeaeSLiu Gang if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {
629abc3aeaeSLiu Gang dev_err(&dev->dev, "Port %d is not ready. "
630abc3aeaeSLiu Gang "Try to restart connection...\n", i);
6317f620df8SZhang Wei /* Disable ports */
632abc3aeaeSLiu Gang out_be32(priv->regs_win
633abc3aeaeSLiu Gang + RIO_CCSR + i*0x20, 0);
6347f620df8SZhang Wei /* Set 1x lane */
635abc3aeaeSLiu Gang setbits32(priv->regs_win
636abc3aeaeSLiu Gang + RIO_CCSR + i*0x20, 0x02000000);
6377f620df8SZhang Wei /* Enable ports */
638abc3aeaeSLiu Gang setbits32(priv->regs_win
639abc3aeaeSLiu Gang + RIO_CCSR + i*0x20, 0x00600000);
6407f620df8SZhang Wei msleep(100);
641abc3aeaeSLiu Gang if (in_be32((priv->regs_win
642abc3aeaeSLiu Gang + RIO_ESCSR + i*0x20)) & 1) {
643abc3aeaeSLiu Gang dev_err(&dev->dev,
644abc3aeaeSLiu Gang "Port %d restart failed.\n", i);
645abc3aeaeSLiu Gang release_resource(&port->iores);
646abc3aeaeSLiu Gang kfree(priv);
647abc3aeaeSLiu Gang kfree(port);
648abc3aeaeSLiu Gang continue;
6497f620df8SZhang Wei }
650abc3aeaeSLiu Gang dev_info(&dev->dev, "Port %d restart success!\n", i);
6517f620df8SZhang Wei }
6527f620df8SZhang Wei fsl_rio_info(&dev->dev, ccsr);
65361b26917SZhang Wei
654e0423236SZhang Wei port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
655e0423236SZhang Wei & RIO_PEF_CTLS) >> 4;
656e0423236SZhang Wei dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
657e0423236SZhang Wei port->sys_size ? 65536 : 256);
658e0423236SZhang Wei
659af84ca38SAlexandre Bounine if (port->host_deviceid >= 0)
660af84ca38SAlexandre Bounine out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
661af84ca38SAlexandre Bounine RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
662af84ca38SAlexandre Bounine else
663abc3aeaeSLiu Gang out_be32(priv->regs_win + RIO_GCCSR,
664abc3aeaeSLiu Gang RIO_PORT_GEN_MASTER);
665af84ca38SAlexandre Bounine
666ad1e9380SZhang Wei priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
667abc3aeaeSLiu Gang + ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET :
668abc3aeaeSLiu Gang RIO_ATMU_REGS_PORT2_OFFSET));
669abc3aeaeSLiu Gang
670ad1e9380SZhang Wei priv->maint_atmu_regs = priv->atmu_regs + 1;
671e6a546fdSMartijn de Gouw priv->inb_atmu_regs = (struct rio_inb_atmu_regs __iomem *)
672e6a546fdSMartijn de Gouw (priv->regs_win +
673e6a546fdSMartijn de Gouw ((i == 0) ? RIO_INB_ATMU_REGS_PORT1_OFFSET :
674e6a546fdSMartijn de Gouw RIO_INB_ATMU_REGS_PORT2_OFFSET));
675e6a546fdSMartijn de Gouw
676adff1649SAlexandre Bounine /* Set to receive packets with any dest ID */
677adff1649SAlexandre Bounine out_be32((priv->regs_win + RIO_ISR_AACR + i*0x80),
678adff1649SAlexandre Bounine RIO_ISR_AACR_AA);
679de3c8d41SKumar Gala
680de3c8d41SKumar Gala /* Configure maintenance transaction window */
681abc3aeaeSLiu Gang out_be32(&priv->maint_atmu_regs->rowbar,
682abc3aeaeSLiu Gang port->iores.start >> 12);
683bd4fb654SThomas Moll out_be32(&priv->maint_atmu_regs->rowar,
684bd4fb654SThomas Moll 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
685de3c8d41SKumar Gala
686abc3aeaeSLiu Gang priv->maint_win = ioremap(port->iores.start,
687abc3aeaeSLiu Gang RIO_MAINT_WIN_SIZE);
688de3c8d41SKumar Gala
689abc3aeaeSLiu Gang rio_law_start = range_start;
6906ec4bedbSLiu Gang
691abc3aeaeSLiu Gang fsl_rio_setup_rmu(port, rmu_np[i]);
692e6a546fdSMartijn de Gouw fsl_rio_inbound_mem_init(priv);
693abc3aeaeSLiu Gang
694abc3aeaeSLiu Gang dbell->mport[i] = port;
6959a0b0627SAlexandre Bounine pw->mport[i] = port;
696abc3aeaeSLiu Gang
697dd64f4feSAlexandre Bounine if (rio_register_mport(port)) {
698dd64f4feSAlexandre Bounine release_resource(&port->iores);
699dd64f4feSAlexandre Bounine kfree(priv);
700dd64f4feSAlexandre Bounine kfree(port);
701dd64f4feSAlexandre Bounine continue;
702dd64f4feSAlexandre Bounine }
703abc3aeaeSLiu Gang active_ports++;
704abc3aeaeSLiu Gang }
705abc3aeaeSLiu Gang
706abc3aeaeSLiu Gang if (!active_ports) {
707abc3aeaeSLiu Gang rc = -ENOLINK;
708abc3aeaeSLiu Gang goto err;
709abc3aeaeSLiu Gang }
710abc3aeaeSLiu Gang
711abc3aeaeSLiu Gang fsl_rio_doorbell_init(dbell);
712abc3aeaeSLiu Gang fsl_rio_port_write_init(pw);
713ad1e9380SZhang Wei
714cc2bb696SZhang Wei return 0;
715ad1e9380SZhang Wei err:
716abc3aeaeSLiu Gang kfree(pw);
717a614db9aSScott Wood pw = NULL;
718abc3aeaeSLiu Gang err_pw:
719abc3aeaeSLiu Gang kfree(dbell);
720a614db9aSScott Wood dbell = NULL;
721abc3aeaeSLiu Gang err_dbell:
722abc3aeaeSLiu Gang iounmap(rmu_regs_win);
723a614db9aSScott Wood rmu_regs_win = NULL;
724abc3aeaeSLiu Gang err_rmu:
7256c75933cSJulia Lawall kfree(ops);
7266c75933cSJulia Lawall err_ops:
727abc3aeaeSLiu Gang iounmap(rio_regs_win);
728a614db9aSScott Wood rio_regs_win = NULL;
729abc3aeaeSLiu Gang err_rio_regs:
730cc2bb696SZhang Wei return rc;
731de3c8d41SKumar Gala }
732cc2bb696SZhang Wei
733cc2bb696SZhang Wei /* The probe function for RapidIO peer-to-peer network.
734cc2bb696SZhang Wei */
fsl_of_rio_rpn_probe(struct platform_device * dev)735cad5cef6SGreg Kroah-Hartman static int fsl_of_rio_rpn_probe(struct platform_device *dev)
736cc2bb696SZhang Wei {
737b7c670d6SRob Herring printk(KERN_INFO "Setting up RapidIO peer-to-peer network %pOF\n",
738b7c670d6SRob Herring dev->dev.of_node);
739cc2bb696SZhang Wei
7402f809985SAlexandre Bounine return fsl_rio_setup(dev);
741cc2bb696SZhang Wei };
742cc2bb696SZhang Wei
743cc2bb696SZhang Wei static const struct of_device_id fsl_of_rio_rpn_ids[] = {
744cc2bb696SZhang Wei {
745abc3aeaeSLiu Gang .compatible = "fsl,srio",
746cc2bb696SZhang Wei },
747cc2bb696SZhang Wei {},
748cc2bb696SZhang Wei };
749cc2bb696SZhang Wei
75000006124SGrant Likely static struct platform_driver fsl_of_rio_rpn_driver = {
7514018294bSGrant Likely .driver = {
752cc2bb696SZhang Wei .name = "fsl-of-rio",
7534018294bSGrant Likely .of_match_table = fsl_of_rio_rpn_ids,
7544018294bSGrant Likely },
755cc2bb696SZhang Wei .probe = fsl_of_rio_rpn_probe,
756cc2bb696SZhang Wei };
757cc2bb696SZhang Wei
fsl_of_rio_rpn_init(void)758cc2bb696SZhang Wei static __init int fsl_of_rio_rpn_init(void)
759cc2bb696SZhang Wei {
76000006124SGrant Likely return platform_driver_register(&fsl_of_rio_rpn_driver);
761cc2bb696SZhang Wei }
762cc2bb696SZhang Wei
763cc2bb696SZhang Wei subsys_initcall(fsl_of_rio_rpn_init);
764