1 /* 2 * MPC83xx/85xx/86xx PCI/PCIE support routing. 3 * 4 * Copyright 2007-2009 Freescale Semiconductor, Inc. 5 * Copyright 2008-2009 MontaVista Software, Inc. 6 * 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 8 * Recode: ZHANG WEI <wei.zhang@freescale.com> 9 * Rewrite the routing for Frescale PCI and PCI Express 10 * Roy Zang <tie-fei.zang@freescale.com> 11 * MPC83xx PCI-Express support: 12 * Tony Li <tony.li@freescale.com> 13 * Anton Vorontsov <avorontsov@ru.mvista.com> 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 */ 20 #include <linux/kernel.h> 21 #include <linux/pci.h> 22 #include <linux/delay.h> 23 #include <linux/string.h> 24 #include <linux/init.h> 25 #include <linux/bootmem.h> 26 #include <linux/lmb.h> 27 #include <linux/log2.h> 28 29 #include <asm/io.h> 30 #include <asm/prom.h> 31 #include <asm/pci-bridge.h> 32 #include <asm/machdep.h> 33 #include <sysdev/fsl_soc.h> 34 #include <sysdev/fsl_pci.h> 35 36 static int fsl_pcie_bus_fixup; 37 38 static void __init quirk_fsl_pcie_header(struct pci_dev *dev) 39 { 40 /* if we aren't a PCIe don't bother */ 41 if (!pci_find_capability(dev, PCI_CAP_ID_EXP)) 42 return; 43 44 dev->class = PCI_CLASS_BRIDGE_PCI << 8; 45 fsl_pcie_bus_fixup = 1; 46 return; 47 } 48 49 static int __init fsl_pcie_check_link(struct pci_controller *hose) 50 { 51 u32 val; 52 53 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); 54 if (val < PCIE_LTSSM_L0) 55 return 1; 56 return 0; 57 } 58 59 #if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx) 60 static int __init setup_one_atmu(struct ccsr_pci __iomem *pci, 61 unsigned int index, const struct resource *res, 62 resource_size_t offset) 63 { 64 resource_size_t pci_addr = res->start - offset; 65 resource_size_t phys_addr = res->start; 66 resource_size_t size = res->end - res->start + 1; 67 u32 flags = 0x80044000; /* enable & mem R/W */ 68 unsigned int i; 69 70 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", 71 (u64)res->start, (u64)size); 72 73 if (res->flags & IORESOURCE_PREFETCH) 74 flags |= 0x10000000; /* enable relaxed ordering */ 75 76 for (i = 0; size > 0; i++) { 77 unsigned int bits = min(__ilog2(size), 78 __ffs(pci_addr | phys_addr)); 79 80 if (index + i >= 5) 81 return -1; 82 83 out_be32(&pci->pow[index + i].potar, pci_addr >> 12); 84 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); 85 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); 86 out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); 87 88 pci_addr += (resource_size_t)1U << bits; 89 phys_addr += (resource_size_t)1U << bits; 90 size -= (resource_size_t)1U << bits; 91 } 92 93 return i; 94 } 95 96 /* atmu setup for fsl pci/pcie controller */ 97 static void __init setup_pci_atmu(struct pci_controller *hose, 98 struct resource *rsrc) 99 { 100 struct ccsr_pci __iomem *pci; 101 int i, j, n, mem_log, win_idx = 2; 102 u64 mem, sz, paddr_hi = 0; 103 u64 paddr_lo = ULLONG_MAX; 104 u32 pcicsrbar = 0, pcicsrbar_sz; 105 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | 106 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 107 char *name = hose->dn->full_name; 108 109 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", 110 (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1); 111 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); 112 if (!pci) { 113 dev_err(hose->parent, "Unable to map ATMU registers\n"); 114 return; 115 } 116 117 /* Disable all windows (except powar0 since it's ignored) */ 118 for(i = 1; i < 5; i++) 119 out_be32(&pci->pow[i].powar, 0); 120 for(i = 0; i < 3; i++) 121 out_be32(&pci->piw[i].piwar, 0); 122 123 /* Setup outbound MEM window */ 124 for(i = 0, j = 1; i < 3; i++) { 125 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) 126 continue; 127 128 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); 129 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); 130 131 n = setup_one_atmu(pci, j, &hose->mem_resources[i], 132 hose->pci_mem_offset); 133 134 if (n < 0 || j >= 5) { 135 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i); 136 hose->mem_resources[i].flags |= IORESOURCE_DISABLED; 137 } else 138 j += n; 139 } 140 141 /* Setup outbound IO window */ 142 if (hose->io_resource.flags & IORESOURCE_IO) { 143 if (j >= 5) { 144 pr_err("Ran out of outbound PCI ATMUs for IO resource\n"); 145 } else { 146 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " 147 "phy base 0x%016llx.\n", 148 (u64)hose->io_resource.start, 149 (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1, 150 (u64)hose->io_base_phys); 151 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); 152 out_be32(&pci->pow[j].potear, 0); 153 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); 154 /* Enable, IO R/W */ 155 out_be32(&pci->pow[j].powar, 0x80088000 156 | (__ilog2(hose->io_resource.end 157 - hose->io_resource.start + 1) - 1)); 158 } 159 } 160 161 /* convert to pci address space */ 162 paddr_hi -= hose->pci_mem_offset; 163 paddr_lo -= hose->pci_mem_offset; 164 165 if (paddr_hi == paddr_lo) { 166 pr_err("%s: No outbound window space\n", name); 167 return ; 168 } 169 170 if (paddr_lo == 0) { 171 pr_err("%s: No space for inbound window\n", name); 172 return ; 173 } 174 175 /* setup PCSRBAR/PEXCSRBAR */ 176 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff); 177 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 178 pcicsrbar_sz = ~pcicsrbar_sz + 1; 179 180 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || 181 (paddr_lo > 0x100000000ull)) 182 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 183 else 184 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; 185 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar); 186 187 paddr_lo = min(paddr_lo, (u64)pcicsrbar); 188 189 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar); 190 191 /* Setup inbound mem window */ 192 mem = lmb_end_of_DRAM(); 193 sz = min(mem, paddr_lo); 194 mem_log = __ilog2_u64(sz); 195 196 /* PCIe can overmap inbound & outbound since RX & TX are separated */ 197 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 198 /* Size window to exact size if power-of-two or one size up */ 199 if ((1ull << mem_log) != mem) { 200 if ((1ull << mem_log) > mem) 201 pr_info("%s: Setting PCI inbound window " 202 "greater than memory size\n", name); 203 mem_log++; 204 } 205 206 piwar |= (mem_log - 1); 207 208 /* Setup inbound memory window */ 209 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 210 out_be32(&pci->piw[win_idx].piwbar, 0x00000000); 211 out_be32(&pci->piw[win_idx].piwar, piwar); 212 win_idx--; 213 214 hose->dma_window_base_cur = 0x00000000; 215 hose->dma_window_size = (resource_size_t)sz; 216 } else { 217 u64 paddr = 0; 218 219 /* Setup inbound memory window */ 220 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 221 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); 222 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1))); 223 win_idx--; 224 225 paddr += 1ull << mem_log; 226 sz -= 1ull << mem_log; 227 228 if (sz) { 229 mem_log = __ilog2_u64(sz); 230 piwar |= (mem_log - 1); 231 232 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 233 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); 234 out_be32(&pci->piw[win_idx].piwar, piwar); 235 win_idx--; 236 237 paddr += 1ull << mem_log; 238 } 239 240 hose->dma_window_base_cur = 0x00000000; 241 hose->dma_window_size = (resource_size_t)paddr; 242 } 243 244 if (hose->dma_window_size < mem) { 245 #ifndef CONFIG_SWIOTLB 246 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to " 247 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", 248 name); 249 #endif 250 /* adjusting outbound windows could reclaim space in mem map */ 251 if (paddr_hi < 0xffffffffull) 252 pr_warning("%s: WARNING: Outbound window cfg leaves " 253 "gaps in memory map. Adjusting the memory map " 254 "could reduce unnecessary bounce buffering.\n", 255 name); 256 257 pr_info("%s: DMA window size is 0x%llx\n", name, 258 (u64)hose->dma_window_size); 259 } 260 261 iounmap(pci); 262 } 263 264 static void __init setup_pci_cmd(struct pci_controller *hose) 265 { 266 u16 cmd; 267 int cap_x; 268 269 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); 270 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY 271 | PCI_COMMAND_IO; 272 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); 273 274 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); 275 if (cap_x) { 276 int pci_x_cmd = cap_x + PCI_X_CMD; 277 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 278 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 279 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); 280 } else { 281 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); 282 } 283 } 284 285 void fsl_pcibios_fixup_bus(struct pci_bus *bus) 286 { 287 struct pci_controller *hose = pci_bus_to_host(bus); 288 int i; 289 290 if ((bus->parent == hose->bus) && 291 ((fsl_pcie_bus_fixup && 292 early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) || 293 (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK))) 294 { 295 for (i = 0; i < 4; ++i) { 296 struct resource *res = bus->resource[i]; 297 struct resource *par = bus->parent->resource[i]; 298 if (res) { 299 res->start = 0; 300 res->end = 0; 301 res->flags = 0; 302 } 303 if (res && par) { 304 res->start = par->start; 305 res->end = par->end; 306 res->flags = par->flags; 307 } 308 } 309 } 310 } 311 312 int __init fsl_add_bridge(struct device_node *dev, int is_primary) 313 { 314 int len; 315 struct pci_controller *hose; 316 struct resource rsrc; 317 const int *bus_range; 318 319 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 320 321 /* Fetch host bridge registers address */ 322 if (of_address_to_resource(dev, 0, &rsrc)) { 323 printk(KERN_WARNING "Can't get pci register base!"); 324 return -ENOMEM; 325 } 326 327 /* Get bus range if any */ 328 bus_range = of_get_property(dev, "bus-range", &len); 329 if (bus_range == NULL || len < 2 * sizeof(int)) 330 printk(KERN_WARNING "Can't get bus-range for %s, assume" 331 " bus 0\n", dev->full_name); 332 333 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 334 hose = pcibios_alloc_controller(dev); 335 if (!hose) 336 return -ENOMEM; 337 338 hose->first_busno = bus_range ? bus_range[0] : 0x0; 339 hose->last_busno = bus_range ? bus_range[1] : 0xff; 340 341 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, 342 PPC_INDIRECT_TYPE_BIG_ENDIAN); 343 setup_pci_cmd(hose); 344 345 /* check PCI express link status */ 346 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 347 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | 348 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; 349 if (fsl_pcie_check_link(hose)) 350 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 351 } 352 353 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 354 "Firmware bus number: %d->%d\n", 355 (unsigned long long)rsrc.start, hose->first_busno, 356 hose->last_busno); 357 358 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 359 hose, hose->cfg_addr, hose->cfg_data); 360 361 /* Interpret the "ranges" property */ 362 /* This also maps the I/O region and sets isa_io/mem_base */ 363 pci_process_bridge_OF_ranges(hose, dev, is_primary); 364 365 /* Setup PEX window registers */ 366 setup_pci_atmu(hose, &rsrc); 367 368 return 0; 369 } 370 371 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header); 372 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header); 373 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header); 374 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header); 375 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header); 376 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header); 377 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header); 378 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569E, quirk_fsl_pcie_header); 379 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569, quirk_fsl_pcie_header); 380 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header); 381 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header); 382 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header); 383 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header); 384 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header); 385 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header); 386 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header); 387 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header); 388 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header); 389 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header); 390 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header); 391 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header); 392 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header); 393 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header); 394 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header); 395 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header); 396 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header); 397 #endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */ 398 399 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) 400 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header); 401 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header); 402 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header); 403 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315, quirk_fsl_pcie_header); 404 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377E, quirk_fsl_pcie_header); 405 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377, quirk_fsl_pcie_header); 406 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378E, quirk_fsl_pcie_header); 407 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378, quirk_fsl_pcie_header); 408 409 struct mpc83xx_pcie_priv { 410 void __iomem *cfg_type0; 411 void __iomem *cfg_type1; 412 u32 dev_base; 413 }; 414 415 /* 416 * With the convention of u-boot, the PCIE outbound window 0 serves 417 * as configuration transactions outbound. 418 */ 419 #define PEX_OUTWIN0_BAR 0xCA4 420 #define PEX_OUTWIN0_TAL 0xCA8 421 #define PEX_OUTWIN0_TAH 0xCAC 422 423 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) 424 { 425 struct pci_controller *hose = pci_bus_to_host(bus); 426 427 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) 428 return PCIBIOS_DEVICE_NOT_FOUND; 429 /* 430 * Workaround for the HW bug: for Type 0 configure transactions the 431 * PCI-E controller does not check the device number bits and just 432 * assumes that the device number bits are 0. 433 */ 434 if (bus->number == hose->first_busno || 435 bus->primary == hose->first_busno) { 436 if (devfn & 0xf8) 437 return PCIBIOS_DEVICE_NOT_FOUND; 438 } 439 440 if (ppc_md.pci_exclude_device) { 441 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 442 return PCIBIOS_DEVICE_NOT_FOUND; 443 } 444 445 return PCIBIOS_SUCCESSFUL; 446 } 447 448 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, 449 unsigned int devfn, int offset) 450 { 451 struct pci_controller *hose = pci_bus_to_host(bus); 452 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 453 u8 bus_no = bus->number - hose->first_busno; 454 u32 dev_base = bus_no << 24 | devfn << 16; 455 int ret; 456 457 ret = mpc83xx_pcie_exclude_device(bus, devfn); 458 if (ret) 459 return NULL; 460 461 offset &= 0xfff; 462 463 /* Type 0 */ 464 if (bus->number == hose->first_busno) 465 return pcie->cfg_type0 + offset; 466 467 if (pcie->dev_base == dev_base) 468 goto mapped; 469 470 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); 471 472 pcie->dev_base = dev_base; 473 mapped: 474 return pcie->cfg_type1 + offset; 475 } 476 477 static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn, 478 int offset, int len, u32 *val) 479 { 480 void __iomem *cfg_addr; 481 482 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); 483 if (!cfg_addr) 484 return PCIBIOS_DEVICE_NOT_FOUND; 485 486 switch (len) { 487 case 1: 488 *val = in_8(cfg_addr); 489 break; 490 case 2: 491 *val = in_le16(cfg_addr); 492 break; 493 default: 494 *val = in_le32(cfg_addr); 495 break; 496 } 497 498 return PCIBIOS_SUCCESSFUL; 499 } 500 501 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 502 int offset, int len, u32 val) 503 { 504 void __iomem *cfg_addr; 505 506 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); 507 if (!cfg_addr) 508 return PCIBIOS_DEVICE_NOT_FOUND; 509 510 switch (len) { 511 case 1: 512 out_8(cfg_addr, val); 513 break; 514 case 2: 515 out_le16(cfg_addr, val); 516 break; 517 default: 518 out_le32(cfg_addr, val); 519 break; 520 } 521 522 return PCIBIOS_SUCCESSFUL; 523 } 524 525 static struct pci_ops mpc83xx_pcie_ops = { 526 .read = mpc83xx_pcie_read_config, 527 .write = mpc83xx_pcie_write_config, 528 }; 529 530 static int __init mpc83xx_pcie_setup(struct pci_controller *hose, 531 struct resource *reg) 532 { 533 struct mpc83xx_pcie_priv *pcie; 534 u32 cfg_bar; 535 int ret = -ENOMEM; 536 537 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); 538 if (!pcie) 539 return ret; 540 541 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); 542 if (!pcie->cfg_type0) 543 goto err0; 544 545 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); 546 if (!cfg_bar) { 547 /* PCI-E isn't configured. */ 548 ret = -ENODEV; 549 goto err1; 550 } 551 552 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); 553 if (!pcie->cfg_type1) 554 goto err1; 555 556 WARN_ON(hose->dn->data); 557 hose->dn->data = pcie; 558 hose->ops = &mpc83xx_pcie_ops; 559 560 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); 561 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); 562 563 if (fsl_pcie_check_link(hose)) 564 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 565 566 return 0; 567 err1: 568 iounmap(pcie->cfg_type0); 569 err0: 570 kfree(pcie); 571 return ret; 572 573 } 574 575 int __init mpc83xx_add_bridge(struct device_node *dev) 576 { 577 int ret; 578 int len; 579 struct pci_controller *hose; 580 struct resource rsrc_reg; 581 struct resource rsrc_cfg; 582 const int *bus_range; 583 int primary; 584 585 if (!of_device_is_available(dev)) { 586 pr_warning("%s: disabled by the firmware.\n", 587 dev->full_name); 588 return -ENODEV; 589 } 590 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 591 592 /* Fetch host bridge registers address */ 593 if (of_address_to_resource(dev, 0, &rsrc_reg)) { 594 printk(KERN_WARNING "Can't get pci register base!\n"); 595 return -ENOMEM; 596 } 597 598 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg)); 599 600 if (of_address_to_resource(dev, 1, &rsrc_cfg)) { 601 printk(KERN_WARNING 602 "No pci config register base in dev tree, " 603 "using default\n"); 604 /* 605 * MPC83xx supports up to two host controllers 606 * one at 0x8500 has config space registers at 0x8300 607 * one at 0x8600 has config space registers at 0x8380 608 */ 609 if ((rsrc_reg.start & 0xfffff) == 0x8500) 610 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300; 611 else if ((rsrc_reg.start & 0xfffff) == 0x8600) 612 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380; 613 } 614 /* 615 * Controller at offset 0x8500 is primary 616 */ 617 if ((rsrc_reg.start & 0xfffff) == 0x8500) 618 primary = 1; 619 else 620 primary = 0; 621 622 /* Get bus range if any */ 623 bus_range = of_get_property(dev, "bus-range", &len); 624 if (bus_range == NULL || len < 2 * sizeof(int)) { 625 printk(KERN_WARNING "Can't get bus-range for %s, assume" 626 " bus 0\n", dev->full_name); 627 } 628 629 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 630 hose = pcibios_alloc_controller(dev); 631 if (!hose) 632 return -ENOMEM; 633 634 hose->first_busno = bus_range ? bus_range[0] : 0; 635 hose->last_busno = bus_range ? bus_range[1] : 0xff; 636 637 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { 638 ret = mpc83xx_pcie_setup(hose, &rsrc_reg); 639 if (ret) 640 goto err0; 641 } else { 642 setup_indirect_pci(hose, rsrc_cfg.start, 643 rsrc_cfg.start + 4, 0); 644 } 645 646 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 647 "Firmware bus number: %d->%d\n", 648 (unsigned long long)rsrc_reg.start, hose->first_busno, 649 hose->last_busno); 650 651 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 652 hose, hose->cfg_addr, hose->cfg_data); 653 654 /* Interpret the "ranges" property */ 655 /* This also maps the I/O region and sets isa_io/mem_base */ 656 pci_process_bridge_OF_ranges(hose, dev, primary); 657 658 return 0; 659 err0: 660 pcibios_free_controller(hose); 661 return ret; 662 } 663 #endif /* CONFIG_PPC_83xx */ 664