1 /* 2 * MPC83xx/85xx/86xx PCI/PCIE support routing. 3 * 4 * Copyright 2007-2012 Freescale Semiconductor, Inc. 5 * Copyright 2008-2009 MontaVista Software, Inc. 6 * 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 8 * Recode: ZHANG WEI <wei.zhang@freescale.com> 9 * Rewrite the routing for Frescale PCI and PCI Express 10 * Roy Zang <tie-fei.zang@freescale.com> 11 * MPC83xx PCI-Express support: 12 * Tony Li <tony.li@freescale.com> 13 * Anton Vorontsov <avorontsov@ru.mvista.com> 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 */ 20 #include <linux/kernel.h> 21 #include <linux/pci.h> 22 #include <linux/delay.h> 23 #include <linux/string.h> 24 #include <linux/init.h> 25 #include <linux/bootmem.h> 26 #include <linux/memblock.h> 27 #include <linux/log2.h> 28 #include <linux/slab.h> 29 30 #include <asm/io.h> 31 #include <asm/prom.h> 32 #include <asm/pci-bridge.h> 33 #include <asm/machdep.h> 34 #include <sysdev/fsl_soc.h> 35 #include <sysdev/fsl_pci.h> 36 37 static int fsl_pcie_bus_fixup, is_mpc83xx_pci; 38 39 static void quirk_fsl_pcie_header(struct pci_dev *dev) 40 { 41 u8 hdr_type; 42 43 /* if we aren't a PCIe don't bother */ 44 if (!pci_find_capability(dev, PCI_CAP_ID_EXP)) 45 return; 46 47 /* if we aren't in host mode don't bother */ 48 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 49 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) 50 return; 51 52 dev->class = PCI_CLASS_BRIDGE_PCI << 8; 53 fsl_pcie_bus_fixup = 1; 54 return; 55 } 56 57 static int fsl_indirect_read_config(struct pci_bus *, unsigned int, 58 int, int, u32 *); 59 60 static int fsl_pcie_check_link(struct pci_controller *hose) 61 { 62 u32 val = 0; 63 64 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { 65 if (hose->ops->read == fsl_indirect_read_config) { 66 struct pci_bus bus; 67 bus.number = 0; 68 bus.sysdata = hose; 69 bus.ops = hose->ops; 70 indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val); 71 } else 72 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); 73 if (val < PCIE_LTSSM_L0) 74 return 1; 75 } else { 76 struct ccsr_pci __iomem *pci = hose->private_data; 77 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */ 78 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) 79 >> PEX_CSR0_LTSSM_SHIFT; 80 if (val != PEX_CSR0_LTSSM_L0) 81 return 1; 82 } 83 84 return 0; 85 } 86 87 static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn, 88 int offset, int len, u32 *val) 89 { 90 struct pci_controller *hose = pci_bus_to_host(bus); 91 92 if (fsl_pcie_check_link(hose)) 93 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 94 else 95 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; 96 97 return indirect_read_config(bus, devfn, offset, len, val); 98 } 99 100 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 101 102 static struct pci_ops fsl_indirect_pcie_ops = 103 { 104 .read = fsl_indirect_read_config, 105 .write = indirect_write_config, 106 }; 107 108 #define MAX_PHYS_ADDR_BITS 40 109 static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS; 110 111 static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask) 112 { 113 if (!dev->dma_mask || !dma_supported(dev, dma_mask)) 114 return -EIO; 115 116 /* 117 * Fixup PCI devices that are able to DMA to above the physical 118 * address width of the SoC such that we can address any internal 119 * SoC address from across PCI if needed 120 */ 121 if ((dev->bus == &pci_bus_type) && 122 dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) { 123 set_dma_ops(dev, &dma_direct_ops); 124 set_dma_offset(dev, pci64_dma_offset); 125 } 126 127 *dev->dma_mask = dma_mask; 128 return 0; 129 } 130 131 static int setup_one_atmu(struct ccsr_pci __iomem *pci, 132 unsigned int index, const struct resource *res, 133 resource_size_t offset) 134 { 135 resource_size_t pci_addr = res->start - offset; 136 resource_size_t phys_addr = res->start; 137 resource_size_t size = resource_size(res); 138 u32 flags = 0x80044000; /* enable & mem R/W */ 139 unsigned int i; 140 141 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", 142 (u64)res->start, (u64)size); 143 144 if (res->flags & IORESOURCE_PREFETCH) 145 flags |= 0x10000000; /* enable relaxed ordering */ 146 147 for (i = 0; size > 0; i++) { 148 unsigned int bits = min(ilog2(size), 149 __ffs(pci_addr | phys_addr)); 150 151 if (index + i >= 5) 152 return -1; 153 154 out_be32(&pci->pow[index + i].potar, pci_addr >> 12); 155 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); 156 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); 157 out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); 158 159 pci_addr += (resource_size_t)1U << bits; 160 phys_addr += (resource_size_t)1U << bits; 161 size -= (resource_size_t)1U << bits; 162 } 163 164 return i; 165 } 166 167 /* atmu setup for fsl pci/pcie controller */ 168 static void setup_pci_atmu(struct pci_controller *hose) 169 { 170 struct ccsr_pci __iomem *pci = hose->private_data; 171 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4; 172 u64 mem, sz, paddr_hi = 0; 173 u64 offset = 0, paddr_lo = ULLONG_MAX; 174 u32 pcicsrbar = 0, pcicsrbar_sz; 175 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | 176 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 177 const char *name = hose->dn->full_name; 178 const u64 *reg; 179 int len; 180 181 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 182 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) { 183 win_idx = 2; 184 start_idx = 0; 185 end_idx = 3; 186 } 187 } 188 189 /* Disable all windows (except powar0 since it's ignored) */ 190 for(i = 1; i < 5; i++) 191 out_be32(&pci->pow[i].powar, 0); 192 for (i = start_idx; i < end_idx; i++) 193 out_be32(&pci->piw[i].piwar, 0); 194 195 /* Setup outbound MEM window */ 196 for(i = 0, j = 1; i < 3; i++) { 197 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) 198 continue; 199 200 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); 201 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); 202 203 /* We assume all memory resources have the same offset */ 204 offset = hose->mem_offset[i]; 205 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset); 206 207 if (n < 0 || j >= 5) { 208 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i); 209 hose->mem_resources[i].flags |= IORESOURCE_DISABLED; 210 } else 211 j += n; 212 } 213 214 /* Setup outbound IO window */ 215 if (hose->io_resource.flags & IORESOURCE_IO) { 216 if (j >= 5) { 217 pr_err("Ran out of outbound PCI ATMUs for IO resource\n"); 218 } else { 219 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " 220 "phy base 0x%016llx.\n", 221 (u64)hose->io_resource.start, 222 (u64)resource_size(&hose->io_resource), 223 (u64)hose->io_base_phys); 224 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); 225 out_be32(&pci->pow[j].potear, 0); 226 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); 227 /* Enable, IO R/W */ 228 out_be32(&pci->pow[j].powar, 0x80088000 229 | (ilog2(hose->io_resource.end 230 - hose->io_resource.start + 1) - 1)); 231 } 232 } 233 234 /* convert to pci address space */ 235 paddr_hi -= offset; 236 paddr_lo -= offset; 237 238 if (paddr_hi == paddr_lo) { 239 pr_err("%s: No outbound window space\n", name); 240 return; 241 } 242 243 if (paddr_lo == 0) { 244 pr_err("%s: No space for inbound window\n", name); 245 return; 246 } 247 248 /* setup PCSRBAR/PEXCSRBAR */ 249 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff); 250 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 251 pcicsrbar_sz = ~pcicsrbar_sz + 1; 252 253 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || 254 (paddr_lo > 0x100000000ull)) 255 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 256 else 257 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; 258 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar); 259 260 paddr_lo = min(paddr_lo, (u64)pcicsrbar); 261 262 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar); 263 264 /* Setup inbound mem window */ 265 mem = memblock_end_of_DRAM(); 266 267 /* 268 * The msi-address-64 property, if it exists, indicates the physical 269 * address of the MSIIR register. Normally, this register is located 270 * inside CCSR, so the ATMU that covers all of CCSR is used. But if 271 * this property exists, then we normally need to create a new ATMU 272 * for it. For now, however, we cheat. The only entity that creates 273 * this property is the Freescale hypervisor, and the address is 274 * specified in the partition configuration. Typically, the address 275 * is located in the page immediately after the end of DDR. If so, we 276 * can avoid allocating a new ATMU by extending the DDR ATMU by one 277 * page. 278 */ 279 reg = of_get_property(hose->dn, "msi-address-64", &len); 280 if (reg && (len == sizeof(u64))) { 281 u64 address = be64_to_cpup(reg); 282 283 if ((address >= mem) && (address < (mem + PAGE_SIZE))) { 284 pr_info("%s: extending DDR ATMU to cover MSIIR", name); 285 mem += PAGE_SIZE; 286 } else { 287 /* TODO: Create a new ATMU for MSIIR */ 288 pr_warn("%s: msi-address-64 address of %llx is " 289 "unsupported\n", name, address); 290 } 291 } 292 293 sz = min(mem, paddr_lo); 294 mem_log = ilog2(sz); 295 296 /* PCIe can overmap inbound & outbound since RX & TX are separated */ 297 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 298 /* Size window to exact size if power-of-two or one size up */ 299 if ((1ull << mem_log) != mem) { 300 if ((1ull << mem_log) > mem) 301 pr_info("%s: Setting PCI inbound window " 302 "greater than memory size\n", name); 303 mem_log++; 304 } 305 306 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK); 307 308 /* Setup inbound memory window */ 309 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 310 out_be32(&pci->piw[win_idx].piwbar, 0x00000000); 311 out_be32(&pci->piw[win_idx].piwar, piwar); 312 win_idx--; 313 314 hose->dma_window_base_cur = 0x00000000; 315 hose->dma_window_size = (resource_size_t)sz; 316 317 /* 318 * if we have >4G of memory setup second PCI inbound window to 319 * let devices that are 64-bit address capable to work w/o 320 * SWIOTLB and access the full range of memory 321 */ 322 if (sz != mem) { 323 mem_log = ilog2(mem); 324 325 /* Size window up if we dont fit in exact power-of-2 */ 326 if ((1ull << mem_log) != mem) 327 mem_log++; 328 329 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1); 330 331 /* Setup inbound memory window */ 332 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 333 out_be32(&pci->piw[win_idx].piwbear, 334 pci64_dma_offset >> 44); 335 out_be32(&pci->piw[win_idx].piwbar, 336 pci64_dma_offset >> 12); 337 out_be32(&pci->piw[win_idx].piwar, piwar); 338 339 /* 340 * install our own dma_set_mask handler to fixup dma_ops 341 * and dma_offset 342 */ 343 ppc_md.dma_set_mask = fsl_pci_dma_set_mask; 344 345 pr_info("%s: Setup 64-bit PCI DMA window\n", name); 346 } 347 } else { 348 u64 paddr = 0; 349 350 /* Setup inbound memory window */ 351 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 352 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); 353 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1))); 354 win_idx--; 355 356 paddr += 1ull << mem_log; 357 sz -= 1ull << mem_log; 358 359 if (sz) { 360 mem_log = ilog2(sz); 361 piwar |= (mem_log - 1); 362 363 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 364 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); 365 out_be32(&pci->piw[win_idx].piwar, piwar); 366 win_idx--; 367 368 paddr += 1ull << mem_log; 369 } 370 371 hose->dma_window_base_cur = 0x00000000; 372 hose->dma_window_size = (resource_size_t)paddr; 373 } 374 375 if (hose->dma_window_size < mem) { 376 #ifndef CONFIG_SWIOTLB 377 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to " 378 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", 379 name); 380 #endif 381 /* adjusting outbound windows could reclaim space in mem map */ 382 if (paddr_hi < 0xffffffffull) 383 pr_warning("%s: WARNING: Outbound window cfg leaves " 384 "gaps in memory map. Adjusting the memory map " 385 "could reduce unnecessary bounce buffering.\n", 386 name); 387 388 pr_info("%s: DMA window size is 0x%llx\n", name, 389 (u64)hose->dma_window_size); 390 } 391 } 392 393 static void __init setup_pci_cmd(struct pci_controller *hose) 394 { 395 u16 cmd; 396 int cap_x; 397 398 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); 399 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY 400 | PCI_COMMAND_IO; 401 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); 402 403 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); 404 if (cap_x) { 405 int pci_x_cmd = cap_x + PCI_X_CMD; 406 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 407 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 408 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); 409 } else { 410 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); 411 } 412 } 413 414 void fsl_pcibios_fixup_bus(struct pci_bus *bus) 415 { 416 struct pci_controller *hose = pci_bus_to_host(bus); 417 int i, is_pcie = 0, no_link; 418 419 /* The root complex bridge comes up with bogus resources, 420 * we copy the PHB ones in. 421 * 422 * With the current generic PCI code, the PHB bus no longer 423 * has bus->resource[0..4] set, so things are a bit more 424 * tricky. 425 */ 426 427 if (fsl_pcie_bus_fixup) 428 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP); 429 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK); 430 431 if (bus->parent == hose->bus && (is_pcie || no_link)) { 432 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) { 433 struct resource *res = bus->resource[i]; 434 struct resource *par; 435 436 if (!res) 437 continue; 438 if (i == 0) 439 par = &hose->io_resource; 440 else if (i < 4) 441 par = &hose->mem_resources[i-1]; 442 else par = NULL; 443 444 res->start = par ? par->start : 0; 445 res->end = par ? par->end : 0; 446 res->flags = par ? par->flags : 0; 447 } 448 } 449 } 450 451 int __init fsl_add_bridge(struct platform_device *pdev, int is_primary) 452 { 453 int len; 454 struct pci_controller *hose; 455 struct resource rsrc; 456 const int *bus_range; 457 u8 hdr_type, progif; 458 struct device_node *dev; 459 struct ccsr_pci __iomem *pci; 460 461 dev = pdev->dev.of_node; 462 463 if (!of_device_is_available(dev)) { 464 pr_warning("%s: disabled\n", dev->full_name); 465 return -ENODEV; 466 } 467 468 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 469 470 /* Fetch host bridge registers address */ 471 if (of_address_to_resource(dev, 0, &rsrc)) { 472 printk(KERN_WARNING "Can't get pci register base!"); 473 return -ENOMEM; 474 } 475 476 /* Get bus range if any */ 477 bus_range = of_get_property(dev, "bus-range", &len); 478 if (bus_range == NULL || len < 2 * sizeof(int)) 479 printk(KERN_WARNING "Can't get bus-range for %s, assume" 480 " bus 0\n", dev->full_name); 481 482 pci_add_flags(PCI_REASSIGN_ALL_BUS); 483 hose = pcibios_alloc_controller(dev); 484 if (!hose) 485 return -ENOMEM; 486 487 /* set platform device as the parent */ 488 hose->parent = &pdev->dev; 489 hose->first_busno = bus_range ? bus_range[0] : 0x0; 490 hose->last_busno = bus_range ? bus_range[1] : 0xff; 491 492 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", 493 (u64)rsrc.start, (u64)resource_size(&rsrc)); 494 495 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc)); 496 if (!hose->private_data) 497 goto no_bridge; 498 499 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, 500 PPC_INDIRECT_TYPE_BIG_ENDIAN); 501 502 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) 503 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; 504 505 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 506 /* use fsl_indirect_read_config for PCIe */ 507 hose->ops = &fsl_indirect_pcie_ops; 508 /* For PCIE read HEADER_TYPE to identify controler mode */ 509 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type); 510 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) 511 goto no_bridge; 512 513 } else { 514 /* For PCI read PROG to identify controller mode */ 515 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif); 516 if ((progif & 1) == 1) 517 goto no_bridge; 518 } 519 520 setup_pci_cmd(hose); 521 522 /* check PCI express link status */ 523 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 524 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | 525 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; 526 if (fsl_pcie_check_link(hose)) 527 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 528 } 529 530 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 531 "Firmware bus number: %d->%d\n", 532 (unsigned long long)rsrc.start, hose->first_busno, 533 hose->last_busno); 534 535 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 536 hose, hose->cfg_addr, hose->cfg_data); 537 538 /* Interpret the "ranges" property */ 539 /* This also maps the I/O region and sets isa_io/mem_base */ 540 pci_process_bridge_OF_ranges(hose, dev, is_primary); 541 542 /* Setup PEX window registers */ 543 setup_pci_atmu(hose); 544 545 return 0; 546 547 no_bridge: 548 iounmap(hose->private_data); 549 /* unmap cfg_data & cfg_addr separately if not on same page */ 550 if (((unsigned long)hose->cfg_data & PAGE_MASK) != 551 ((unsigned long)hose->cfg_addr & PAGE_MASK)) 552 iounmap(hose->cfg_data); 553 iounmap(hose->cfg_addr); 554 pcibios_free_controller(hose); 555 return -ENODEV; 556 } 557 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ 558 559 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header); 560 561 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) 562 struct mpc83xx_pcie_priv { 563 void __iomem *cfg_type0; 564 void __iomem *cfg_type1; 565 u32 dev_base; 566 }; 567 568 struct pex_inbound_window { 569 u32 ar; 570 u32 tar; 571 u32 barl; 572 u32 barh; 573 }; 574 575 /* 576 * With the convention of u-boot, the PCIE outbound window 0 serves 577 * as configuration transactions outbound. 578 */ 579 #define PEX_OUTWIN0_BAR 0xCA4 580 #define PEX_OUTWIN0_TAL 0xCA8 581 #define PEX_OUTWIN0_TAH 0xCAC 582 #define PEX_RC_INWIN_BASE 0xE60 583 #define PEX_RCIWARn_EN 0x1 584 585 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) 586 { 587 struct pci_controller *hose = pci_bus_to_host(bus); 588 589 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) 590 return PCIBIOS_DEVICE_NOT_FOUND; 591 /* 592 * Workaround for the HW bug: for Type 0 configure transactions the 593 * PCI-E controller does not check the device number bits and just 594 * assumes that the device number bits are 0. 595 */ 596 if (bus->number == hose->first_busno || 597 bus->primary == hose->first_busno) { 598 if (devfn & 0xf8) 599 return PCIBIOS_DEVICE_NOT_FOUND; 600 } 601 602 if (ppc_md.pci_exclude_device) { 603 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 604 return PCIBIOS_DEVICE_NOT_FOUND; 605 } 606 607 return PCIBIOS_SUCCESSFUL; 608 } 609 610 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, 611 unsigned int devfn, int offset) 612 { 613 struct pci_controller *hose = pci_bus_to_host(bus); 614 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 615 u32 dev_base = bus->number << 24 | devfn << 16; 616 int ret; 617 618 ret = mpc83xx_pcie_exclude_device(bus, devfn); 619 if (ret) 620 return NULL; 621 622 offset &= 0xfff; 623 624 /* Type 0 */ 625 if (bus->number == hose->first_busno) 626 return pcie->cfg_type0 + offset; 627 628 if (pcie->dev_base == dev_base) 629 goto mapped; 630 631 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); 632 633 pcie->dev_base = dev_base; 634 mapped: 635 return pcie->cfg_type1 + offset; 636 } 637 638 static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn, 639 int offset, int len, u32 *val) 640 { 641 void __iomem *cfg_addr; 642 643 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); 644 if (!cfg_addr) 645 return PCIBIOS_DEVICE_NOT_FOUND; 646 647 switch (len) { 648 case 1: 649 *val = in_8(cfg_addr); 650 break; 651 case 2: 652 *val = in_le16(cfg_addr); 653 break; 654 default: 655 *val = in_le32(cfg_addr); 656 break; 657 } 658 659 return PCIBIOS_SUCCESSFUL; 660 } 661 662 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 663 int offset, int len, u32 val) 664 { 665 struct pci_controller *hose = pci_bus_to_host(bus); 666 void __iomem *cfg_addr; 667 668 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); 669 if (!cfg_addr) 670 return PCIBIOS_DEVICE_NOT_FOUND; 671 672 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */ 673 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno) 674 val &= 0xffffff00; 675 676 switch (len) { 677 case 1: 678 out_8(cfg_addr, val); 679 break; 680 case 2: 681 out_le16(cfg_addr, val); 682 break; 683 default: 684 out_le32(cfg_addr, val); 685 break; 686 } 687 688 return PCIBIOS_SUCCESSFUL; 689 } 690 691 static struct pci_ops mpc83xx_pcie_ops = { 692 .read = mpc83xx_pcie_read_config, 693 .write = mpc83xx_pcie_write_config, 694 }; 695 696 static int __init mpc83xx_pcie_setup(struct pci_controller *hose, 697 struct resource *reg) 698 { 699 struct mpc83xx_pcie_priv *pcie; 700 u32 cfg_bar; 701 int ret = -ENOMEM; 702 703 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); 704 if (!pcie) 705 return ret; 706 707 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); 708 if (!pcie->cfg_type0) 709 goto err0; 710 711 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); 712 if (!cfg_bar) { 713 /* PCI-E isn't configured. */ 714 ret = -ENODEV; 715 goto err1; 716 } 717 718 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); 719 if (!pcie->cfg_type1) 720 goto err1; 721 722 WARN_ON(hose->dn->data); 723 hose->dn->data = pcie; 724 hose->ops = &mpc83xx_pcie_ops; 725 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; 726 727 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); 728 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); 729 730 if (fsl_pcie_check_link(hose)) 731 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 732 733 return 0; 734 err1: 735 iounmap(pcie->cfg_type0); 736 err0: 737 kfree(pcie); 738 return ret; 739 740 } 741 742 int __init mpc83xx_add_bridge(struct device_node *dev) 743 { 744 int ret; 745 int len; 746 struct pci_controller *hose; 747 struct resource rsrc_reg; 748 struct resource rsrc_cfg; 749 const int *bus_range; 750 int primary; 751 752 is_mpc83xx_pci = 1; 753 754 if (!of_device_is_available(dev)) { 755 pr_warning("%s: disabled by the firmware.\n", 756 dev->full_name); 757 return -ENODEV; 758 } 759 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 760 761 /* Fetch host bridge registers address */ 762 if (of_address_to_resource(dev, 0, &rsrc_reg)) { 763 printk(KERN_WARNING "Can't get pci register base!\n"); 764 return -ENOMEM; 765 } 766 767 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg)); 768 769 if (of_address_to_resource(dev, 1, &rsrc_cfg)) { 770 printk(KERN_WARNING 771 "No pci config register base in dev tree, " 772 "using default\n"); 773 /* 774 * MPC83xx supports up to two host controllers 775 * one at 0x8500 has config space registers at 0x8300 776 * one at 0x8600 has config space registers at 0x8380 777 */ 778 if ((rsrc_reg.start & 0xfffff) == 0x8500) 779 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300; 780 else if ((rsrc_reg.start & 0xfffff) == 0x8600) 781 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380; 782 } 783 /* 784 * Controller at offset 0x8500 is primary 785 */ 786 if ((rsrc_reg.start & 0xfffff) == 0x8500) 787 primary = 1; 788 else 789 primary = 0; 790 791 /* Get bus range if any */ 792 bus_range = of_get_property(dev, "bus-range", &len); 793 if (bus_range == NULL || len < 2 * sizeof(int)) { 794 printk(KERN_WARNING "Can't get bus-range for %s, assume" 795 " bus 0\n", dev->full_name); 796 } 797 798 pci_add_flags(PCI_REASSIGN_ALL_BUS); 799 hose = pcibios_alloc_controller(dev); 800 if (!hose) 801 return -ENOMEM; 802 803 hose->first_busno = bus_range ? bus_range[0] : 0; 804 hose->last_busno = bus_range ? bus_range[1] : 0xff; 805 806 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { 807 ret = mpc83xx_pcie_setup(hose, &rsrc_reg); 808 if (ret) 809 goto err0; 810 } else { 811 setup_indirect_pci(hose, rsrc_cfg.start, 812 rsrc_cfg.start + 4, 0); 813 } 814 815 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 816 "Firmware bus number: %d->%d\n", 817 (unsigned long long)rsrc_reg.start, hose->first_busno, 818 hose->last_busno); 819 820 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 821 hose, hose->cfg_addr, hose->cfg_data); 822 823 /* Interpret the "ranges" property */ 824 /* This also maps the I/O region and sets isa_io/mem_base */ 825 pci_process_bridge_OF_ranges(hose, dev, primary); 826 827 return 0; 828 err0: 829 pcibios_free_controller(hose); 830 return ret; 831 } 832 #endif /* CONFIG_PPC_83xx */ 833 834 u64 fsl_pci_immrbar_base(struct pci_controller *hose) 835 { 836 #ifdef CONFIG_PPC_83xx 837 if (is_mpc83xx_pci) { 838 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 839 struct pex_inbound_window *in; 840 int i; 841 842 /* Walk the Root Complex Inbound windows to match IMMR base */ 843 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE; 844 for (i = 0; i < 4; i++) { 845 /* not enabled, skip */ 846 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN) 847 continue; 848 849 if (get_immrbase() == in_le32(&in[i].tar)) 850 return (u64)in_le32(&in[i].barh) << 32 | 851 in_le32(&in[i].barl); 852 } 853 854 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n"); 855 } 856 #endif 857 858 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 859 if (!is_mpc83xx_pci) { 860 u32 base; 861 862 pci_bus_read_config_dword(hose->bus, 863 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); 864 return base; 865 } 866 #endif 867 868 return 0; 869 } 870 871 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 872 static const struct of_device_id pci_ids[] = { 873 { .compatible = "fsl,mpc8540-pci", }, 874 { .compatible = "fsl,mpc8548-pcie", }, 875 { .compatible = "fsl,mpc8610-pci", }, 876 { .compatible = "fsl,mpc8641-pcie", }, 877 { .compatible = "fsl,qoriq-pcie-v2.1", }, 878 { .compatible = "fsl,qoriq-pcie-v2.2", }, 879 { .compatible = "fsl,qoriq-pcie-v2.3", }, 880 { .compatible = "fsl,qoriq-pcie-v2.4", }, 881 { .compatible = "fsl,qoriq-pcie-v3.0", }, 882 883 /* 884 * The following entries are for compatibility with older device 885 * trees. 886 */ 887 { .compatible = "fsl,p1022-pcie", }, 888 { .compatible = "fsl,p4080-pcie", }, 889 890 {}, 891 }; 892 893 struct device_node *fsl_pci_primary; 894 895 void fsl_pci_assign_primary(void) 896 { 897 struct device_node *np; 898 899 /* Callers can specify the primary bus using other means. */ 900 if (fsl_pci_primary) 901 return; 902 903 /* If a PCI host bridge contains an ISA node, it's primary. */ 904 np = of_find_node_by_type(NULL, "isa"); 905 while ((fsl_pci_primary = of_get_parent(np))) { 906 of_node_put(np); 907 np = fsl_pci_primary; 908 909 if (of_match_node(pci_ids, np) && of_device_is_available(np)) 910 return; 911 } 912 913 /* 914 * If there's no PCI host bridge with ISA, arbitrarily 915 * designate one as primary. This can go away once 916 * various bugs with primary-less systems are fixed. 917 */ 918 for_each_matching_node(np, pci_ids) { 919 if (of_device_is_available(np)) { 920 fsl_pci_primary = np; 921 of_node_put(np); 922 return; 923 } 924 } 925 } 926 927 static int fsl_pci_probe(struct platform_device *pdev) 928 { 929 int ret; 930 struct device_node *node; 931 #ifdef CONFIG_SWIOTLB 932 struct pci_controller *hose; 933 #endif 934 935 node = pdev->dev.of_node; 936 ret = fsl_add_bridge(pdev, fsl_pci_primary == node); 937 938 #ifdef CONFIG_SWIOTLB 939 if (ret == 0) { 940 hose = pci_find_hose_for_OF_device(pdev->dev.of_node); 941 942 /* 943 * if we couldn't map all of DRAM via the dma windows 944 * we need SWIOTLB to handle buffers located outside of 945 * dma capable memory region 946 */ 947 if (memblock_end_of_DRAM() - 1 > hose->dma_window_base_cur + 948 hose->dma_window_size) 949 ppc_swiotlb_enable = 1; 950 } 951 #endif 952 953 mpc85xx_pci_err_probe(pdev); 954 955 return 0; 956 } 957 958 #ifdef CONFIG_PM 959 static int fsl_pci_resume(struct device *dev) 960 { 961 struct pci_controller *hose; 962 struct resource pci_rsrc; 963 964 hose = pci_find_hose_for_OF_device(dev->of_node); 965 if (!hose) 966 return -ENODEV; 967 968 if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) { 969 dev_err(dev, "Get pci register base failed."); 970 return -ENODEV; 971 } 972 973 setup_pci_atmu(hose); 974 975 return 0; 976 } 977 978 static const struct dev_pm_ops pci_pm_ops = { 979 .resume = fsl_pci_resume, 980 }; 981 982 #define PCI_PM_OPS (&pci_pm_ops) 983 984 #else 985 986 #define PCI_PM_OPS NULL 987 988 #endif 989 990 static struct platform_driver fsl_pci_driver = { 991 .driver = { 992 .name = "fsl-pci", 993 .pm = PCI_PM_OPS, 994 .of_match_table = pci_ids, 995 }, 996 .probe = fsl_pci_probe, 997 }; 998 999 static int __init fsl_pci_init(void) 1000 { 1001 return platform_driver_register(&fsl_pci_driver); 1002 } 1003 arch_initcall(fsl_pci_init); 1004 #endif 1005