1 /* 2 * MPC83xx/85xx/86xx PCI/PCIE support routing. 3 * 4 * Copyright 2007-2010 Freescale Semiconductor, Inc. 5 * Copyright 2008-2009 MontaVista Software, Inc. 6 * 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 8 * Recode: ZHANG WEI <wei.zhang@freescale.com> 9 * Rewrite the routing for Frescale PCI and PCI Express 10 * Roy Zang <tie-fei.zang@freescale.com> 11 * MPC83xx PCI-Express support: 12 * Tony Li <tony.li@freescale.com> 13 * Anton Vorontsov <avorontsov@ru.mvista.com> 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 */ 20 #include <linux/kernel.h> 21 #include <linux/pci.h> 22 #include <linux/delay.h> 23 #include <linux/string.h> 24 #include <linux/init.h> 25 #include <linux/bootmem.h> 26 #include <linux/memblock.h> 27 #include <linux/log2.h> 28 #include <linux/slab.h> 29 30 #include <asm/io.h> 31 #include <asm/prom.h> 32 #include <asm/pci-bridge.h> 33 #include <asm/machdep.h> 34 #include <sysdev/fsl_soc.h> 35 #include <sysdev/fsl_pci.h> 36 37 static int fsl_pcie_bus_fixup, is_mpc83xx_pci; 38 39 static void __init quirk_fsl_pcie_header(struct pci_dev *dev) 40 { 41 /* if we aren't a PCIe don't bother */ 42 if (!pci_find_capability(dev, PCI_CAP_ID_EXP)) 43 return; 44 45 dev->class = PCI_CLASS_BRIDGE_PCI << 8; 46 fsl_pcie_bus_fixup = 1; 47 return; 48 } 49 50 static int __init fsl_pcie_check_link(struct pci_controller *hose) 51 { 52 u32 val; 53 54 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); 55 if (val < PCIE_LTSSM_L0) 56 return 1; 57 return 0; 58 } 59 60 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 61 static int __init setup_one_atmu(struct ccsr_pci __iomem *pci, 62 unsigned int index, const struct resource *res, 63 resource_size_t offset) 64 { 65 resource_size_t pci_addr = res->start - offset; 66 resource_size_t phys_addr = res->start; 67 resource_size_t size = res->end - res->start + 1; 68 u32 flags = 0x80044000; /* enable & mem R/W */ 69 unsigned int i; 70 71 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", 72 (u64)res->start, (u64)size); 73 74 if (res->flags & IORESOURCE_PREFETCH) 75 flags |= 0x10000000; /* enable relaxed ordering */ 76 77 for (i = 0; size > 0; i++) { 78 unsigned int bits = min(__ilog2(size), 79 __ffs(pci_addr | phys_addr)); 80 81 if (index + i >= 5) 82 return -1; 83 84 out_be32(&pci->pow[index + i].potar, pci_addr >> 12); 85 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); 86 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); 87 out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); 88 89 pci_addr += (resource_size_t)1U << bits; 90 phys_addr += (resource_size_t)1U << bits; 91 size -= (resource_size_t)1U << bits; 92 } 93 94 return i; 95 } 96 97 /* atmu setup for fsl pci/pcie controller */ 98 static void __init setup_pci_atmu(struct pci_controller *hose, 99 struct resource *rsrc) 100 { 101 struct ccsr_pci __iomem *pci; 102 int i, j, n, mem_log, win_idx = 2; 103 u64 mem, sz, paddr_hi = 0; 104 u64 paddr_lo = ULLONG_MAX; 105 u32 pcicsrbar = 0, pcicsrbar_sz; 106 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | 107 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 108 char *name = hose->dn->full_name; 109 110 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", 111 (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1); 112 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); 113 if (!pci) { 114 dev_err(hose->parent, "Unable to map ATMU registers\n"); 115 return; 116 } 117 118 /* Disable all windows (except powar0 since it's ignored) */ 119 for(i = 1; i < 5; i++) 120 out_be32(&pci->pow[i].powar, 0); 121 for(i = 0; i < 3; i++) 122 out_be32(&pci->piw[i].piwar, 0); 123 124 /* Setup outbound MEM window */ 125 for(i = 0, j = 1; i < 3; i++) { 126 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) 127 continue; 128 129 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); 130 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); 131 132 n = setup_one_atmu(pci, j, &hose->mem_resources[i], 133 hose->pci_mem_offset); 134 135 if (n < 0 || j >= 5) { 136 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i); 137 hose->mem_resources[i].flags |= IORESOURCE_DISABLED; 138 } else 139 j += n; 140 } 141 142 /* Setup outbound IO window */ 143 if (hose->io_resource.flags & IORESOURCE_IO) { 144 if (j >= 5) { 145 pr_err("Ran out of outbound PCI ATMUs for IO resource\n"); 146 } else { 147 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " 148 "phy base 0x%016llx.\n", 149 (u64)hose->io_resource.start, 150 (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1, 151 (u64)hose->io_base_phys); 152 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); 153 out_be32(&pci->pow[j].potear, 0); 154 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); 155 /* Enable, IO R/W */ 156 out_be32(&pci->pow[j].powar, 0x80088000 157 | (__ilog2(hose->io_resource.end 158 - hose->io_resource.start + 1) - 1)); 159 } 160 } 161 162 /* convert to pci address space */ 163 paddr_hi -= hose->pci_mem_offset; 164 paddr_lo -= hose->pci_mem_offset; 165 166 if (paddr_hi == paddr_lo) { 167 pr_err("%s: No outbound window space\n", name); 168 return ; 169 } 170 171 if (paddr_lo == 0) { 172 pr_err("%s: No space for inbound window\n", name); 173 return ; 174 } 175 176 /* setup PCSRBAR/PEXCSRBAR */ 177 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff); 178 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 179 pcicsrbar_sz = ~pcicsrbar_sz + 1; 180 181 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || 182 (paddr_lo > 0x100000000ull)) 183 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 184 else 185 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; 186 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar); 187 188 paddr_lo = min(paddr_lo, (u64)pcicsrbar); 189 190 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar); 191 192 /* Setup inbound mem window */ 193 mem = memblock_end_of_DRAM(); 194 sz = min(mem, paddr_lo); 195 mem_log = __ilog2_u64(sz); 196 197 /* PCIe can overmap inbound & outbound since RX & TX are separated */ 198 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 199 /* Size window to exact size if power-of-two or one size up */ 200 if ((1ull << mem_log) != mem) { 201 if ((1ull << mem_log) > mem) 202 pr_info("%s: Setting PCI inbound window " 203 "greater than memory size\n", name); 204 mem_log++; 205 } 206 207 piwar |= (mem_log - 1); 208 209 /* Setup inbound memory window */ 210 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 211 out_be32(&pci->piw[win_idx].piwbar, 0x00000000); 212 out_be32(&pci->piw[win_idx].piwar, piwar); 213 win_idx--; 214 215 hose->dma_window_base_cur = 0x00000000; 216 hose->dma_window_size = (resource_size_t)sz; 217 } else { 218 u64 paddr = 0; 219 220 /* Setup inbound memory window */ 221 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 222 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); 223 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1))); 224 win_idx--; 225 226 paddr += 1ull << mem_log; 227 sz -= 1ull << mem_log; 228 229 if (sz) { 230 mem_log = __ilog2_u64(sz); 231 piwar |= (mem_log - 1); 232 233 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 234 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); 235 out_be32(&pci->piw[win_idx].piwar, piwar); 236 win_idx--; 237 238 paddr += 1ull << mem_log; 239 } 240 241 hose->dma_window_base_cur = 0x00000000; 242 hose->dma_window_size = (resource_size_t)paddr; 243 } 244 245 if (hose->dma_window_size < mem) { 246 #ifndef CONFIG_SWIOTLB 247 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to " 248 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", 249 name); 250 #endif 251 /* adjusting outbound windows could reclaim space in mem map */ 252 if (paddr_hi < 0xffffffffull) 253 pr_warning("%s: WARNING: Outbound window cfg leaves " 254 "gaps in memory map. Adjusting the memory map " 255 "could reduce unnecessary bounce buffering.\n", 256 name); 257 258 pr_info("%s: DMA window size is 0x%llx\n", name, 259 (u64)hose->dma_window_size); 260 } 261 262 iounmap(pci); 263 } 264 265 static void __init setup_pci_cmd(struct pci_controller *hose) 266 { 267 u16 cmd; 268 int cap_x; 269 270 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); 271 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY 272 | PCI_COMMAND_IO; 273 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); 274 275 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); 276 if (cap_x) { 277 int pci_x_cmd = cap_x + PCI_X_CMD; 278 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 279 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 280 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); 281 } else { 282 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); 283 } 284 } 285 286 void fsl_pcibios_fixup_bus(struct pci_bus *bus) 287 { 288 struct pci_controller *hose = pci_bus_to_host(bus); 289 int i; 290 291 if ((bus->parent == hose->bus) && 292 ((fsl_pcie_bus_fixup && 293 early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) || 294 (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK))) 295 { 296 for (i = 0; i < 4; ++i) { 297 struct resource *res = bus->resource[i]; 298 struct resource *par = bus->parent->resource[i]; 299 if (res) { 300 res->start = 0; 301 res->end = 0; 302 res->flags = 0; 303 } 304 if (res && par) { 305 res->start = par->start; 306 res->end = par->end; 307 res->flags = par->flags; 308 } 309 } 310 } 311 } 312 313 int __init fsl_add_bridge(struct device_node *dev, int is_primary) 314 { 315 int len; 316 struct pci_controller *hose; 317 struct resource rsrc; 318 const int *bus_range; 319 320 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 321 322 /* Fetch host bridge registers address */ 323 if (of_address_to_resource(dev, 0, &rsrc)) { 324 printk(KERN_WARNING "Can't get pci register base!"); 325 return -ENOMEM; 326 } 327 328 /* Get bus range if any */ 329 bus_range = of_get_property(dev, "bus-range", &len); 330 if (bus_range == NULL || len < 2 * sizeof(int)) 331 printk(KERN_WARNING "Can't get bus-range for %s, assume" 332 " bus 0\n", dev->full_name); 333 334 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 335 hose = pcibios_alloc_controller(dev); 336 if (!hose) 337 return -ENOMEM; 338 339 hose->first_busno = bus_range ? bus_range[0] : 0x0; 340 hose->last_busno = bus_range ? bus_range[1] : 0xff; 341 342 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, 343 PPC_INDIRECT_TYPE_BIG_ENDIAN); 344 setup_pci_cmd(hose); 345 346 /* check PCI express link status */ 347 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 348 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | 349 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; 350 if (fsl_pcie_check_link(hose)) 351 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 352 } 353 354 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 355 "Firmware bus number: %d->%d\n", 356 (unsigned long long)rsrc.start, hose->first_busno, 357 hose->last_busno); 358 359 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 360 hose, hose->cfg_addr, hose->cfg_data); 361 362 /* Interpret the "ranges" property */ 363 /* This also maps the I/O region and sets isa_io/mem_base */ 364 pci_process_bridge_OF_ranges(hose, dev, is_primary); 365 366 /* Setup PEX window registers */ 367 setup_pci_atmu(hose, &rsrc); 368 369 return 0; 370 } 371 372 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header); 373 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header); 374 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header); 375 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header); 376 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header); 377 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header); 378 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header); 379 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569E, quirk_fsl_pcie_header); 380 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569, quirk_fsl_pcie_header); 381 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header); 382 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header); 383 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header); 384 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header); 385 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header); 386 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header); 387 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header); 388 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header); 389 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header); 390 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header); 391 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header); 392 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header); 393 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header); 394 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header); 395 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header); 396 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011E, quirk_fsl_pcie_header); 397 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011, quirk_fsl_pcie_header); 398 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013E, quirk_fsl_pcie_header); 399 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013, quirk_fsl_pcie_header); 400 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020E, quirk_fsl_pcie_header); 401 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020, quirk_fsl_pcie_header); 402 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021E, quirk_fsl_pcie_header); 403 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021, quirk_fsl_pcie_header); 404 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022E, quirk_fsl_pcie_header); 405 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022, quirk_fsl_pcie_header); 406 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010E, quirk_fsl_pcie_header); 407 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010, quirk_fsl_pcie_header); 408 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header); 409 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header); 410 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040E, quirk_fsl_pcie_header); 411 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040, quirk_fsl_pcie_header); 412 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041E, quirk_fsl_pcie_header); 413 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041, quirk_fsl_pcie_header); 414 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040E, quirk_fsl_pcie_header); 415 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040, quirk_fsl_pcie_header); 416 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080E, quirk_fsl_pcie_header); 417 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080, quirk_fsl_pcie_header); 418 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010E, quirk_fsl_pcie_header); 419 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010, quirk_fsl_pcie_header); 420 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020E, quirk_fsl_pcie_header); 421 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020, quirk_fsl_pcie_header); 422 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ 423 424 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) 425 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8308, quirk_fsl_pcie_header); 426 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header); 427 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header); 428 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header); 429 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315, quirk_fsl_pcie_header); 430 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377E, quirk_fsl_pcie_header); 431 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377, quirk_fsl_pcie_header); 432 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378E, quirk_fsl_pcie_header); 433 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378, quirk_fsl_pcie_header); 434 435 struct mpc83xx_pcie_priv { 436 void __iomem *cfg_type0; 437 void __iomem *cfg_type1; 438 u32 dev_base; 439 }; 440 441 struct pex_inbound_window { 442 u32 ar; 443 u32 tar; 444 u32 barl; 445 u32 barh; 446 }; 447 448 /* 449 * With the convention of u-boot, the PCIE outbound window 0 serves 450 * as configuration transactions outbound. 451 */ 452 #define PEX_OUTWIN0_BAR 0xCA4 453 #define PEX_OUTWIN0_TAL 0xCA8 454 #define PEX_OUTWIN0_TAH 0xCAC 455 #define PEX_RC_INWIN_BASE 0xE60 456 #define PEX_RCIWARn_EN 0x1 457 458 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) 459 { 460 struct pci_controller *hose = pci_bus_to_host(bus); 461 462 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) 463 return PCIBIOS_DEVICE_NOT_FOUND; 464 /* 465 * Workaround for the HW bug: for Type 0 configure transactions the 466 * PCI-E controller does not check the device number bits and just 467 * assumes that the device number bits are 0. 468 */ 469 if (bus->number == hose->first_busno || 470 bus->primary == hose->first_busno) { 471 if (devfn & 0xf8) 472 return PCIBIOS_DEVICE_NOT_FOUND; 473 } 474 475 if (ppc_md.pci_exclude_device) { 476 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 477 return PCIBIOS_DEVICE_NOT_FOUND; 478 } 479 480 return PCIBIOS_SUCCESSFUL; 481 } 482 483 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, 484 unsigned int devfn, int offset) 485 { 486 struct pci_controller *hose = pci_bus_to_host(bus); 487 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 488 u32 dev_base = bus->number << 24 | devfn << 16; 489 int ret; 490 491 ret = mpc83xx_pcie_exclude_device(bus, devfn); 492 if (ret) 493 return NULL; 494 495 offset &= 0xfff; 496 497 /* Type 0 */ 498 if (bus->number == hose->first_busno) 499 return pcie->cfg_type0 + offset; 500 501 if (pcie->dev_base == dev_base) 502 goto mapped; 503 504 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); 505 506 pcie->dev_base = dev_base; 507 mapped: 508 return pcie->cfg_type1 + offset; 509 } 510 511 static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn, 512 int offset, int len, u32 *val) 513 { 514 void __iomem *cfg_addr; 515 516 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); 517 if (!cfg_addr) 518 return PCIBIOS_DEVICE_NOT_FOUND; 519 520 switch (len) { 521 case 1: 522 *val = in_8(cfg_addr); 523 break; 524 case 2: 525 *val = in_le16(cfg_addr); 526 break; 527 default: 528 *val = in_le32(cfg_addr); 529 break; 530 } 531 532 return PCIBIOS_SUCCESSFUL; 533 } 534 535 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 536 int offset, int len, u32 val) 537 { 538 struct pci_controller *hose = pci_bus_to_host(bus); 539 void __iomem *cfg_addr; 540 541 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); 542 if (!cfg_addr) 543 return PCIBIOS_DEVICE_NOT_FOUND; 544 545 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */ 546 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno) 547 val &= 0xffffff00; 548 549 switch (len) { 550 case 1: 551 out_8(cfg_addr, val); 552 break; 553 case 2: 554 out_le16(cfg_addr, val); 555 break; 556 default: 557 out_le32(cfg_addr, val); 558 break; 559 } 560 561 return PCIBIOS_SUCCESSFUL; 562 } 563 564 static struct pci_ops mpc83xx_pcie_ops = { 565 .read = mpc83xx_pcie_read_config, 566 .write = mpc83xx_pcie_write_config, 567 }; 568 569 static int __init mpc83xx_pcie_setup(struct pci_controller *hose, 570 struct resource *reg) 571 { 572 struct mpc83xx_pcie_priv *pcie; 573 u32 cfg_bar; 574 int ret = -ENOMEM; 575 576 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); 577 if (!pcie) 578 return ret; 579 580 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); 581 if (!pcie->cfg_type0) 582 goto err0; 583 584 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); 585 if (!cfg_bar) { 586 /* PCI-E isn't configured. */ 587 ret = -ENODEV; 588 goto err1; 589 } 590 591 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); 592 if (!pcie->cfg_type1) 593 goto err1; 594 595 WARN_ON(hose->dn->data); 596 hose->dn->data = pcie; 597 hose->ops = &mpc83xx_pcie_ops; 598 599 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); 600 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); 601 602 if (fsl_pcie_check_link(hose)) 603 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 604 605 return 0; 606 err1: 607 iounmap(pcie->cfg_type0); 608 err0: 609 kfree(pcie); 610 return ret; 611 612 } 613 614 int __init mpc83xx_add_bridge(struct device_node *dev) 615 { 616 int ret; 617 int len; 618 struct pci_controller *hose; 619 struct resource rsrc_reg; 620 struct resource rsrc_cfg; 621 const int *bus_range; 622 int primary; 623 624 is_mpc83xx_pci = 1; 625 626 if (!of_device_is_available(dev)) { 627 pr_warning("%s: disabled by the firmware.\n", 628 dev->full_name); 629 return -ENODEV; 630 } 631 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 632 633 /* Fetch host bridge registers address */ 634 if (of_address_to_resource(dev, 0, &rsrc_reg)) { 635 printk(KERN_WARNING "Can't get pci register base!\n"); 636 return -ENOMEM; 637 } 638 639 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg)); 640 641 if (of_address_to_resource(dev, 1, &rsrc_cfg)) { 642 printk(KERN_WARNING 643 "No pci config register base in dev tree, " 644 "using default\n"); 645 /* 646 * MPC83xx supports up to two host controllers 647 * one at 0x8500 has config space registers at 0x8300 648 * one at 0x8600 has config space registers at 0x8380 649 */ 650 if ((rsrc_reg.start & 0xfffff) == 0x8500) 651 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300; 652 else if ((rsrc_reg.start & 0xfffff) == 0x8600) 653 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380; 654 } 655 /* 656 * Controller at offset 0x8500 is primary 657 */ 658 if ((rsrc_reg.start & 0xfffff) == 0x8500) 659 primary = 1; 660 else 661 primary = 0; 662 663 /* Get bus range if any */ 664 bus_range = of_get_property(dev, "bus-range", &len); 665 if (bus_range == NULL || len < 2 * sizeof(int)) { 666 printk(KERN_WARNING "Can't get bus-range for %s, assume" 667 " bus 0\n", dev->full_name); 668 } 669 670 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 671 hose = pcibios_alloc_controller(dev); 672 if (!hose) 673 return -ENOMEM; 674 675 hose->first_busno = bus_range ? bus_range[0] : 0; 676 hose->last_busno = bus_range ? bus_range[1] : 0xff; 677 678 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { 679 ret = mpc83xx_pcie_setup(hose, &rsrc_reg); 680 if (ret) 681 goto err0; 682 } else { 683 setup_indirect_pci(hose, rsrc_cfg.start, 684 rsrc_cfg.start + 4, 0); 685 } 686 687 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 688 "Firmware bus number: %d->%d\n", 689 (unsigned long long)rsrc_reg.start, hose->first_busno, 690 hose->last_busno); 691 692 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 693 hose, hose->cfg_addr, hose->cfg_data); 694 695 /* Interpret the "ranges" property */ 696 /* This also maps the I/O region and sets isa_io/mem_base */ 697 pci_process_bridge_OF_ranges(hose, dev, primary); 698 699 return 0; 700 err0: 701 pcibios_free_controller(hose); 702 return ret; 703 } 704 #endif /* CONFIG_PPC_83xx */ 705 706 u64 fsl_pci_immrbar_base(struct pci_controller *hose) 707 { 708 #ifdef CONFIG_PPC_83xx 709 if (is_mpc83xx_pci) { 710 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 711 struct pex_inbound_window *in; 712 int i; 713 714 /* Walk the Root Complex Inbound windows to match IMMR base */ 715 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE; 716 for (i = 0; i < 4; i++) { 717 /* not enabled, skip */ 718 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN) 719 continue; 720 721 if (get_immrbase() == in_le32(&in[i].tar)) 722 return (u64)in_le32(&in[i].barh) << 32 | 723 in_le32(&in[i].barl); 724 } 725 726 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n"); 727 } 728 #endif 729 730 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 731 if (!is_mpc83xx_pci) { 732 u32 base; 733 734 pci_bus_read_config_dword(hose->bus, 735 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); 736 return base; 737 } 738 #endif 739 740 return 0; 741 } 742