1 /* 2 * MPC83xx/85xx/86xx PCI/PCIE support routing. 3 * 4 * Copyright 2007-2009 Freescale Semiconductor, Inc. 5 * Copyright 2008-2009 MontaVista Software, Inc. 6 * 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 8 * Recode: ZHANG WEI <wei.zhang@freescale.com> 9 * Rewrite the routing for Frescale PCI and PCI Express 10 * Roy Zang <tie-fei.zang@freescale.com> 11 * MPC83xx PCI-Express support: 12 * Tony Li <tony.li@freescale.com> 13 * Anton Vorontsov <avorontsov@ru.mvista.com> 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 */ 20 #include <linux/kernel.h> 21 #include <linux/pci.h> 22 #include <linux/delay.h> 23 #include <linux/string.h> 24 #include <linux/init.h> 25 #include <linux/bootmem.h> 26 27 #include <asm/io.h> 28 #include <asm/prom.h> 29 #include <asm/pci-bridge.h> 30 #include <asm/machdep.h> 31 #include <sysdev/fsl_soc.h> 32 #include <sysdev/fsl_pci.h> 33 34 static int fsl_pcie_bus_fixup; 35 36 static void __init quirk_fsl_pcie_header(struct pci_dev *dev) 37 { 38 /* if we aren't a PCIe don't bother */ 39 if (!pci_find_capability(dev, PCI_CAP_ID_EXP)) 40 return; 41 42 dev->class = PCI_CLASS_BRIDGE_PCI << 8; 43 fsl_pcie_bus_fixup = 1; 44 return; 45 } 46 47 static int __init fsl_pcie_check_link(struct pci_controller *hose) 48 { 49 u32 val; 50 51 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); 52 if (val < PCIE_LTSSM_L0) 53 return 1; 54 return 0; 55 } 56 57 #if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx) 58 static int __init setup_one_atmu(struct ccsr_pci __iomem *pci, 59 unsigned int index, const struct resource *res, 60 resource_size_t offset) 61 { 62 resource_size_t pci_addr = res->start - offset; 63 resource_size_t phys_addr = res->start; 64 resource_size_t size = res->end - res->start + 1; 65 u32 flags = 0x80044000; /* enable & mem R/W */ 66 unsigned int i; 67 68 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", 69 (u64)res->start, (u64)size); 70 71 if (res->flags & IORESOURCE_PREFETCH) 72 flags |= 0x10000000; /* enable relaxed ordering */ 73 74 for (i = 0; size > 0; i++) { 75 unsigned int bits = min(__ilog2(size), 76 __ffs(pci_addr | phys_addr)); 77 78 if (index + i >= 5) 79 return -1; 80 81 out_be32(&pci->pow[index + i].potar, pci_addr >> 12); 82 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); 83 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); 84 out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); 85 86 pci_addr += (resource_size_t)1U << bits; 87 phys_addr += (resource_size_t)1U << bits; 88 size -= (resource_size_t)1U << bits; 89 } 90 91 return i; 92 } 93 94 /* atmu setup for fsl pci/pcie controller */ 95 static void __init setup_pci_atmu(struct pci_controller *hose, 96 struct resource *rsrc) 97 { 98 struct ccsr_pci __iomem *pci; 99 int i, j, n; 100 101 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", 102 (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1); 103 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); 104 if (!pci) { 105 dev_err(hose->parent, "Unable to map ATMU registers\n"); 106 return; 107 } 108 109 /* Disable all windows (except powar0 since it's ignored) */ 110 for(i = 1; i < 5; i++) 111 out_be32(&pci->pow[i].powar, 0); 112 for(i = 0; i < 3; i++) 113 out_be32(&pci->piw[i].piwar, 0); 114 115 /* Setup outbound MEM window */ 116 for(i = 0, j = 1; i < 3; i++) { 117 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) 118 continue; 119 120 n = setup_one_atmu(pci, j, &hose->mem_resources[i], 121 hose->pci_mem_offset); 122 123 if (n < 0 || j >= 5) { 124 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i); 125 hose->mem_resources[i].flags |= IORESOURCE_DISABLED; 126 } else 127 j += n; 128 } 129 130 /* Setup outbound IO window */ 131 if (hose->io_resource.flags & IORESOURCE_IO) { 132 if (j >= 5) { 133 pr_err("Ran out of outbound PCI ATMUs for IO resource\n"); 134 } else { 135 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " 136 "phy base 0x%016llx.\n", 137 (u64)hose->io_resource.start, 138 (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1, 139 (u64)hose->io_base_phys); 140 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); 141 out_be32(&pci->pow[j].potear, 0); 142 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); 143 /* Enable, IO R/W */ 144 out_be32(&pci->pow[j].powar, 0x80088000 145 | (__ilog2(hose->io_resource.end 146 - hose->io_resource.start + 1) - 1)); 147 } 148 } 149 150 /* Setup 2G inbound Memory Window @ 1 */ 151 out_be32(&pci->piw[2].pitar, 0x00000000); 152 out_be32(&pci->piw[2].piwbar,0x00000000); 153 out_be32(&pci->piw[2].piwar, PIWAR_2G); 154 155 iounmap(pci); 156 } 157 158 static void __init setup_pci_cmd(struct pci_controller *hose) 159 { 160 u16 cmd; 161 int cap_x; 162 163 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); 164 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY 165 | PCI_COMMAND_IO; 166 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); 167 168 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); 169 if (cap_x) { 170 int pci_x_cmd = cap_x + PCI_X_CMD; 171 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 172 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 173 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); 174 } else { 175 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); 176 } 177 } 178 179 static void __init setup_pci_pcsrbar(struct pci_controller *hose) 180 { 181 #ifdef CONFIG_PCI_MSI 182 phys_addr_t immr_base; 183 184 immr_base = get_immrbase(); 185 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, immr_base); 186 #endif 187 } 188 189 void fsl_pcibios_fixup_bus(struct pci_bus *bus) 190 { 191 struct pci_controller *hose = (struct pci_controller *) bus->sysdata; 192 int i; 193 194 if ((bus->parent == hose->bus) && 195 ((fsl_pcie_bus_fixup && 196 early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) || 197 (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK))) 198 { 199 for (i = 0; i < 4; ++i) { 200 struct resource *res = bus->resource[i]; 201 struct resource *par = bus->parent->resource[i]; 202 if (res) { 203 res->start = 0; 204 res->end = 0; 205 res->flags = 0; 206 } 207 if (res && par) { 208 res->start = par->start; 209 res->end = par->end; 210 res->flags = par->flags; 211 } 212 } 213 } 214 } 215 216 int __init fsl_add_bridge(struct device_node *dev, int is_primary) 217 { 218 int len; 219 struct pci_controller *hose; 220 struct resource rsrc; 221 const int *bus_range; 222 223 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 224 225 /* Fetch host bridge registers address */ 226 if (of_address_to_resource(dev, 0, &rsrc)) { 227 printk(KERN_WARNING "Can't get pci register base!"); 228 return -ENOMEM; 229 } 230 231 /* Get bus range if any */ 232 bus_range = of_get_property(dev, "bus-range", &len); 233 if (bus_range == NULL || len < 2 * sizeof(int)) 234 printk(KERN_WARNING "Can't get bus-range for %s, assume" 235 " bus 0\n", dev->full_name); 236 237 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 238 hose = pcibios_alloc_controller(dev); 239 if (!hose) 240 return -ENOMEM; 241 242 hose->first_busno = bus_range ? bus_range[0] : 0x0; 243 hose->last_busno = bus_range ? bus_range[1] : 0xff; 244 245 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, 246 PPC_INDIRECT_TYPE_BIG_ENDIAN); 247 setup_pci_cmd(hose); 248 249 /* check PCI express link status */ 250 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 251 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | 252 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; 253 if (fsl_pcie_check_link(hose)) 254 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 255 } 256 257 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 258 "Firmware bus number: %d->%d\n", 259 (unsigned long long)rsrc.start, hose->first_busno, 260 hose->last_busno); 261 262 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 263 hose, hose->cfg_addr, hose->cfg_data); 264 265 /* Interpret the "ranges" property */ 266 /* This also maps the I/O region and sets isa_io/mem_base */ 267 pci_process_bridge_OF_ranges(hose, dev, is_primary); 268 269 /* Setup PEX window registers */ 270 setup_pci_atmu(hose, &rsrc); 271 272 /* Setup PEXCSRBAR */ 273 setup_pci_pcsrbar(hose); 274 return 0; 275 } 276 277 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header); 278 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header); 279 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header); 280 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header); 281 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header); 282 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header); 283 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header); 284 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header); 285 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header); 286 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header); 287 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header); 288 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header); 289 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header); 290 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header); 291 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header); 292 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header); 293 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header); 294 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header); 295 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header); 296 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header); 297 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header); 298 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header); 299 #endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */ 300 301 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) 302 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header); 303 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header); 304 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header); 305 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315, quirk_fsl_pcie_header); 306 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377E, quirk_fsl_pcie_header); 307 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377, quirk_fsl_pcie_header); 308 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378E, quirk_fsl_pcie_header); 309 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378, quirk_fsl_pcie_header); 310 311 struct mpc83xx_pcie_priv { 312 void __iomem *cfg_type0; 313 void __iomem *cfg_type1; 314 u32 dev_base; 315 }; 316 317 /* 318 * With the convention of u-boot, the PCIE outbound window 0 serves 319 * as configuration transactions outbound. 320 */ 321 #define PEX_OUTWIN0_BAR 0xCA4 322 #define PEX_OUTWIN0_TAL 0xCA8 323 #define PEX_OUTWIN0_TAH 0xCAC 324 325 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) 326 { 327 struct pci_controller *hose = bus->sysdata; 328 329 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) 330 return PCIBIOS_DEVICE_NOT_FOUND; 331 /* 332 * Workaround for the HW bug: for Type 0 configure transactions the 333 * PCI-E controller does not check the device number bits and just 334 * assumes that the device number bits are 0. 335 */ 336 if (bus->number == hose->first_busno || 337 bus->primary == hose->first_busno) { 338 if (devfn & 0xf8) 339 return PCIBIOS_DEVICE_NOT_FOUND; 340 } 341 342 if (ppc_md.pci_exclude_device) { 343 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 344 return PCIBIOS_DEVICE_NOT_FOUND; 345 } 346 347 return PCIBIOS_SUCCESSFUL; 348 } 349 350 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, 351 unsigned int devfn, int offset) 352 { 353 struct pci_controller *hose = bus->sysdata; 354 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 355 u8 bus_no = bus->number - hose->first_busno; 356 u32 dev_base = bus_no << 24 | devfn << 16; 357 int ret; 358 359 ret = mpc83xx_pcie_exclude_device(bus, devfn); 360 if (ret) 361 return NULL; 362 363 offset &= 0xfff; 364 365 /* Type 0 */ 366 if (bus->number == hose->first_busno) 367 return pcie->cfg_type0 + offset; 368 369 if (pcie->dev_base == dev_base) 370 goto mapped; 371 372 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); 373 374 pcie->dev_base = dev_base; 375 mapped: 376 return pcie->cfg_type1 + offset; 377 } 378 379 static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn, 380 int offset, int len, u32 *val) 381 { 382 void __iomem *cfg_addr; 383 384 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); 385 if (!cfg_addr) 386 return PCIBIOS_DEVICE_NOT_FOUND; 387 388 switch (len) { 389 case 1: 390 *val = in_8(cfg_addr); 391 break; 392 case 2: 393 *val = in_le16(cfg_addr); 394 break; 395 default: 396 *val = in_le32(cfg_addr); 397 break; 398 } 399 400 return PCIBIOS_SUCCESSFUL; 401 } 402 403 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 404 int offset, int len, u32 val) 405 { 406 void __iomem *cfg_addr; 407 408 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); 409 if (!cfg_addr) 410 return PCIBIOS_DEVICE_NOT_FOUND; 411 412 switch (len) { 413 case 1: 414 out_8(cfg_addr, val); 415 break; 416 case 2: 417 out_le16(cfg_addr, val); 418 break; 419 default: 420 out_le32(cfg_addr, val); 421 break; 422 } 423 424 return PCIBIOS_SUCCESSFUL; 425 } 426 427 static struct pci_ops mpc83xx_pcie_ops = { 428 .read = mpc83xx_pcie_read_config, 429 .write = mpc83xx_pcie_write_config, 430 }; 431 432 static int __init mpc83xx_pcie_setup(struct pci_controller *hose, 433 struct resource *reg) 434 { 435 struct mpc83xx_pcie_priv *pcie; 436 u32 cfg_bar; 437 int ret = -ENOMEM; 438 439 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); 440 if (!pcie) 441 return ret; 442 443 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); 444 if (!pcie->cfg_type0) 445 goto err0; 446 447 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); 448 if (!cfg_bar) { 449 /* PCI-E isn't configured. */ 450 ret = -ENODEV; 451 goto err1; 452 } 453 454 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); 455 if (!pcie->cfg_type1) 456 goto err1; 457 458 WARN_ON(hose->dn->data); 459 hose->dn->data = pcie; 460 hose->ops = &mpc83xx_pcie_ops; 461 462 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); 463 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); 464 465 if (fsl_pcie_check_link(hose)) 466 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 467 468 return 0; 469 err1: 470 iounmap(pcie->cfg_type0); 471 err0: 472 kfree(pcie); 473 return ret; 474 475 } 476 477 int __init mpc83xx_add_bridge(struct device_node *dev) 478 { 479 int ret; 480 int len; 481 struct pci_controller *hose; 482 struct resource rsrc_reg; 483 struct resource rsrc_cfg; 484 const int *bus_range; 485 int primary; 486 487 if (!of_device_is_available(dev)) { 488 pr_warning("%s: disabled by the firmware.\n", 489 dev->full_name); 490 return -ENODEV; 491 } 492 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 493 494 /* Fetch host bridge registers address */ 495 if (of_address_to_resource(dev, 0, &rsrc_reg)) { 496 printk(KERN_WARNING "Can't get pci register base!\n"); 497 return -ENOMEM; 498 } 499 500 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg)); 501 502 if (of_address_to_resource(dev, 1, &rsrc_cfg)) { 503 printk(KERN_WARNING 504 "No pci config register base in dev tree, " 505 "using default\n"); 506 /* 507 * MPC83xx supports up to two host controllers 508 * one at 0x8500 has config space registers at 0x8300 509 * one at 0x8600 has config space registers at 0x8380 510 */ 511 if ((rsrc_reg.start & 0xfffff) == 0x8500) 512 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300; 513 else if ((rsrc_reg.start & 0xfffff) == 0x8600) 514 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380; 515 } 516 /* 517 * Controller at offset 0x8500 is primary 518 */ 519 if ((rsrc_reg.start & 0xfffff) == 0x8500) 520 primary = 1; 521 else 522 primary = 0; 523 524 /* Get bus range if any */ 525 bus_range = of_get_property(dev, "bus-range", &len); 526 if (bus_range == NULL || len < 2 * sizeof(int)) { 527 printk(KERN_WARNING "Can't get bus-range for %s, assume" 528 " bus 0\n", dev->full_name); 529 } 530 531 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 532 hose = pcibios_alloc_controller(dev); 533 if (!hose) 534 return -ENOMEM; 535 536 hose->first_busno = bus_range ? bus_range[0] : 0; 537 hose->last_busno = bus_range ? bus_range[1] : 0xff; 538 539 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { 540 ret = mpc83xx_pcie_setup(hose, &rsrc_reg); 541 if (ret) 542 goto err0; 543 } else { 544 setup_indirect_pci(hose, rsrc_cfg.start, 545 rsrc_cfg.start + 4, 0); 546 } 547 548 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 549 "Firmware bus number: %d->%d\n", 550 (unsigned long long)rsrc_reg.start, hose->first_busno, 551 hose->last_busno); 552 553 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 554 hose, hose->cfg_addr, hose->cfg_data); 555 556 /* Interpret the "ranges" property */ 557 /* This also maps the I/O region and sets isa_io/mem_base */ 558 pci_process_bridge_OF_ranges(hose, dev, primary); 559 560 return 0; 561 err0: 562 pcibios_free_controller(hose); 563 return ret; 564 } 565 #endif /* CONFIG_PPC_83xx */ 566