1 /* 2 * MPC83xx/85xx/86xx PCI/PCIE support routing. 3 * 4 * Copyright 2007-2012 Freescale Semiconductor, Inc. 5 * Copyright 2008-2009 MontaVista Software, Inc. 6 * 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 8 * Recode: ZHANG WEI <wei.zhang@freescale.com> 9 * Rewrite the routing for Frescale PCI and PCI Express 10 * Roy Zang <tie-fei.zang@freescale.com> 11 * MPC83xx PCI-Express support: 12 * Tony Li <tony.li@freescale.com> 13 * Anton Vorontsov <avorontsov@ru.mvista.com> 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 */ 20 #include <linux/kernel.h> 21 #include <linux/pci.h> 22 #include <linux/delay.h> 23 #include <linux/string.h> 24 #include <linux/init.h> 25 #include <linux/interrupt.h> 26 #include <linux/bootmem.h> 27 #include <linux/memblock.h> 28 #include <linux/log2.h> 29 #include <linux/slab.h> 30 #include <linux/suspend.h> 31 #include <linux/syscore_ops.h> 32 #include <linux/uaccess.h> 33 34 #include <asm/io.h> 35 #include <asm/prom.h> 36 #include <asm/pci-bridge.h> 37 #include <asm/ppc-pci.h> 38 #include <asm/machdep.h> 39 #include <asm/disassemble.h> 40 #include <asm/ppc-opcode.h> 41 #include <sysdev/fsl_soc.h> 42 #include <sysdev/fsl_pci.h> 43 44 static int fsl_pcie_bus_fixup, is_mpc83xx_pci; 45 46 static void quirk_fsl_pcie_early(struct pci_dev *dev) 47 { 48 u8 hdr_type; 49 50 /* if we aren't a PCIe don't bother */ 51 if (!pci_is_pcie(dev)) 52 return; 53 54 /* if we aren't in host mode don't bother */ 55 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 56 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) 57 return; 58 59 dev->class = PCI_CLASS_BRIDGE_PCI << 8; 60 fsl_pcie_bus_fixup = 1; 61 return; 62 } 63 64 static int fsl_indirect_read_config(struct pci_bus *, unsigned int, 65 int, int, u32 *); 66 67 static int fsl_pcie_check_link(struct pci_controller *hose) 68 { 69 u32 val = 0; 70 71 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { 72 if (hose->ops->read == fsl_indirect_read_config) { 73 struct pci_bus bus; 74 bus.number = hose->first_busno; 75 bus.sysdata = hose; 76 bus.ops = hose->ops; 77 indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val); 78 } else 79 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); 80 if (val < PCIE_LTSSM_L0) 81 return 1; 82 } else { 83 struct ccsr_pci __iomem *pci = hose->private_data; 84 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */ 85 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) 86 >> PEX_CSR0_LTSSM_SHIFT; 87 if (val != PEX_CSR0_LTSSM_L0) 88 return 1; 89 } 90 91 return 0; 92 } 93 94 static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn, 95 int offset, int len, u32 *val) 96 { 97 struct pci_controller *hose = pci_bus_to_host(bus); 98 99 if (fsl_pcie_check_link(hose)) 100 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 101 else 102 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; 103 104 return indirect_read_config(bus, devfn, offset, len, val); 105 } 106 107 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 108 109 static struct pci_ops fsl_indirect_pcie_ops = 110 { 111 .read = fsl_indirect_read_config, 112 .write = indirect_write_config, 113 }; 114 115 #define MAX_PHYS_ADDR_BITS 40 116 static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS; 117 118 static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask) 119 { 120 if (!dev->dma_mask || !dma_supported(dev, dma_mask)) 121 return -EIO; 122 123 /* 124 * Fixup PCI devices that are able to DMA to above the physical 125 * address width of the SoC such that we can address any internal 126 * SoC address from across PCI if needed 127 */ 128 if ((dev_is_pci(dev)) && 129 dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) { 130 set_dma_ops(dev, &dma_direct_ops); 131 set_dma_offset(dev, pci64_dma_offset); 132 } 133 134 *dev->dma_mask = dma_mask; 135 return 0; 136 } 137 138 static int setup_one_atmu(struct ccsr_pci __iomem *pci, 139 unsigned int index, const struct resource *res, 140 resource_size_t offset) 141 { 142 resource_size_t pci_addr = res->start - offset; 143 resource_size_t phys_addr = res->start; 144 resource_size_t size = resource_size(res); 145 u32 flags = 0x80044000; /* enable & mem R/W */ 146 unsigned int i; 147 148 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", 149 (u64)res->start, (u64)size); 150 151 if (res->flags & IORESOURCE_PREFETCH) 152 flags |= 0x10000000; /* enable relaxed ordering */ 153 154 for (i = 0; size > 0; i++) { 155 unsigned int bits = min(ilog2(size), 156 __ffs(pci_addr | phys_addr)); 157 158 if (index + i >= 5) 159 return -1; 160 161 out_be32(&pci->pow[index + i].potar, pci_addr >> 12); 162 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); 163 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); 164 out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); 165 166 pci_addr += (resource_size_t)1U << bits; 167 phys_addr += (resource_size_t)1U << bits; 168 size -= (resource_size_t)1U << bits; 169 } 170 171 return i; 172 } 173 174 /* atmu setup for fsl pci/pcie controller */ 175 static void setup_pci_atmu(struct pci_controller *hose) 176 { 177 struct ccsr_pci __iomem *pci = hose->private_data; 178 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4; 179 u64 mem, sz, paddr_hi = 0; 180 u64 offset = 0, paddr_lo = ULLONG_MAX; 181 u32 pcicsrbar = 0, pcicsrbar_sz; 182 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | 183 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 184 const char *name = hose->dn->full_name; 185 const u64 *reg; 186 int len; 187 188 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 189 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) { 190 win_idx = 2; 191 start_idx = 0; 192 end_idx = 3; 193 } 194 } 195 196 /* Disable all windows (except powar0 since it's ignored) */ 197 for(i = 1; i < 5; i++) 198 out_be32(&pci->pow[i].powar, 0); 199 for (i = start_idx; i < end_idx; i++) 200 out_be32(&pci->piw[i].piwar, 0); 201 202 /* Setup outbound MEM window */ 203 for(i = 0, j = 1; i < 3; i++) { 204 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) 205 continue; 206 207 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); 208 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); 209 210 /* We assume all memory resources have the same offset */ 211 offset = hose->mem_offset[i]; 212 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset); 213 214 if (n < 0 || j >= 5) { 215 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i); 216 hose->mem_resources[i].flags |= IORESOURCE_DISABLED; 217 } else 218 j += n; 219 } 220 221 /* Setup outbound IO window */ 222 if (hose->io_resource.flags & IORESOURCE_IO) { 223 if (j >= 5) { 224 pr_err("Ran out of outbound PCI ATMUs for IO resource\n"); 225 } else { 226 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " 227 "phy base 0x%016llx.\n", 228 (u64)hose->io_resource.start, 229 (u64)resource_size(&hose->io_resource), 230 (u64)hose->io_base_phys); 231 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); 232 out_be32(&pci->pow[j].potear, 0); 233 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); 234 /* Enable, IO R/W */ 235 out_be32(&pci->pow[j].powar, 0x80088000 236 | (ilog2(hose->io_resource.end 237 - hose->io_resource.start + 1) - 1)); 238 } 239 } 240 241 /* convert to pci address space */ 242 paddr_hi -= offset; 243 paddr_lo -= offset; 244 245 if (paddr_hi == paddr_lo) { 246 pr_err("%s: No outbound window space\n", name); 247 return; 248 } 249 250 if (paddr_lo == 0) { 251 pr_err("%s: No space for inbound window\n", name); 252 return; 253 } 254 255 /* setup PCSRBAR/PEXCSRBAR */ 256 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff); 257 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 258 pcicsrbar_sz = ~pcicsrbar_sz + 1; 259 260 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || 261 (paddr_lo > 0x100000000ull)) 262 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 263 else 264 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; 265 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar); 266 267 paddr_lo = min(paddr_lo, (u64)pcicsrbar); 268 269 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar); 270 271 /* Setup inbound mem window */ 272 mem = memblock_end_of_DRAM(); 273 274 /* 275 * The msi-address-64 property, if it exists, indicates the physical 276 * address of the MSIIR register. Normally, this register is located 277 * inside CCSR, so the ATMU that covers all of CCSR is used. But if 278 * this property exists, then we normally need to create a new ATMU 279 * for it. For now, however, we cheat. The only entity that creates 280 * this property is the Freescale hypervisor, and the address is 281 * specified in the partition configuration. Typically, the address 282 * is located in the page immediately after the end of DDR. If so, we 283 * can avoid allocating a new ATMU by extending the DDR ATMU by one 284 * page. 285 */ 286 reg = of_get_property(hose->dn, "msi-address-64", &len); 287 if (reg && (len == sizeof(u64))) { 288 u64 address = be64_to_cpup(reg); 289 290 if ((address >= mem) && (address < (mem + PAGE_SIZE))) { 291 pr_info("%s: extending DDR ATMU to cover MSIIR", name); 292 mem += PAGE_SIZE; 293 } else { 294 /* TODO: Create a new ATMU for MSIIR */ 295 pr_warn("%s: msi-address-64 address of %llx is " 296 "unsupported\n", name, address); 297 } 298 } 299 300 sz = min(mem, paddr_lo); 301 mem_log = ilog2(sz); 302 303 /* PCIe can overmap inbound & outbound since RX & TX are separated */ 304 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 305 /* Size window to exact size if power-of-two or one size up */ 306 if ((1ull << mem_log) != mem) { 307 mem_log++; 308 if ((1ull << mem_log) > mem) 309 pr_info("%s: Setting PCI inbound window " 310 "greater than memory size\n", name); 311 } 312 313 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK); 314 315 /* Setup inbound memory window */ 316 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 317 out_be32(&pci->piw[win_idx].piwbar, 0x00000000); 318 out_be32(&pci->piw[win_idx].piwar, piwar); 319 win_idx--; 320 321 hose->dma_window_base_cur = 0x00000000; 322 hose->dma_window_size = (resource_size_t)sz; 323 324 /* 325 * if we have >4G of memory setup second PCI inbound window to 326 * let devices that are 64-bit address capable to work w/o 327 * SWIOTLB and access the full range of memory 328 */ 329 if (sz != mem) { 330 mem_log = ilog2(mem); 331 332 /* Size window up if we dont fit in exact power-of-2 */ 333 if ((1ull << mem_log) != mem) 334 mem_log++; 335 336 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1); 337 338 /* Setup inbound memory window */ 339 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 340 out_be32(&pci->piw[win_idx].piwbear, 341 pci64_dma_offset >> 44); 342 out_be32(&pci->piw[win_idx].piwbar, 343 pci64_dma_offset >> 12); 344 out_be32(&pci->piw[win_idx].piwar, piwar); 345 346 /* 347 * install our own dma_set_mask handler to fixup dma_ops 348 * and dma_offset 349 */ 350 ppc_md.dma_set_mask = fsl_pci_dma_set_mask; 351 352 pr_info("%s: Setup 64-bit PCI DMA window\n", name); 353 } 354 } else { 355 u64 paddr = 0; 356 357 /* Setup inbound memory window */ 358 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 359 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); 360 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1))); 361 win_idx--; 362 363 paddr += 1ull << mem_log; 364 sz -= 1ull << mem_log; 365 366 if (sz) { 367 mem_log = ilog2(sz); 368 piwar |= (mem_log - 1); 369 370 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 371 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); 372 out_be32(&pci->piw[win_idx].piwar, piwar); 373 win_idx--; 374 375 paddr += 1ull << mem_log; 376 } 377 378 hose->dma_window_base_cur = 0x00000000; 379 hose->dma_window_size = (resource_size_t)paddr; 380 } 381 382 if (hose->dma_window_size < mem) { 383 #ifdef CONFIG_SWIOTLB 384 ppc_swiotlb_enable = 1; 385 #else 386 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to " 387 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", 388 name); 389 #endif 390 /* adjusting outbound windows could reclaim space in mem map */ 391 if (paddr_hi < 0xffffffffull) 392 pr_warning("%s: WARNING: Outbound window cfg leaves " 393 "gaps in memory map. Adjusting the memory map " 394 "could reduce unnecessary bounce buffering.\n", 395 name); 396 397 pr_info("%s: DMA window size is 0x%llx\n", name, 398 (u64)hose->dma_window_size); 399 } 400 } 401 402 static void __init setup_pci_cmd(struct pci_controller *hose) 403 { 404 u16 cmd; 405 int cap_x; 406 407 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); 408 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY 409 | PCI_COMMAND_IO; 410 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); 411 412 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); 413 if (cap_x) { 414 int pci_x_cmd = cap_x + PCI_X_CMD; 415 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 416 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 417 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); 418 } else { 419 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); 420 } 421 } 422 423 void fsl_pcibios_fixup_bus(struct pci_bus *bus) 424 { 425 struct pci_controller *hose = pci_bus_to_host(bus); 426 int i, is_pcie = 0, no_link; 427 428 /* The root complex bridge comes up with bogus resources, 429 * we copy the PHB ones in. 430 * 431 * With the current generic PCI code, the PHB bus no longer 432 * has bus->resource[0..4] set, so things are a bit more 433 * tricky. 434 */ 435 436 if (fsl_pcie_bus_fixup) 437 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP); 438 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK); 439 440 if (bus->parent == hose->bus && (is_pcie || no_link)) { 441 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) { 442 struct resource *res = bus->resource[i]; 443 struct resource *par; 444 445 if (!res) 446 continue; 447 if (i == 0) 448 par = &hose->io_resource; 449 else if (i < 4) 450 par = &hose->mem_resources[i-1]; 451 else par = NULL; 452 453 res->start = par ? par->start : 0; 454 res->end = par ? par->end : 0; 455 res->flags = par ? par->flags : 0; 456 } 457 } 458 } 459 460 int fsl_add_bridge(struct platform_device *pdev, int is_primary) 461 { 462 int len; 463 struct pci_controller *hose; 464 struct resource rsrc; 465 const int *bus_range; 466 u8 hdr_type, progif; 467 struct device_node *dev; 468 struct ccsr_pci __iomem *pci; 469 470 dev = pdev->dev.of_node; 471 472 if (!of_device_is_available(dev)) { 473 pr_warning("%s: disabled\n", dev->full_name); 474 return -ENODEV; 475 } 476 477 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 478 479 /* Fetch host bridge registers address */ 480 if (of_address_to_resource(dev, 0, &rsrc)) { 481 printk(KERN_WARNING "Can't get pci register base!"); 482 return -ENOMEM; 483 } 484 485 /* Get bus range if any */ 486 bus_range = of_get_property(dev, "bus-range", &len); 487 if (bus_range == NULL || len < 2 * sizeof(int)) 488 printk(KERN_WARNING "Can't get bus-range for %s, assume" 489 " bus 0\n", dev->full_name); 490 491 pci_add_flags(PCI_REASSIGN_ALL_BUS); 492 hose = pcibios_alloc_controller(dev); 493 if (!hose) 494 return -ENOMEM; 495 496 /* set platform device as the parent */ 497 hose->parent = &pdev->dev; 498 hose->first_busno = bus_range ? bus_range[0] : 0x0; 499 hose->last_busno = bus_range ? bus_range[1] : 0xff; 500 501 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", 502 (u64)rsrc.start, (u64)resource_size(&rsrc)); 503 504 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc)); 505 if (!hose->private_data) 506 goto no_bridge; 507 508 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, 509 PPC_INDIRECT_TYPE_BIG_ENDIAN); 510 511 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) 512 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; 513 514 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 515 /* use fsl_indirect_read_config for PCIe */ 516 hose->ops = &fsl_indirect_pcie_ops; 517 /* For PCIE read HEADER_TYPE to identify controler mode */ 518 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type); 519 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) 520 goto no_bridge; 521 522 } else { 523 /* For PCI read PROG to identify controller mode */ 524 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif); 525 if ((progif & 1) && 526 !of_property_read_bool(dev, "fsl,pci-agent-force-enum")) 527 goto no_bridge; 528 } 529 530 setup_pci_cmd(hose); 531 532 /* check PCI express link status */ 533 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 534 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | 535 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; 536 if (fsl_pcie_check_link(hose)) 537 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 538 } 539 540 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 541 "Firmware bus number: %d->%d\n", 542 (unsigned long long)rsrc.start, hose->first_busno, 543 hose->last_busno); 544 545 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 546 hose, hose->cfg_addr, hose->cfg_data); 547 548 /* Interpret the "ranges" property */ 549 /* This also maps the I/O region and sets isa_io/mem_base */ 550 pci_process_bridge_OF_ranges(hose, dev, is_primary); 551 552 /* Setup PEX window registers */ 553 setup_pci_atmu(hose); 554 555 return 0; 556 557 no_bridge: 558 iounmap(hose->private_data); 559 /* unmap cfg_data & cfg_addr separately if not on same page */ 560 if (((unsigned long)hose->cfg_data & PAGE_MASK) != 561 ((unsigned long)hose->cfg_addr & PAGE_MASK)) 562 iounmap(hose->cfg_data); 563 iounmap(hose->cfg_addr); 564 pcibios_free_controller(hose); 565 return -ENODEV; 566 } 567 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ 568 569 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, 570 quirk_fsl_pcie_early); 571 572 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) 573 struct mpc83xx_pcie_priv { 574 void __iomem *cfg_type0; 575 void __iomem *cfg_type1; 576 u32 dev_base; 577 }; 578 579 struct pex_inbound_window { 580 u32 ar; 581 u32 tar; 582 u32 barl; 583 u32 barh; 584 }; 585 586 /* 587 * With the convention of u-boot, the PCIE outbound window 0 serves 588 * as configuration transactions outbound. 589 */ 590 #define PEX_OUTWIN0_BAR 0xCA4 591 #define PEX_OUTWIN0_TAL 0xCA8 592 #define PEX_OUTWIN0_TAH 0xCAC 593 #define PEX_RC_INWIN_BASE 0xE60 594 #define PEX_RCIWARn_EN 0x1 595 596 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) 597 { 598 struct pci_controller *hose = pci_bus_to_host(bus); 599 600 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) 601 return PCIBIOS_DEVICE_NOT_FOUND; 602 /* 603 * Workaround for the HW bug: for Type 0 configure transactions the 604 * PCI-E controller does not check the device number bits and just 605 * assumes that the device number bits are 0. 606 */ 607 if (bus->number == hose->first_busno || 608 bus->primary == hose->first_busno) { 609 if (devfn & 0xf8) 610 return PCIBIOS_DEVICE_NOT_FOUND; 611 } 612 613 if (ppc_md.pci_exclude_device) { 614 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 615 return PCIBIOS_DEVICE_NOT_FOUND; 616 } 617 618 return PCIBIOS_SUCCESSFUL; 619 } 620 621 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, 622 unsigned int devfn, int offset) 623 { 624 struct pci_controller *hose = pci_bus_to_host(bus); 625 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 626 u32 dev_base = bus->number << 24 | devfn << 16; 627 int ret; 628 629 ret = mpc83xx_pcie_exclude_device(bus, devfn); 630 if (ret) 631 return NULL; 632 633 offset &= 0xfff; 634 635 /* Type 0 */ 636 if (bus->number == hose->first_busno) 637 return pcie->cfg_type0 + offset; 638 639 if (pcie->dev_base == dev_base) 640 goto mapped; 641 642 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); 643 644 pcie->dev_base = dev_base; 645 mapped: 646 return pcie->cfg_type1 + offset; 647 } 648 649 static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn, 650 int offset, int len, u32 *val) 651 { 652 void __iomem *cfg_addr; 653 654 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); 655 if (!cfg_addr) 656 return PCIBIOS_DEVICE_NOT_FOUND; 657 658 switch (len) { 659 case 1: 660 *val = in_8(cfg_addr); 661 break; 662 case 2: 663 *val = in_le16(cfg_addr); 664 break; 665 default: 666 *val = in_le32(cfg_addr); 667 break; 668 } 669 670 return PCIBIOS_SUCCESSFUL; 671 } 672 673 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 674 int offset, int len, u32 val) 675 { 676 struct pci_controller *hose = pci_bus_to_host(bus); 677 void __iomem *cfg_addr; 678 679 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); 680 if (!cfg_addr) 681 return PCIBIOS_DEVICE_NOT_FOUND; 682 683 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */ 684 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno) 685 val &= 0xffffff00; 686 687 switch (len) { 688 case 1: 689 out_8(cfg_addr, val); 690 break; 691 case 2: 692 out_le16(cfg_addr, val); 693 break; 694 default: 695 out_le32(cfg_addr, val); 696 break; 697 } 698 699 return PCIBIOS_SUCCESSFUL; 700 } 701 702 static struct pci_ops mpc83xx_pcie_ops = { 703 .read = mpc83xx_pcie_read_config, 704 .write = mpc83xx_pcie_write_config, 705 }; 706 707 static int __init mpc83xx_pcie_setup(struct pci_controller *hose, 708 struct resource *reg) 709 { 710 struct mpc83xx_pcie_priv *pcie; 711 u32 cfg_bar; 712 int ret = -ENOMEM; 713 714 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); 715 if (!pcie) 716 return ret; 717 718 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); 719 if (!pcie->cfg_type0) 720 goto err0; 721 722 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); 723 if (!cfg_bar) { 724 /* PCI-E isn't configured. */ 725 ret = -ENODEV; 726 goto err1; 727 } 728 729 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); 730 if (!pcie->cfg_type1) 731 goto err1; 732 733 WARN_ON(hose->dn->data); 734 hose->dn->data = pcie; 735 hose->ops = &mpc83xx_pcie_ops; 736 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; 737 738 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); 739 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); 740 741 if (fsl_pcie_check_link(hose)) 742 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 743 744 return 0; 745 err1: 746 iounmap(pcie->cfg_type0); 747 err0: 748 kfree(pcie); 749 return ret; 750 751 } 752 753 int __init mpc83xx_add_bridge(struct device_node *dev) 754 { 755 int ret; 756 int len; 757 struct pci_controller *hose; 758 struct resource rsrc_reg; 759 struct resource rsrc_cfg; 760 const int *bus_range; 761 int primary; 762 763 is_mpc83xx_pci = 1; 764 765 if (!of_device_is_available(dev)) { 766 pr_warning("%s: disabled by the firmware.\n", 767 dev->full_name); 768 return -ENODEV; 769 } 770 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 771 772 /* Fetch host bridge registers address */ 773 if (of_address_to_resource(dev, 0, &rsrc_reg)) { 774 printk(KERN_WARNING "Can't get pci register base!\n"); 775 return -ENOMEM; 776 } 777 778 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg)); 779 780 if (of_address_to_resource(dev, 1, &rsrc_cfg)) { 781 printk(KERN_WARNING 782 "No pci config register base in dev tree, " 783 "using default\n"); 784 /* 785 * MPC83xx supports up to two host controllers 786 * one at 0x8500 has config space registers at 0x8300 787 * one at 0x8600 has config space registers at 0x8380 788 */ 789 if ((rsrc_reg.start & 0xfffff) == 0x8500) 790 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300; 791 else if ((rsrc_reg.start & 0xfffff) == 0x8600) 792 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380; 793 } 794 /* 795 * Controller at offset 0x8500 is primary 796 */ 797 if ((rsrc_reg.start & 0xfffff) == 0x8500) 798 primary = 1; 799 else 800 primary = 0; 801 802 /* Get bus range if any */ 803 bus_range = of_get_property(dev, "bus-range", &len); 804 if (bus_range == NULL || len < 2 * sizeof(int)) { 805 printk(KERN_WARNING "Can't get bus-range for %s, assume" 806 " bus 0\n", dev->full_name); 807 } 808 809 pci_add_flags(PCI_REASSIGN_ALL_BUS); 810 hose = pcibios_alloc_controller(dev); 811 if (!hose) 812 return -ENOMEM; 813 814 hose->first_busno = bus_range ? bus_range[0] : 0; 815 hose->last_busno = bus_range ? bus_range[1] : 0xff; 816 817 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { 818 ret = mpc83xx_pcie_setup(hose, &rsrc_reg); 819 if (ret) 820 goto err0; 821 } else { 822 setup_indirect_pci(hose, rsrc_cfg.start, 823 rsrc_cfg.start + 4, 0); 824 } 825 826 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 827 "Firmware bus number: %d->%d\n", 828 (unsigned long long)rsrc_reg.start, hose->first_busno, 829 hose->last_busno); 830 831 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 832 hose, hose->cfg_addr, hose->cfg_data); 833 834 /* Interpret the "ranges" property */ 835 /* This also maps the I/O region and sets isa_io/mem_base */ 836 pci_process_bridge_OF_ranges(hose, dev, primary); 837 838 return 0; 839 err0: 840 pcibios_free_controller(hose); 841 return ret; 842 } 843 #endif /* CONFIG_PPC_83xx */ 844 845 u64 fsl_pci_immrbar_base(struct pci_controller *hose) 846 { 847 #ifdef CONFIG_PPC_83xx 848 if (is_mpc83xx_pci) { 849 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 850 struct pex_inbound_window *in; 851 int i; 852 853 /* Walk the Root Complex Inbound windows to match IMMR base */ 854 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE; 855 for (i = 0; i < 4; i++) { 856 /* not enabled, skip */ 857 if (!(in_le32(&in[i].ar) & PEX_RCIWARn_EN)) 858 continue; 859 860 if (get_immrbase() == in_le32(&in[i].tar)) 861 return (u64)in_le32(&in[i].barh) << 32 | 862 in_le32(&in[i].barl); 863 } 864 865 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n"); 866 } 867 #endif 868 869 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 870 if (!is_mpc83xx_pci) { 871 u32 base; 872 873 pci_bus_read_config_dword(hose->bus, 874 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); 875 876 /* 877 * For PEXCSRBAR, bit 3-0 indicate prefetchable and 878 * address type. So when getting base address, these 879 * bits should be masked 880 */ 881 base &= PCI_BASE_ADDRESS_MEM_MASK; 882 883 return base; 884 } 885 #endif 886 887 return 0; 888 } 889 890 #ifdef CONFIG_E500 891 static int mcheck_handle_load(struct pt_regs *regs, u32 inst) 892 { 893 unsigned int rd, ra, rb, d; 894 895 rd = get_rt(inst); 896 ra = get_ra(inst); 897 rb = get_rb(inst); 898 d = get_d(inst); 899 900 switch (get_op(inst)) { 901 case 31: 902 switch (get_xop(inst)) { 903 case OP_31_XOP_LWZX: 904 case OP_31_XOP_LWBRX: 905 regs->gpr[rd] = 0xffffffff; 906 break; 907 908 case OP_31_XOP_LWZUX: 909 regs->gpr[rd] = 0xffffffff; 910 regs->gpr[ra] += regs->gpr[rb]; 911 break; 912 913 case OP_31_XOP_LBZX: 914 regs->gpr[rd] = 0xff; 915 break; 916 917 case OP_31_XOP_LBZUX: 918 regs->gpr[rd] = 0xff; 919 regs->gpr[ra] += regs->gpr[rb]; 920 break; 921 922 case OP_31_XOP_LHZX: 923 case OP_31_XOP_LHBRX: 924 regs->gpr[rd] = 0xffff; 925 break; 926 927 case OP_31_XOP_LHZUX: 928 regs->gpr[rd] = 0xffff; 929 regs->gpr[ra] += regs->gpr[rb]; 930 break; 931 932 case OP_31_XOP_LHAX: 933 regs->gpr[rd] = ~0UL; 934 break; 935 936 case OP_31_XOP_LHAUX: 937 regs->gpr[rd] = ~0UL; 938 regs->gpr[ra] += regs->gpr[rb]; 939 break; 940 941 default: 942 return 0; 943 } 944 break; 945 946 case OP_LWZ: 947 regs->gpr[rd] = 0xffffffff; 948 break; 949 950 case OP_LWZU: 951 regs->gpr[rd] = 0xffffffff; 952 regs->gpr[ra] += (s16)d; 953 break; 954 955 case OP_LBZ: 956 regs->gpr[rd] = 0xff; 957 break; 958 959 case OP_LBZU: 960 regs->gpr[rd] = 0xff; 961 regs->gpr[ra] += (s16)d; 962 break; 963 964 case OP_LHZ: 965 regs->gpr[rd] = 0xffff; 966 break; 967 968 case OP_LHZU: 969 regs->gpr[rd] = 0xffff; 970 regs->gpr[ra] += (s16)d; 971 break; 972 973 case OP_LHA: 974 regs->gpr[rd] = ~0UL; 975 break; 976 977 case OP_LHAU: 978 regs->gpr[rd] = ~0UL; 979 regs->gpr[ra] += (s16)d; 980 break; 981 982 default: 983 return 0; 984 } 985 986 return 1; 987 } 988 989 static int is_in_pci_mem_space(phys_addr_t addr) 990 { 991 struct pci_controller *hose; 992 struct resource *res; 993 int i; 994 995 list_for_each_entry(hose, &hose_list, list_node) { 996 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)) 997 continue; 998 999 for (i = 0; i < 3; i++) { 1000 res = &hose->mem_resources[i]; 1001 if ((res->flags & IORESOURCE_MEM) && 1002 addr >= res->start && addr <= res->end) 1003 return 1; 1004 } 1005 } 1006 return 0; 1007 } 1008 1009 int fsl_pci_mcheck_exception(struct pt_regs *regs) 1010 { 1011 u32 inst; 1012 int ret; 1013 phys_addr_t addr = 0; 1014 1015 /* Let KVM/QEMU deal with the exception */ 1016 if (regs->msr & MSR_GS) 1017 return 0; 1018 1019 #ifdef CONFIG_PHYS_64BIT 1020 addr = mfspr(SPRN_MCARU); 1021 addr <<= 32; 1022 #endif 1023 addr += mfspr(SPRN_MCAR); 1024 1025 if (is_in_pci_mem_space(addr)) { 1026 if (user_mode(regs)) { 1027 pagefault_disable(); 1028 ret = get_user(regs->nip, &inst); 1029 pagefault_enable(); 1030 } else { 1031 ret = probe_kernel_address(regs->nip, inst); 1032 } 1033 1034 if (mcheck_handle_load(regs, inst)) { 1035 regs->nip += 4; 1036 return 1; 1037 } 1038 } 1039 1040 return 0; 1041 } 1042 #endif 1043 1044 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 1045 static const struct of_device_id pci_ids[] = { 1046 { .compatible = "fsl,mpc8540-pci", }, 1047 { .compatible = "fsl,mpc8548-pcie", }, 1048 { .compatible = "fsl,mpc8610-pci", }, 1049 { .compatible = "fsl,mpc8641-pcie", }, 1050 { .compatible = "fsl,qoriq-pcie", }, 1051 { .compatible = "fsl,qoriq-pcie-v2.1", }, 1052 { .compatible = "fsl,qoriq-pcie-v2.2", }, 1053 { .compatible = "fsl,qoriq-pcie-v2.3", }, 1054 { .compatible = "fsl,qoriq-pcie-v2.4", }, 1055 { .compatible = "fsl,qoriq-pcie-v3.0", }, 1056 1057 /* 1058 * The following entries are for compatibility with older device 1059 * trees. 1060 */ 1061 { .compatible = "fsl,p1022-pcie", }, 1062 { .compatible = "fsl,p4080-pcie", }, 1063 1064 {}, 1065 }; 1066 1067 struct device_node *fsl_pci_primary; 1068 1069 void fsl_pci_assign_primary(void) 1070 { 1071 struct device_node *np; 1072 1073 /* Callers can specify the primary bus using other means. */ 1074 if (fsl_pci_primary) 1075 return; 1076 1077 /* If a PCI host bridge contains an ISA node, it's primary. */ 1078 np = of_find_node_by_type(NULL, "isa"); 1079 while ((fsl_pci_primary = of_get_parent(np))) { 1080 of_node_put(np); 1081 np = fsl_pci_primary; 1082 1083 if (of_match_node(pci_ids, np) && of_device_is_available(np)) 1084 return; 1085 } 1086 1087 /* 1088 * If there's no PCI host bridge with ISA, arbitrarily 1089 * designate one as primary. This can go away once 1090 * various bugs with primary-less systems are fixed. 1091 */ 1092 for_each_matching_node(np, pci_ids) { 1093 if (of_device_is_available(np)) { 1094 fsl_pci_primary = np; 1095 of_node_put(np); 1096 return; 1097 } 1098 } 1099 } 1100 1101 #ifdef CONFIG_PM_SLEEP 1102 static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id) 1103 { 1104 struct pci_controller *hose = dev_id; 1105 struct ccsr_pci __iomem *pci = hose->private_data; 1106 u32 dr; 1107 1108 dr = in_be32(&pci->pex_pme_mes_dr); 1109 if (!dr) 1110 return IRQ_NONE; 1111 1112 out_be32(&pci->pex_pme_mes_dr, dr); 1113 1114 return IRQ_HANDLED; 1115 } 1116 1117 static int fsl_pci_pme_probe(struct pci_controller *hose) 1118 { 1119 struct ccsr_pci __iomem *pci; 1120 struct pci_dev *dev; 1121 int pme_irq; 1122 int res; 1123 u16 pms; 1124 1125 /* Get hose's pci_dev */ 1126 dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list); 1127 1128 /* PME Disable */ 1129 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); 1130 pms &= ~PCI_PM_CTRL_PME_ENABLE; 1131 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); 1132 1133 pme_irq = irq_of_parse_and_map(hose->dn, 0); 1134 if (!pme_irq) { 1135 dev_err(&dev->dev, "Failed to map PME interrupt.\n"); 1136 1137 return -ENXIO; 1138 } 1139 1140 res = devm_request_irq(hose->parent, pme_irq, 1141 fsl_pci_pme_handle, 1142 IRQF_SHARED, 1143 "[PCI] PME", hose); 1144 if (res < 0) { 1145 dev_err(&dev->dev, "Unable to requiest irq %d for PME\n", pme_irq); 1146 irq_dispose_mapping(pme_irq); 1147 1148 return -ENODEV; 1149 } 1150 1151 pci = hose->private_data; 1152 1153 /* Enable PTOD, ENL23D & EXL23D */ 1154 clrbits32(&pci->pex_pme_mes_disr, 1155 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); 1156 1157 out_be32(&pci->pex_pme_mes_ier, 0); 1158 setbits32(&pci->pex_pme_mes_ier, 1159 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); 1160 1161 /* PME Enable */ 1162 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); 1163 pms |= PCI_PM_CTRL_PME_ENABLE; 1164 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); 1165 1166 return 0; 1167 } 1168 1169 static void send_pme_turnoff_message(struct pci_controller *hose) 1170 { 1171 struct ccsr_pci __iomem *pci = hose->private_data; 1172 u32 dr; 1173 int i; 1174 1175 /* Send PME_Turn_Off Message Request */ 1176 setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR); 1177 1178 /* Wait trun off done */ 1179 for (i = 0; i < 150; i++) { 1180 dr = in_be32(&pci->pex_pme_mes_dr); 1181 if (dr) { 1182 out_be32(&pci->pex_pme_mes_dr, dr); 1183 break; 1184 } 1185 1186 udelay(1000); 1187 } 1188 } 1189 1190 static void fsl_pci_syscore_do_suspend(struct pci_controller *hose) 1191 { 1192 send_pme_turnoff_message(hose); 1193 } 1194 1195 static int fsl_pci_syscore_suspend(void) 1196 { 1197 struct pci_controller *hose, *tmp; 1198 1199 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 1200 fsl_pci_syscore_do_suspend(hose); 1201 1202 return 0; 1203 } 1204 1205 static void fsl_pci_syscore_do_resume(struct pci_controller *hose) 1206 { 1207 struct ccsr_pci __iomem *pci = hose->private_data; 1208 u32 dr; 1209 int i; 1210 1211 /* Send Exit L2 State Message */ 1212 setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S); 1213 1214 /* Wait exit done */ 1215 for (i = 0; i < 150; i++) { 1216 dr = in_be32(&pci->pex_pme_mes_dr); 1217 if (dr) { 1218 out_be32(&pci->pex_pme_mes_dr, dr); 1219 break; 1220 } 1221 1222 udelay(1000); 1223 } 1224 1225 setup_pci_atmu(hose); 1226 } 1227 1228 static void fsl_pci_syscore_resume(void) 1229 { 1230 struct pci_controller *hose, *tmp; 1231 1232 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 1233 fsl_pci_syscore_do_resume(hose); 1234 } 1235 1236 static struct syscore_ops pci_syscore_pm_ops = { 1237 .suspend = fsl_pci_syscore_suspend, 1238 .resume = fsl_pci_syscore_resume, 1239 }; 1240 #endif 1241 1242 void fsl_pcibios_fixup_phb(struct pci_controller *phb) 1243 { 1244 #ifdef CONFIG_PM_SLEEP 1245 fsl_pci_pme_probe(phb); 1246 #endif 1247 } 1248 1249 static int fsl_pci_probe(struct platform_device *pdev) 1250 { 1251 struct device_node *node; 1252 int ret; 1253 1254 node = pdev->dev.of_node; 1255 ret = fsl_add_bridge(pdev, fsl_pci_primary == node); 1256 1257 mpc85xx_pci_err_probe(pdev); 1258 1259 return 0; 1260 } 1261 1262 static struct platform_driver fsl_pci_driver = { 1263 .driver = { 1264 .name = "fsl-pci", 1265 .of_match_table = pci_ids, 1266 }, 1267 .probe = fsl_pci_probe, 1268 }; 1269 1270 static int __init fsl_pci_init(void) 1271 { 1272 #ifdef CONFIG_PM_SLEEP 1273 register_syscore_ops(&pci_syscore_pm_ops); 1274 #endif 1275 return platform_driver_register(&fsl_pci_driver); 1276 } 1277 arch_initcall(fsl_pci_init); 1278 #endif 1279