1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MPC83xx/85xx/86xx PCI/PCIE support routing. 4 * 5 * Copyright 2007-2012 Freescale Semiconductor, Inc. 6 * Copyright 2008-2009 MontaVista Software, Inc. 7 * 8 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 9 * Recode: ZHANG WEI <wei.zhang@freescale.com> 10 * Rewrite the routing for Frescale PCI and PCI Express 11 * Roy Zang <tie-fei.zang@freescale.com> 12 * MPC83xx PCI-Express support: 13 * Tony Li <tony.li@freescale.com> 14 * Anton Vorontsov <avorontsov@ru.mvista.com> 15 */ 16 #include <linux/kernel.h> 17 #include <linux/pci.h> 18 #include <linux/delay.h> 19 #include <linux/string.h> 20 #include <linux/fsl/edac.h> 21 #include <linux/init.h> 22 #include <linux/interrupt.h> 23 #include <linux/memblock.h> 24 #include <linux/log2.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/platform_device.h> 28 #include <linux/slab.h> 29 #include <linux/suspend.h> 30 #include <linux/syscore_ops.h> 31 #include <linux/uaccess.h> 32 33 #include <asm/io.h> 34 #include <asm/pci-bridge.h> 35 #include <asm/ppc-pci.h> 36 #include <asm/machdep.h> 37 #include <asm/mpc85xx.h> 38 #include <asm/disassemble.h> 39 #include <asm/ppc-opcode.h> 40 #include <asm/swiotlb.h> 41 #include <asm/setup.h> 42 #include <sysdev/fsl_soc.h> 43 #include <sysdev/fsl_pci.h> 44 45 static int fsl_pcie_bus_fixup, is_mpc83xx_pci; 46 47 static void quirk_fsl_pcie_early(struct pci_dev *dev) 48 { 49 u8 hdr_type; 50 51 /* if we aren't a PCIe don't bother */ 52 if (!pci_is_pcie(dev)) 53 return; 54 55 /* if we aren't in host mode don't bother */ 56 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 57 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) 58 return; 59 60 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; 61 fsl_pcie_bus_fixup = 1; 62 return; 63 } 64 65 static int fsl_indirect_read_config(struct pci_bus *, unsigned int, 66 int, int, u32 *); 67 68 static int fsl_pcie_check_link(struct pci_controller *hose) 69 { 70 u32 val = 0; 71 72 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { 73 if (hose->ops->read == fsl_indirect_read_config) 74 __indirect_read_config(hose, hose->first_busno, 0, 75 PCIE_LTSSM, 4, &val); 76 else 77 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); 78 if (val < PCIE_LTSSM_L0) 79 return 1; 80 } else { 81 struct ccsr_pci __iomem *pci = hose->private_data; 82 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */ 83 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) 84 >> PEX_CSR0_LTSSM_SHIFT; 85 if (val != PEX_CSR0_LTSSM_L0) 86 return 1; 87 } 88 89 return 0; 90 } 91 92 static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn, 93 int offset, int len, u32 *val) 94 { 95 struct pci_controller *hose = pci_bus_to_host(bus); 96 97 if (fsl_pcie_check_link(hose)) 98 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 99 else 100 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; 101 102 return indirect_read_config(bus, devfn, offset, len, val); 103 } 104 105 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 106 107 static struct pci_ops fsl_indirect_pcie_ops = 108 { 109 .read = fsl_indirect_read_config, 110 .write = indirect_write_config, 111 }; 112 113 static u64 pci64_dma_offset; 114 115 #ifdef CONFIG_SWIOTLB 116 static void pci_dma_dev_setup_swiotlb(struct pci_dev *pdev) 117 { 118 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 119 120 pdev->dev.bus_dma_limit = 121 hose->dma_window_base_cur + hose->dma_window_size - 1; 122 } 123 124 static void setup_swiotlb_ops(struct pci_controller *hose) 125 { 126 if (ppc_swiotlb_enable) 127 hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb; 128 } 129 #else 130 static inline void setup_swiotlb_ops(struct pci_controller *hose) {} 131 #endif 132 133 static void fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask) 134 { 135 /* 136 * Fix up PCI devices that are able to DMA to the large inbound 137 * mapping that allows addressing any RAM address from across PCI. 138 */ 139 if (dev_is_pci(dev) && dma_mask >= pci64_dma_offset * 2 - 1) { 140 dev->bus_dma_limit = 0; 141 dev->archdata.dma_offset = pci64_dma_offset; 142 } 143 } 144 145 static int setup_one_atmu(struct ccsr_pci __iomem *pci, 146 unsigned int index, const struct resource *res, 147 resource_size_t offset) 148 { 149 resource_size_t pci_addr = res->start - offset; 150 resource_size_t phys_addr = res->start; 151 resource_size_t size = resource_size(res); 152 u32 flags = 0x80044000; /* enable & mem R/W */ 153 unsigned int i; 154 155 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", 156 (u64)res->start, (u64)size); 157 158 if (res->flags & IORESOURCE_PREFETCH) 159 flags |= 0x10000000; /* enable relaxed ordering */ 160 161 for (i = 0; size > 0; i++) { 162 unsigned int bits = min_t(u32, ilog2(size), 163 __ffs(pci_addr | phys_addr)); 164 165 if (index + i >= 5) 166 return -1; 167 168 out_be32(&pci->pow[index + i].potar, pci_addr >> 12); 169 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); 170 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); 171 out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); 172 173 pci_addr += (resource_size_t)1U << bits; 174 phys_addr += (resource_size_t)1U << bits; 175 size -= (resource_size_t)1U << bits; 176 } 177 178 return i; 179 } 180 181 static bool is_kdump(void) 182 { 183 struct device_node *node; 184 185 node = of_find_node_by_type(NULL, "memory"); 186 if (!node) { 187 WARN_ON_ONCE(1); 188 return false; 189 } 190 191 return of_property_read_bool(node, "linux,usable-memory"); 192 } 193 194 /* atmu setup for fsl pci/pcie controller */ 195 static void setup_pci_atmu(struct pci_controller *hose) 196 { 197 struct ccsr_pci __iomem *pci = hose->private_data; 198 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4; 199 u64 mem, sz, paddr_hi = 0; 200 u64 offset = 0, paddr_lo = ULLONG_MAX; 201 u32 pcicsrbar = 0, pcicsrbar_sz; 202 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | 203 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 204 const u64 *reg; 205 int len; 206 bool setup_inbound; 207 208 /* 209 * If this is kdump, we don't want to trigger a bunch of PCI 210 * errors by closing the window on in-flight DMA. 211 * 212 * We still run most of the function's logic so that things like 213 * hose->dma_window_size still get set. 214 */ 215 setup_inbound = !is_kdump(); 216 217 if (of_device_is_compatible(hose->dn, "fsl,bsc9132-pcie")) { 218 /* 219 * BSC9132 Rev1.0 has an issue where all the PEX inbound 220 * windows have implemented the default target value as 0xf 221 * for CCSR space.In all Freescale legacy devices the target 222 * of 0xf is reserved for local memory space. 9132 Rev1.0 223 * now has local memory space mapped to target 0x0 instead of 224 * 0xf. Hence adding a workaround to remove the target 0xf 225 * defined for memory space from Inbound window attributes. 226 */ 227 piwar &= ~PIWAR_TGI_LOCAL; 228 } 229 230 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 231 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) { 232 win_idx = 2; 233 start_idx = 0; 234 end_idx = 3; 235 } 236 } 237 238 /* Disable all windows (except powar0 since it's ignored) */ 239 for(i = 1; i < 5; i++) 240 out_be32(&pci->pow[i].powar, 0); 241 242 if (setup_inbound) { 243 for (i = start_idx; i < end_idx; i++) 244 out_be32(&pci->piw[i].piwar, 0); 245 } 246 247 /* Setup outbound MEM window */ 248 for(i = 0, j = 1; i < 3; i++) { 249 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) 250 continue; 251 252 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); 253 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); 254 255 /* We assume all memory resources have the same offset */ 256 offset = hose->mem_offset[i]; 257 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset); 258 259 if (n < 0 || j >= 5) { 260 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i); 261 hose->mem_resources[i].flags |= IORESOURCE_DISABLED; 262 } else 263 j += n; 264 } 265 266 /* Setup outbound IO window */ 267 if (hose->io_resource.flags & IORESOURCE_IO) { 268 if (j >= 5) { 269 pr_err("Ran out of outbound PCI ATMUs for IO resource\n"); 270 } else { 271 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " 272 "phy base 0x%016llx.\n", 273 (u64)hose->io_resource.start, 274 (u64)resource_size(&hose->io_resource), 275 (u64)hose->io_base_phys); 276 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); 277 out_be32(&pci->pow[j].potear, 0); 278 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); 279 /* Enable, IO R/W */ 280 out_be32(&pci->pow[j].powar, 0x80088000 281 | (ilog2(hose->io_resource.end 282 - hose->io_resource.start + 1) - 1)); 283 } 284 } 285 286 /* convert to pci address space */ 287 paddr_hi -= offset; 288 paddr_lo -= offset; 289 290 if (paddr_hi == paddr_lo) { 291 pr_err("%pOF: No outbound window space\n", hose->dn); 292 return; 293 } 294 295 if (paddr_lo == 0) { 296 pr_err("%pOF: No space for inbound window\n", hose->dn); 297 return; 298 } 299 300 /* setup PCSRBAR/PEXCSRBAR */ 301 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff); 302 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 303 pcicsrbar_sz = ~pcicsrbar_sz + 1; 304 305 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || 306 (paddr_lo > 0x100000000ull)) 307 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 308 else 309 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; 310 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar); 311 312 paddr_lo = min(paddr_lo, (u64)pcicsrbar); 313 314 pr_info("%pOF: PCICSRBAR @ 0x%x\n", hose->dn, pcicsrbar); 315 316 /* Setup inbound mem window */ 317 mem = memblock_end_of_DRAM(); 318 pr_info("%s: end of DRAM %llx\n", __func__, mem); 319 320 /* 321 * The msi-address-64 property, if it exists, indicates the physical 322 * address of the MSIIR register. Normally, this register is located 323 * inside CCSR, so the ATMU that covers all of CCSR is used. But if 324 * this property exists, then we normally need to create a new ATMU 325 * for it. For now, however, we cheat. The only entity that creates 326 * this property is the Freescale hypervisor, and the address is 327 * specified in the partition configuration. Typically, the address 328 * is located in the page immediately after the end of DDR. If so, we 329 * can avoid allocating a new ATMU by extending the DDR ATMU by one 330 * page. 331 */ 332 reg = of_get_property(hose->dn, "msi-address-64", &len); 333 if (reg && (len == sizeof(u64))) { 334 u64 address = be64_to_cpup(reg); 335 336 if ((address >= mem) && (address < (mem + PAGE_SIZE))) { 337 pr_info("%pOF: extending DDR ATMU to cover MSIIR", hose->dn); 338 mem += PAGE_SIZE; 339 } else { 340 /* TODO: Create a new ATMU for MSIIR */ 341 pr_warn("%pOF: msi-address-64 address of %llx is " 342 "unsupported\n", hose->dn, address); 343 } 344 } 345 346 sz = min(mem, paddr_lo); 347 mem_log = ilog2(sz); 348 349 /* PCIe can overmap inbound & outbound since RX & TX are separated */ 350 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 351 /* Size window to exact size if power-of-two or one size up */ 352 if ((1ull << mem_log) != mem) { 353 mem_log++; 354 if ((1ull << mem_log) > mem) 355 pr_info("%pOF: Setting PCI inbound window " 356 "greater than memory size\n", hose->dn); 357 } 358 359 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK); 360 361 if (setup_inbound) { 362 /* Setup inbound memory window */ 363 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 364 out_be32(&pci->piw[win_idx].piwbar, 0x00000000); 365 out_be32(&pci->piw[win_idx].piwar, piwar); 366 } 367 368 win_idx--; 369 hose->dma_window_base_cur = 0x00000000; 370 hose->dma_window_size = (resource_size_t)sz; 371 372 /* 373 * if we have >4G of memory setup second PCI inbound window to 374 * let devices that are 64-bit address capable to work w/o 375 * SWIOTLB and access the full range of memory 376 */ 377 if (sz != mem) { 378 mem_log = ilog2(mem); 379 380 /* Size window up if we dont fit in exact power-of-2 */ 381 if ((1ull << mem_log) != mem) 382 mem_log++; 383 384 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1); 385 pci64_dma_offset = 1ULL << mem_log; 386 387 if (setup_inbound) { 388 /* Setup inbound memory window */ 389 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 390 out_be32(&pci->piw[win_idx].piwbear, 391 pci64_dma_offset >> 44); 392 out_be32(&pci->piw[win_idx].piwbar, 393 pci64_dma_offset >> 12); 394 out_be32(&pci->piw[win_idx].piwar, piwar); 395 } 396 397 /* 398 * install our own dma_set_mask handler to fixup dma_ops 399 * and dma_offset 400 */ 401 ppc_md.dma_set_mask = fsl_pci_dma_set_mask; 402 403 pr_info("%pOF: Setup 64-bit PCI DMA window\n", hose->dn); 404 } 405 } else { 406 u64 paddr = 0; 407 408 if (setup_inbound) { 409 /* Setup inbound memory window */ 410 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 411 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); 412 out_be32(&pci->piw[win_idx].piwar, 413 (piwar | (mem_log - 1))); 414 } 415 416 win_idx--; 417 paddr += 1ull << mem_log; 418 sz -= 1ull << mem_log; 419 420 if (sz) { 421 mem_log = ilog2(sz); 422 piwar |= (mem_log - 1); 423 424 if (setup_inbound) { 425 out_be32(&pci->piw[win_idx].pitar, 426 paddr >> 12); 427 out_be32(&pci->piw[win_idx].piwbar, 428 paddr >> 12); 429 out_be32(&pci->piw[win_idx].piwar, piwar); 430 } 431 432 win_idx--; 433 paddr += 1ull << mem_log; 434 } 435 436 hose->dma_window_base_cur = 0x00000000; 437 hose->dma_window_size = (resource_size_t)paddr; 438 } 439 440 if (hose->dma_window_size < mem) { 441 #ifdef CONFIG_SWIOTLB 442 ppc_swiotlb_enable = 1; 443 #else 444 pr_err("%pOF: ERROR: Memory size exceeds PCI ATMU ability to " 445 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", 446 hose->dn); 447 #endif 448 /* adjusting outbound windows could reclaim space in mem map */ 449 if (paddr_hi < 0xffffffffull) 450 pr_warn("%pOF: WARNING: Outbound window cfg leaves " 451 "gaps in memory map. Adjusting the memory map " 452 "could reduce unnecessary bounce buffering.\n", 453 hose->dn); 454 455 pr_info("%pOF: DMA window size is 0x%llx\n", hose->dn, 456 (u64)hose->dma_window_size); 457 } 458 } 459 460 static void setup_pci_cmd(struct pci_controller *hose) 461 { 462 u16 cmd; 463 int cap_x; 464 465 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); 466 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY 467 | PCI_COMMAND_IO; 468 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); 469 470 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); 471 if (cap_x) { 472 int pci_x_cmd = cap_x + PCI_X_CMD; 473 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 474 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 475 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); 476 } else { 477 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); 478 } 479 } 480 481 void fsl_pcibios_fixup_bus(struct pci_bus *bus) 482 { 483 struct pci_controller *hose = pci_bus_to_host(bus); 484 int i, is_pcie = 0, no_link; 485 486 /* The root complex bridge comes up with bogus resources, 487 * we copy the PHB ones in. 488 * 489 * With the current generic PCI code, the PHB bus no longer 490 * has bus->resource[0..4] set, so things are a bit more 491 * tricky. 492 */ 493 494 if (fsl_pcie_bus_fixup) 495 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP); 496 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK); 497 498 if (bus->parent == hose->bus && (is_pcie || no_link)) { 499 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) { 500 struct resource *res = bus->resource[i]; 501 struct resource *par; 502 503 if (!res) 504 continue; 505 if (i == 0) 506 par = &hose->io_resource; 507 else if (i < 4) 508 par = &hose->mem_resources[i-1]; 509 else par = NULL; 510 511 res->start = par ? par->start : 0; 512 res->end = par ? par->end : 0; 513 res->flags = par ? par->flags : 0; 514 } 515 } 516 } 517 518 int fsl_add_bridge(struct platform_device *pdev, int is_primary) 519 { 520 int len; 521 struct pci_controller *hose; 522 struct resource rsrc; 523 const int *bus_range; 524 u8 hdr_type, progif; 525 u32 class_code; 526 struct device_node *dev; 527 struct ccsr_pci __iomem *pci; 528 u16 temp; 529 u32 svr = mfspr(SPRN_SVR); 530 531 dev = pdev->dev.of_node; 532 533 if (!of_device_is_available(dev)) { 534 pr_warn("%pOF: disabled\n", dev); 535 return -ENODEV; 536 } 537 538 pr_debug("Adding PCI host bridge %pOF\n", dev); 539 540 /* Fetch host bridge registers address */ 541 if (of_address_to_resource(dev, 0, &rsrc)) { 542 printk(KERN_WARNING "Can't get pci register base!"); 543 return -ENOMEM; 544 } 545 546 /* Get bus range if any */ 547 bus_range = of_get_property(dev, "bus-range", &len); 548 if (bus_range == NULL || len < 2 * sizeof(int)) 549 printk(KERN_WARNING "Can't get bus-range for %pOF, assume" 550 " bus 0\n", dev); 551 552 pci_add_flags(PCI_REASSIGN_ALL_BUS); 553 hose = pcibios_alloc_controller(dev); 554 if (!hose) 555 return -ENOMEM; 556 557 /* set platform device as the parent */ 558 hose->parent = &pdev->dev; 559 hose->first_busno = bus_range ? bus_range[0] : 0x0; 560 hose->last_busno = bus_range ? bus_range[1] : 0xff; 561 562 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", 563 (u64)rsrc.start, (u64)resource_size(&rsrc)); 564 565 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc)); 566 if (!hose->private_data) 567 goto no_bridge; 568 569 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, 570 PPC_INDIRECT_TYPE_BIG_ENDIAN); 571 572 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) 573 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; 574 575 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 576 /* use fsl_indirect_read_config for PCIe */ 577 hose->ops = &fsl_indirect_pcie_ops; 578 /* For PCIE read HEADER_TYPE to identify controller mode */ 579 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type); 580 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) 581 goto no_bridge; 582 583 } else { 584 /* For PCI read PROG to identify controller mode */ 585 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif); 586 if ((progif & 1) && 587 !of_property_read_bool(dev, "fsl,pci-agent-force-enum")) 588 goto no_bridge; 589 } 590 591 setup_pci_cmd(hose); 592 593 /* check PCI express link status */ 594 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 595 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | 596 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; 597 if (fsl_pcie_check_link(hose)) 598 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 599 /* Fix Class Code to PCI_CLASS_BRIDGE_PCI_NORMAL for pre-3.0 controller */ 600 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) { 601 early_read_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, &class_code); 602 class_code &= 0xff; 603 class_code |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8; 604 early_write_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, class_code); 605 } 606 } else { 607 /* 608 * Set PBFR(PCI Bus Function Register)[10] = 1 to 609 * disable the combining of crossing cacheline 610 * boundary requests into one burst transaction. 611 * PCI-X operation is not affected. 612 * Fix erratum PCI 5 on MPC8548 613 */ 614 #define PCI_BUS_FUNCTION 0x44 615 #define PCI_BUS_FUNCTION_MDS 0x400 /* Master disable streaming */ 616 if (((SVR_SOC_VER(svr) == SVR_8543) || 617 (SVR_SOC_VER(svr) == SVR_8545) || 618 (SVR_SOC_VER(svr) == SVR_8547) || 619 (SVR_SOC_VER(svr) == SVR_8548)) && 620 !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) { 621 early_read_config_word(hose, 0, 0, 622 PCI_BUS_FUNCTION, &temp); 623 temp |= PCI_BUS_FUNCTION_MDS; 624 early_write_config_word(hose, 0, 0, 625 PCI_BUS_FUNCTION, temp); 626 } 627 } 628 629 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 630 "Firmware bus number: %d->%d\n", 631 (unsigned long long)rsrc.start, hose->first_busno, 632 hose->last_busno); 633 634 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 635 hose, hose->cfg_addr, hose->cfg_data); 636 637 /* Interpret the "ranges" property */ 638 /* This also maps the I/O region and sets isa_io/mem_base */ 639 pci_process_bridge_OF_ranges(hose, dev, is_primary); 640 641 /* Setup PEX window registers */ 642 setup_pci_atmu(hose); 643 644 /* Set up controller operations */ 645 setup_swiotlb_ops(hose); 646 647 return 0; 648 649 no_bridge: 650 iounmap(hose->private_data); 651 /* unmap cfg_data & cfg_addr separately if not on same page */ 652 if (((unsigned long)hose->cfg_data & PAGE_MASK) != 653 ((unsigned long)hose->cfg_addr & PAGE_MASK)) 654 iounmap(hose->cfg_data); 655 iounmap(hose->cfg_addr); 656 pcibios_free_controller(hose); 657 return -ENODEV; 658 } 659 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ 660 661 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, 662 quirk_fsl_pcie_early); 663 664 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) 665 struct mpc83xx_pcie_priv { 666 void __iomem *cfg_type0; 667 void __iomem *cfg_type1; 668 u32 dev_base; 669 }; 670 671 struct pex_inbound_window { 672 u32 ar; 673 u32 tar; 674 u32 barl; 675 u32 barh; 676 }; 677 678 /* 679 * With the convention of u-boot, the PCIE outbound window 0 serves 680 * as configuration transactions outbound. 681 */ 682 #define PEX_OUTWIN0_BAR 0xCA4 683 #define PEX_OUTWIN0_TAL 0xCA8 684 #define PEX_OUTWIN0_TAH 0xCAC 685 #define PEX_RC_INWIN_BASE 0xE60 686 #define PEX_RCIWARn_EN 0x1 687 688 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) 689 { 690 struct pci_controller *hose = pci_bus_to_host(bus); 691 692 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) 693 return PCIBIOS_DEVICE_NOT_FOUND; 694 /* 695 * Workaround for the HW bug: for Type 0 configure transactions the 696 * PCI-E controller does not check the device number bits and just 697 * assumes that the device number bits are 0. 698 */ 699 if (bus->number == hose->first_busno || 700 bus->primary == hose->first_busno) { 701 if (devfn & 0xf8) 702 return PCIBIOS_DEVICE_NOT_FOUND; 703 } 704 705 if (ppc_md.pci_exclude_device) { 706 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 707 return PCIBIOS_DEVICE_NOT_FOUND; 708 } 709 710 return PCIBIOS_SUCCESSFUL; 711 } 712 713 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, 714 unsigned int devfn, int offset) 715 { 716 struct pci_controller *hose = pci_bus_to_host(bus); 717 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 718 u32 dev_base = bus->number << 24 | devfn << 16; 719 int ret; 720 721 ret = mpc83xx_pcie_exclude_device(bus, devfn); 722 if (ret) 723 return NULL; 724 725 offset &= 0xfff; 726 727 /* Type 0 */ 728 if (bus->number == hose->first_busno) 729 return pcie->cfg_type0 + offset; 730 731 if (pcie->dev_base == dev_base) 732 goto mapped; 733 734 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); 735 736 pcie->dev_base = dev_base; 737 mapped: 738 return pcie->cfg_type1 + offset; 739 } 740 741 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 742 int offset, int len, u32 val) 743 { 744 struct pci_controller *hose = pci_bus_to_host(bus); 745 746 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */ 747 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno) 748 val &= 0xffffff00; 749 750 return pci_generic_config_write(bus, devfn, offset, len, val); 751 } 752 753 static struct pci_ops mpc83xx_pcie_ops = { 754 .map_bus = mpc83xx_pcie_remap_cfg, 755 .read = pci_generic_config_read, 756 .write = mpc83xx_pcie_write_config, 757 }; 758 759 static int __init mpc83xx_pcie_setup(struct pci_controller *hose, 760 struct resource *reg) 761 { 762 struct mpc83xx_pcie_priv *pcie; 763 u32 cfg_bar; 764 int ret = -ENOMEM; 765 766 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); 767 if (!pcie) 768 return ret; 769 770 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); 771 if (!pcie->cfg_type0) 772 goto err0; 773 774 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); 775 if (!cfg_bar) { 776 /* PCI-E isn't configured. */ 777 ret = -ENODEV; 778 goto err1; 779 } 780 781 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); 782 if (!pcie->cfg_type1) 783 goto err1; 784 785 WARN_ON(hose->dn->data); 786 hose->dn->data = pcie; 787 hose->ops = &mpc83xx_pcie_ops; 788 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; 789 790 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); 791 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); 792 793 if (fsl_pcie_check_link(hose)) 794 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 795 796 return 0; 797 err1: 798 iounmap(pcie->cfg_type0); 799 err0: 800 kfree(pcie); 801 return ret; 802 803 } 804 805 int __init mpc83xx_add_bridge(struct device_node *dev) 806 { 807 int ret; 808 int len; 809 struct pci_controller *hose; 810 struct resource rsrc_reg; 811 struct resource rsrc_cfg; 812 const int *bus_range; 813 int primary; 814 815 is_mpc83xx_pci = 1; 816 817 if (!of_device_is_available(dev)) { 818 pr_warn("%pOF: disabled by the firmware.\n", 819 dev); 820 return -ENODEV; 821 } 822 pr_debug("Adding PCI host bridge %pOF\n", dev); 823 824 /* Fetch host bridge registers address */ 825 if (of_address_to_resource(dev, 0, &rsrc_reg)) { 826 printk(KERN_WARNING "Can't get pci register base!\n"); 827 return -ENOMEM; 828 } 829 830 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg)); 831 832 if (of_address_to_resource(dev, 1, &rsrc_cfg)) { 833 printk(KERN_WARNING 834 "No pci config register base in dev tree, " 835 "using default\n"); 836 /* 837 * MPC83xx supports up to two host controllers 838 * one at 0x8500 has config space registers at 0x8300 839 * one at 0x8600 has config space registers at 0x8380 840 */ 841 if ((rsrc_reg.start & 0xfffff) == 0x8500) 842 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300; 843 else if ((rsrc_reg.start & 0xfffff) == 0x8600) 844 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380; 845 } 846 /* 847 * Controller at offset 0x8500 is primary 848 */ 849 if ((rsrc_reg.start & 0xfffff) == 0x8500) 850 primary = 1; 851 else 852 primary = 0; 853 854 /* Get bus range if any */ 855 bus_range = of_get_property(dev, "bus-range", &len); 856 if (bus_range == NULL || len < 2 * sizeof(int)) { 857 printk(KERN_WARNING "Can't get bus-range for %pOF, assume" 858 " bus 0\n", dev); 859 } 860 861 pci_add_flags(PCI_REASSIGN_ALL_BUS); 862 hose = pcibios_alloc_controller(dev); 863 if (!hose) 864 return -ENOMEM; 865 866 hose->first_busno = bus_range ? bus_range[0] : 0; 867 hose->last_busno = bus_range ? bus_range[1] : 0xff; 868 869 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { 870 ret = mpc83xx_pcie_setup(hose, &rsrc_reg); 871 if (ret) 872 goto err0; 873 } else { 874 setup_indirect_pci(hose, rsrc_cfg.start, 875 rsrc_cfg.start + 4, 0); 876 } 877 878 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 879 "Firmware bus number: %d->%d\n", 880 (unsigned long long)rsrc_reg.start, hose->first_busno, 881 hose->last_busno); 882 883 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 884 hose, hose->cfg_addr, hose->cfg_data); 885 886 /* Interpret the "ranges" property */ 887 /* This also maps the I/O region and sets isa_io/mem_base */ 888 pci_process_bridge_OF_ranges(hose, dev, primary); 889 890 return 0; 891 err0: 892 pcibios_free_controller(hose); 893 return ret; 894 } 895 #endif /* CONFIG_PPC_83xx */ 896 897 u64 fsl_pci_immrbar_base(struct pci_controller *hose) 898 { 899 #ifdef CONFIG_PPC_83xx 900 if (is_mpc83xx_pci) { 901 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 902 struct pex_inbound_window *in; 903 int i; 904 905 /* Walk the Root Complex Inbound windows to match IMMR base */ 906 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE; 907 for (i = 0; i < 4; i++) { 908 /* not enabled, skip */ 909 if (!(in_le32(&in[i].ar) & PEX_RCIWARn_EN)) 910 continue; 911 912 if (get_immrbase() == in_le32(&in[i].tar)) 913 return (u64)in_le32(&in[i].barh) << 32 | 914 in_le32(&in[i].barl); 915 } 916 917 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n"); 918 } 919 #endif 920 921 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 922 if (!is_mpc83xx_pci) { 923 u32 base; 924 925 pci_bus_read_config_dword(hose->bus, 926 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); 927 928 /* 929 * For PEXCSRBAR, bit 3-0 indicate prefetchable and 930 * address type. So when getting base address, these 931 * bits should be masked 932 */ 933 base &= PCI_BASE_ADDRESS_MEM_MASK; 934 935 return base; 936 } 937 #endif 938 939 return 0; 940 } 941 942 #ifdef CONFIG_E500 943 static int mcheck_handle_load(struct pt_regs *regs, u32 inst) 944 { 945 unsigned int rd, ra, rb, d; 946 947 rd = get_rt(inst); 948 ra = get_ra(inst); 949 rb = get_rb(inst); 950 d = get_d(inst); 951 952 switch (get_op(inst)) { 953 case 31: 954 switch (get_xop(inst)) { 955 case OP_31_XOP_LWZX: 956 case OP_31_XOP_LWBRX: 957 regs->gpr[rd] = 0xffffffff; 958 break; 959 960 case OP_31_XOP_LWZUX: 961 regs->gpr[rd] = 0xffffffff; 962 regs->gpr[ra] += regs->gpr[rb]; 963 break; 964 965 case OP_31_XOP_LBZX: 966 regs->gpr[rd] = 0xff; 967 break; 968 969 case OP_31_XOP_LBZUX: 970 regs->gpr[rd] = 0xff; 971 regs->gpr[ra] += regs->gpr[rb]; 972 break; 973 974 case OP_31_XOP_LHZX: 975 case OP_31_XOP_LHBRX: 976 regs->gpr[rd] = 0xffff; 977 break; 978 979 case OP_31_XOP_LHZUX: 980 regs->gpr[rd] = 0xffff; 981 regs->gpr[ra] += regs->gpr[rb]; 982 break; 983 984 case OP_31_XOP_LHAX: 985 regs->gpr[rd] = ~0UL; 986 break; 987 988 case OP_31_XOP_LHAUX: 989 regs->gpr[rd] = ~0UL; 990 regs->gpr[ra] += regs->gpr[rb]; 991 break; 992 993 default: 994 return 0; 995 } 996 break; 997 998 case OP_LWZ: 999 regs->gpr[rd] = 0xffffffff; 1000 break; 1001 1002 case OP_LWZU: 1003 regs->gpr[rd] = 0xffffffff; 1004 regs->gpr[ra] += (s16)d; 1005 break; 1006 1007 case OP_LBZ: 1008 regs->gpr[rd] = 0xff; 1009 break; 1010 1011 case OP_LBZU: 1012 regs->gpr[rd] = 0xff; 1013 regs->gpr[ra] += (s16)d; 1014 break; 1015 1016 case OP_LHZ: 1017 regs->gpr[rd] = 0xffff; 1018 break; 1019 1020 case OP_LHZU: 1021 regs->gpr[rd] = 0xffff; 1022 regs->gpr[ra] += (s16)d; 1023 break; 1024 1025 case OP_LHA: 1026 regs->gpr[rd] = ~0UL; 1027 break; 1028 1029 case OP_LHAU: 1030 regs->gpr[rd] = ~0UL; 1031 regs->gpr[ra] += (s16)d; 1032 break; 1033 1034 default: 1035 return 0; 1036 } 1037 1038 return 1; 1039 } 1040 1041 static int is_in_pci_mem_space(phys_addr_t addr) 1042 { 1043 struct pci_controller *hose; 1044 struct resource *res; 1045 int i; 1046 1047 list_for_each_entry(hose, &hose_list, list_node) { 1048 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)) 1049 continue; 1050 1051 for (i = 0; i < 3; i++) { 1052 res = &hose->mem_resources[i]; 1053 if ((res->flags & IORESOURCE_MEM) && 1054 addr >= res->start && addr <= res->end) 1055 return 1; 1056 } 1057 } 1058 return 0; 1059 } 1060 1061 int fsl_pci_mcheck_exception(struct pt_regs *regs) 1062 { 1063 u32 inst; 1064 int ret; 1065 phys_addr_t addr = 0; 1066 1067 /* Let KVM/QEMU deal with the exception */ 1068 if (regs->msr & MSR_GS) 1069 return 0; 1070 1071 #ifdef CONFIG_PHYS_64BIT 1072 addr = mfspr(SPRN_MCARU); 1073 addr <<= 32; 1074 #endif 1075 addr += mfspr(SPRN_MCAR); 1076 1077 if (is_in_pci_mem_space(addr)) { 1078 if (user_mode(regs)) 1079 ret = copy_from_user_nofault(&inst, 1080 (void __user *)regs->nip, sizeof(inst)); 1081 else 1082 ret = get_kernel_nofault(inst, (void *)regs->nip); 1083 1084 if (!ret && mcheck_handle_load(regs, inst)) { 1085 regs_add_return_ip(regs, 4); 1086 return 1; 1087 } 1088 } 1089 1090 return 0; 1091 } 1092 #endif 1093 1094 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 1095 static const struct of_device_id pci_ids[] = { 1096 { .compatible = "fsl,mpc8540-pci", }, 1097 { .compatible = "fsl,mpc8548-pcie", }, 1098 { .compatible = "fsl,mpc8610-pci", }, 1099 { .compatible = "fsl,mpc8641-pcie", }, 1100 { .compatible = "fsl,qoriq-pcie", }, 1101 { .compatible = "fsl,qoriq-pcie-v2.1", }, 1102 { .compatible = "fsl,qoriq-pcie-v2.2", }, 1103 { .compatible = "fsl,qoriq-pcie-v2.3", }, 1104 { .compatible = "fsl,qoriq-pcie-v2.4", }, 1105 { .compatible = "fsl,qoriq-pcie-v3.0", }, 1106 1107 /* 1108 * The following entries are for compatibility with older device 1109 * trees. 1110 */ 1111 { .compatible = "fsl,p1022-pcie", }, 1112 { .compatible = "fsl,p4080-pcie", }, 1113 1114 {}, 1115 }; 1116 1117 struct device_node *fsl_pci_primary; 1118 1119 void __init fsl_pci_assign_primary(void) 1120 { 1121 struct device_node *np; 1122 1123 /* Callers can specify the primary bus using other means. */ 1124 if (fsl_pci_primary) 1125 return; 1126 1127 /* If a PCI host bridge contains an ISA node, it's primary. */ 1128 np = of_find_node_by_type(NULL, "isa"); 1129 while ((fsl_pci_primary = of_get_parent(np))) { 1130 of_node_put(np); 1131 np = fsl_pci_primary; 1132 1133 if (of_match_node(pci_ids, np) && of_device_is_available(np)) 1134 return; 1135 } 1136 1137 /* 1138 * If there's no PCI host bridge with ISA, arbitrarily 1139 * designate one as primary. This can go away once 1140 * various bugs with primary-less systems are fixed. 1141 */ 1142 for_each_matching_node(np, pci_ids) { 1143 if (of_device_is_available(np)) { 1144 fsl_pci_primary = np; 1145 of_node_put(np); 1146 return; 1147 } 1148 } 1149 } 1150 1151 #ifdef CONFIG_PM_SLEEP 1152 static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id) 1153 { 1154 struct pci_controller *hose = dev_id; 1155 struct ccsr_pci __iomem *pci = hose->private_data; 1156 u32 dr; 1157 1158 dr = in_be32(&pci->pex_pme_mes_dr); 1159 if (!dr) 1160 return IRQ_NONE; 1161 1162 out_be32(&pci->pex_pme_mes_dr, dr); 1163 1164 return IRQ_HANDLED; 1165 } 1166 1167 static int fsl_pci_pme_probe(struct pci_controller *hose) 1168 { 1169 struct ccsr_pci __iomem *pci; 1170 struct pci_dev *dev; 1171 int pme_irq; 1172 int res; 1173 u16 pms; 1174 1175 /* Get hose's pci_dev */ 1176 dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list); 1177 1178 /* PME Disable */ 1179 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); 1180 pms &= ~PCI_PM_CTRL_PME_ENABLE; 1181 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); 1182 1183 pme_irq = irq_of_parse_and_map(hose->dn, 0); 1184 if (!pme_irq) { 1185 dev_err(&dev->dev, "Failed to map PME interrupt.\n"); 1186 1187 return -ENXIO; 1188 } 1189 1190 res = devm_request_irq(hose->parent, pme_irq, 1191 fsl_pci_pme_handle, 1192 IRQF_SHARED, 1193 "[PCI] PME", hose); 1194 if (res < 0) { 1195 dev_err(&dev->dev, "Unable to request irq %d for PME\n", pme_irq); 1196 irq_dispose_mapping(pme_irq); 1197 1198 return -ENODEV; 1199 } 1200 1201 pci = hose->private_data; 1202 1203 /* Enable PTOD, ENL23D & EXL23D */ 1204 clrbits32(&pci->pex_pme_mes_disr, 1205 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); 1206 1207 out_be32(&pci->pex_pme_mes_ier, 0); 1208 setbits32(&pci->pex_pme_mes_ier, 1209 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); 1210 1211 /* PME Enable */ 1212 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); 1213 pms |= PCI_PM_CTRL_PME_ENABLE; 1214 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); 1215 1216 return 0; 1217 } 1218 1219 static void send_pme_turnoff_message(struct pci_controller *hose) 1220 { 1221 struct ccsr_pci __iomem *pci = hose->private_data; 1222 u32 dr; 1223 int i; 1224 1225 /* Send PME_Turn_Off Message Request */ 1226 setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR); 1227 1228 /* Wait trun off done */ 1229 for (i = 0; i < 150; i++) { 1230 dr = in_be32(&pci->pex_pme_mes_dr); 1231 if (dr) { 1232 out_be32(&pci->pex_pme_mes_dr, dr); 1233 break; 1234 } 1235 1236 udelay(1000); 1237 } 1238 } 1239 1240 static void fsl_pci_syscore_do_suspend(struct pci_controller *hose) 1241 { 1242 send_pme_turnoff_message(hose); 1243 } 1244 1245 static int fsl_pci_syscore_suspend(void) 1246 { 1247 struct pci_controller *hose, *tmp; 1248 1249 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 1250 fsl_pci_syscore_do_suspend(hose); 1251 1252 return 0; 1253 } 1254 1255 static void fsl_pci_syscore_do_resume(struct pci_controller *hose) 1256 { 1257 struct ccsr_pci __iomem *pci = hose->private_data; 1258 u32 dr; 1259 int i; 1260 1261 /* Send Exit L2 State Message */ 1262 setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S); 1263 1264 /* Wait exit done */ 1265 for (i = 0; i < 150; i++) { 1266 dr = in_be32(&pci->pex_pme_mes_dr); 1267 if (dr) { 1268 out_be32(&pci->pex_pme_mes_dr, dr); 1269 break; 1270 } 1271 1272 udelay(1000); 1273 } 1274 1275 setup_pci_atmu(hose); 1276 } 1277 1278 static void fsl_pci_syscore_resume(void) 1279 { 1280 struct pci_controller *hose, *tmp; 1281 1282 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 1283 fsl_pci_syscore_do_resume(hose); 1284 } 1285 1286 static struct syscore_ops pci_syscore_pm_ops = { 1287 .suspend = fsl_pci_syscore_suspend, 1288 .resume = fsl_pci_syscore_resume, 1289 }; 1290 #endif 1291 1292 void fsl_pcibios_fixup_phb(struct pci_controller *phb) 1293 { 1294 #ifdef CONFIG_PM_SLEEP 1295 fsl_pci_pme_probe(phb); 1296 #endif 1297 } 1298 1299 static int add_err_dev(struct platform_device *pdev) 1300 { 1301 struct platform_device *errdev; 1302 struct mpc85xx_edac_pci_plat_data pd = { 1303 .of_node = pdev->dev.of_node 1304 }; 1305 1306 errdev = platform_device_register_resndata(&pdev->dev, 1307 "mpc85xx-pci-edac", 1308 PLATFORM_DEVID_AUTO, 1309 pdev->resource, 1310 pdev->num_resources, 1311 &pd, sizeof(pd)); 1312 1313 return PTR_ERR_OR_ZERO(errdev); 1314 } 1315 1316 static int fsl_pci_probe(struct platform_device *pdev) 1317 { 1318 struct device_node *node; 1319 int ret; 1320 1321 node = pdev->dev.of_node; 1322 ret = fsl_add_bridge(pdev, fsl_pci_primary == node); 1323 if (ret) 1324 return ret; 1325 1326 ret = add_err_dev(pdev); 1327 if (ret) 1328 dev_err(&pdev->dev, "couldn't register error device: %d\n", 1329 ret); 1330 1331 return 0; 1332 } 1333 1334 static struct platform_driver fsl_pci_driver = { 1335 .driver = { 1336 .name = "fsl-pci", 1337 .of_match_table = pci_ids, 1338 }, 1339 .probe = fsl_pci_probe, 1340 }; 1341 1342 static int __init fsl_pci_init(void) 1343 { 1344 #ifdef CONFIG_PM_SLEEP 1345 register_syscore_ops(&pci_syscore_pm_ops); 1346 #endif 1347 return platform_driver_register(&fsl_pci_driver); 1348 } 1349 arch_initcall(fsl_pci_init); 1350 #endif 1351