1 /* 2 * MPC83xx/85xx/86xx PCI/PCIE support routing. 3 * 4 * Copyright 2007-2012 Freescale Semiconductor, Inc. 5 * Copyright 2008-2009 MontaVista Software, Inc. 6 * 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 8 * Recode: ZHANG WEI <wei.zhang@freescale.com> 9 * Rewrite the routing for Frescale PCI and PCI Express 10 * Roy Zang <tie-fei.zang@freescale.com> 11 * MPC83xx PCI-Express support: 12 * Tony Li <tony.li@freescale.com> 13 * Anton Vorontsov <avorontsov@ru.mvista.com> 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 */ 20 #include <linux/kernel.h> 21 #include <linux/pci.h> 22 #include <linux/delay.h> 23 #include <linux/string.h> 24 #include <linux/init.h> 25 #include <linux/interrupt.h> 26 #include <linux/memblock.h> 27 #include <linux/log2.h> 28 #include <linux/slab.h> 29 #include <linux/suspend.h> 30 #include <linux/syscore_ops.h> 31 #include <linux/uaccess.h> 32 33 #include <asm/io.h> 34 #include <asm/prom.h> 35 #include <asm/pci-bridge.h> 36 #include <asm/ppc-pci.h> 37 #include <asm/machdep.h> 38 #include <asm/disassemble.h> 39 #include <asm/ppc-opcode.h> 40 #include <sysdev/fsl_soc.h> 41 #include <sysdev/fsl_pci.h> 42 43 static int fsl_pcie_bus_fixup, is_mpc83xx_pci; 44 45 static void quirk_fsl_pcie_early(struct pci_dev *dev) 46 { 47 u8 hdr_type; 48 49 /* if we aren't a PCIe don't bother */ 50 if (!pci_is_pcie(dev)) 51 return; 52 53 /* if we aren't in host mode don't bother */ 54 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 55 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) 56 return; 57 58 dev->class = PCI_CLASS_BRIDGE_PCI << 8; 59 fsl_pcie_bus_fixup = 1; 60 return; 61 } 62 63 static int fsl_indirect_read_config(struct pci_bus *, unsigned int, 64 int, int, u32 *); 65 66 static int fsl_pcie_check_link(struct pci_controller *hose) 67 { 68 u32 val = 0; 69 70 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { 71 if (hose->ops->read == fsl_indirect_read_config) 72 __indirect_read_config(hose, hose->first_busno, 0, 73 PCIE_LTSSM, 4, &val); 74 else 75 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); 76 if (val < PCIE_LTSSM_L0) 77 return 1; 78 } else { 79 struct ccsr_pci __iomem *pci = hose->private_data; 80 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */ 81 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) 82 >> PEX_CSR0_LTSSM_SHIFT; 83 if (val != PEX_CSR0_LTSSM_L0) 84 return 1; 85 } 86 87 return 0; 88 } 89 90 static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn, 91 int offset, int len, u32 *val) 92 { 93 struct pci_controller *hose = pci_bus_to_host(bus); 94 95 if (fsl_pcie_check_link(hose)) 96 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 97 else 98 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; 99 100 return indirect_read_config(bus, devfn, offset, len, val); 101 } 102 103 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 104 105 static struct pci_ops fsl_indirect_pcie_ops = 106 { 107 .read = fsl_indirect_read_config, 108 .write = indirect_write_config, 109 }; 110 111 #define MAX_PHYS_ADDR_BITS 40 112 static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS; 113 114 #ifdef CONFIG_SWIOTLB 115 static void setup_swiotlb_ops(struct pci_controller *hose) 116 { 117 if (ppc_swiotlb_enable) { 118 hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb; 119 set_pci_dma_ops(&swiotlb_dma_ops); 120 } 121 } 122 #else 123 static inline void setup_swiotlb_ops(struct pci_controller *hose) {} 124 #endif 125 126 static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask) 127 { 128 if (!dev->dma_mask || !dma_supported(dev, dma_mask)) 129 return -EIO; 130 131 /* 132 * Fixup PCI devices that are able to DMA to above the physical 133 * address width of the SoC such that we can address any internal 134 * SoC address from across PCI if needed 135 */ 136 if ((dev_is_pci(dev)) && 137 dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) { 138 set_dma_ops(dev, &dma_direct_ops); 139 set_dma_offset(dev, pci64_dma_offset); 140 } 141 142 *dev->dma_mask = dma_mask; 143 return 0; 144 } 145 146 static int setup_one_atmu(struct ccsr_pci __iomem *pci, 147 unsigned int index, const struct resource *res, 148 resource_size_t offset) 149 { 150 resource_size_t pci_addr = res->start - offset; 151 resource_size_t phys_addr = res->start; 152 resource_size_t size = resource_size(res); 153 u32 flags = 0x80044000; /* enable & mem R/W */ 154 unsigned int i; 155 156 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", 157 (u64)res->start, (u64)size); 158 159 if (res->flags & IORESOURCE_PREFETCH) 160 flags |= 0x10000000; /* enable relaxed ordering */ 161 162 for (i = 0; size > 0; i++) { 163 unsigned int bits = min_t(u32, ilog2(size), 164 __ffs(pci_addr | phys_addr)); 165 166 if (index + i >= 5) 167 return -1; 168 169 out_be32(&pci->pow[index + i].potar, pci_addr >> 12); 170 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); 171 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); 172 out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); 173 174 pci_addr += (resource_size_t)1U << bits; 175 phys_addr += (resource_size_t)1U << bits; 176 size -= (resource_size_t)1U << bits; 177 } 178 179 return i; 180 } 181 182 static bool is_kdump(void) 183 { 184 struct device_node *node; 185 186 node = of_find_node_by_type(NULL, "memory"); 187 if (!node) { 188 WARN_ON_ONCE(1); 189 return false; 190 } 191 192 return of_property_read_bool(node, "linux,usable-memory"); 193 } 194 195 /* atmu setup for fsl pci/pcie controller */ 196 static void setup_pci_atmu(struct pci_controller *hose) 197 { 198 struct ccsr_pci __iomem *pci = hose->private_data; 199 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4; 200 u64 mem, sz, paddr_hi = 0; 201 u64 offset = 0, paddr_lo = ULLONG_MAX; 202 u32 pcicsrbar = 0, pcicsrbar_sz; 203 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | 204 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 205 const char *name = hose->dn->full_name; 206 const u64 *reg; 207 int len; 208 bool setup_inbound; 209 210 /* 211 * If this is kdump, we don't want to trigger a bunch of PCI 212 * errors by closing the window on in-flight DMA. 213 * 214 * We still run most of the function's logic so that things like 215 * hose->dma_window_size still get set. 216 */ 217 setup_inbound = !is_kdump(); 218 219 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 220 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) { 221 win_idx = 2; 222 start_idx = 0; 223 end_idx = 3; 224 } 225 } 226 227 /* Disable all windows (except powar0 since it's ignored) */ 228 for(i = 1; i < 5; i++) 229 out_be32(&pci->pow[i].powar, 0); 230 231 if (setup_inbound) { 232 for (i = start_idx; i < end_idx; i++) 233 out_be32(&pci->piw[i].piwar, 0); 234 } 235 236 /* Setup outbound MEM window */ 237 for(i = 0, j = 1; i < 3; i++) { 238 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) 239 continue; 240 241 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); 242 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); 243 244 /* We assume all memory resources have the same offset */ 245 offset = hose->mem_offset[i]; 246 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset); 247 248 if (n < 0 || j >= 5) { 249 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i); 250 hose->mem_resources[i].flags |= IORESOURCE_DISABLED; 251 } else 252 j += n; 253 } 254 255 /* Setup outbound IO window */ 256 if (hose->io_resource.flags & IORESOURCE_IO) { 257 if (j >= 5) { 258 pr_err("Ran out of outbound PCI ATMUs for IO resource\n"); 259 } else { 260 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " 261 "phy base 0x%016llx.\n", 262 (u64)hose->io_resource.start, 263 (u64)resource_size(&hose->io_resource), 264 (u64)hose->io_base_phys); 265 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); 266 out_be32(&pci->pow[j].potear, 0); 267 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); 268 /* Enable, IO R/W */ 269 out_be32(&pci->pow[j].powar, 0x80088000 270 | (ilog2(hose->io_resource.end 271 - hose->io_resource.start + 1) - 1)); 272 } 273 } 274 275 /* convert to pci address space */ 276 paddr_hi -= offset; 277 paddr_lo -= offset; 278 279 if (paddr_hi == paddr_lo) { 280 pr_err("%s: No outbound window space\n", name); 281 return; 282 } 283 284 if (paddr_lo == 0) { 285 pr_err("%s: No space for inbound window\n", name); 286 return; 287 } 288 289 /* setup PCSRBAR/PEXCSRBAR */ 290 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff); 291 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 292 pcicsrbar_sz = ~pcicsrbar_sz + 1; 293 294 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || 295 (paddr_lo > 0x100000000ull)) 296 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 297 else 298 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; 299 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar); 300 301 paddr_lo = min(paddr_lo, (u64)pcicsrbar); 302 303 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar); 304 305 /* Setup inbound mem window */ 306 mem = memblock_end_of_DRAM(); 307 pr_info("%s: end of DRAM %llx\n", __func__, mem); 308 309 /* 310 * The msi-address-64 property, if it exists, indicates the physical 311 * address of the MSIIR register. Normally, this register is located 312 * inside CCSR, so the ATMU that covers all of CCSR is used. But if 313 * this property exists, then we normally need to create a new ATMU 314 * for it. For now, however, we cheat. The only entity that creates 315 * this property is the Freescale hypervisor, and the address is 316 * specified in the partition configuration. Typically, the address 317 * is located in the page immediately after the end of DDR. If so, we 318 * can avoid allocating a new ATMU by extending the DDR ATMU by one 319 * page. 320 */ 321 reg = of_get_property(hose->dn, "msi-address-64", &len); 322 if (reg && (len == sizeof(u64))) { 323 u64 address = be64_to_cpup(reg); 324 325 if ((address >= mem) && (address < (mem + PAGE_SIZE))) { 326 pr_info("%s: extending DDR ATMU to cover MSIIR", name); 327 mem += PAGE_SIZE; 328 } else { 329 /* TODO: Create a new ATMU for MSIIR */ 330 pr_warn("%s: msi-address-64 address of %llx is " 331 "unsupported\n", name, address); 332 } 333 } 334 335 sz = min(mem, paddr_lo); 336 mem_log = ilog2(sz); 337 338 /* PCIe can overmap inbound & outbound since RX & TX are separated */ 339 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 340 /* Size window to exact size if power-of-two or one size up */ 341 if ((1ull << mem_log) != mem) { 342 mem_log++; 343 if ((1ull << mem_log) > mem) 344 pr_info("%s: Setting PCI inbound window " 345 "greater than memory size\n", name); 346 } 347 348 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK); 349 350 if (setup_inbound) { 351 /* Setup inbound memory window */ 352 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 353 out_be32(&pci->piw[win_idx].piwbar, 0x00000000); 354 out_be32(&pci->piw[win_idx].piwar, piwar); 355 } 356 357 win_idx--; 358 hose->dma_window_base_cur = 0x00000000; 359 hose->dma_window_size = (resource_size_t)sz; 360 361 /* 362 * if we have >4G of memory setup second PCI inbound window to 363 * let devices that are 64-bit address capable to work w/o 364 * SWIOTLB and access the full range of memory 365 */ 366 if (sz != mem) { 367 mem_log = ilog2(mem); 368 369 /* Size window up if we dont fit in exact power-of-2 */ 370 if ((1ull << mem_log) != mem) 371 mem_log++; 372 373 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1); 374 375 if (setup_inbound) { 376 /* Setup inbound memory window */ 377 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 378 out_be32(&pci->piw[win_idx].piwbear, 379 pci64_dma_offset >> 44); 380 out_be32(&pci->piw[win_idx].piwbar, 381 pci64_dma_offset >> 12); 382 out_be32(&pci->piw[win_idx].piwar, piwar); 383 } 384 385 /* 386 * install our own dma_set_mask handler to fixup dma_ops 387 * and dma_offset 388 */ 389 ppc_md.dma_set_mask = fsl_pci_dma_set_mask; 390 391 pr_info("%s: Setup 64-bit PCI DMA window\n", name); 392 } 393 } else { 394 u64 paddr = 0; 395 396 if (setup_inbound) { 397 /* Setup inbound memory window */ 398 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 399 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); 400 out_be32(&pci->piw[win_idx].piwar, 401 (piwar | (mem_log - 1))); 402 } 403 404 win_idx--; 405 paddr += 1ull << mem_log; 406 sz -= 1ull << mem_log; 407 408 if (sz) { 409 mem_log = ilog2(sz); 410 piwar |= (mem_log - 1); 411 412 if (setup_inbound) { 413 out_be32(&pci->piw[win_idx].pitar, 414 paddr >> 12); 415 out_be32(&pci->piw[win_idx].piwbar, 416 paddr >> 12); 417 out_be32(&pci->piw[win_idx].piwar, piwar); 418 } 419 420 win_idx--; 421 paddr += 1ull << mem_log; 422 } 423 424 hose->dma_window_base_cur = 0x00000000; 425 hose->dma_window_size = (resource_size_t)paddr; 426 } 427 428 if (hose->dma_window_size < mem) { 429 #ifdef CONFIG_SWIOTLB 430 ppc_swiotlb_enable = 1; 431 #else 432 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to " 433 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", 434 name); 435 #endif 436 /* adjusting outbound windows could reclaim space in mem map */ 437 if (paddr_hi < 0xffffffffull) 438 pr_warning("%s: WARNING: Outbound window cfg leaves " 439 "gaps in memory map. Adjusting the memory map " 440 "could reduce unnecessary bounce buffering.\n", 441 name); 442 443 pr_info("%s: DMA window size is 0x%llx\n", name, 444 (u64)hose->dma_window_size); 445 } 446 } 447 448 static void __init setup_pci_cmd(struct pci_controller *hose) 449 { 450 u16 cmd; 451 int cap_x; 452 453 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); 454 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY 455 | PCI_COMMAND_IO; 456 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); 457 458 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); 459 if (cap_x) { 460 int pci_x_cmd = cap_x + PCI_X_CMD; 461 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 462 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 463 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); 464 } else { 465 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); 466 } 467 } 468 469 void fsl_pcibios_fixup_bus(struct pci_bus *bus) 470 { 471 struct pci_controller *hose = pci_bus_to_host(bus); 472 int i, is_pcie = 0, no_link; 473 474 /* The root complex bridge comes up with bogus resources, 475 * we copy the PHB ones in. 476 * 477 * With the current generic PCI code, the PHB bus no longer 478 * has bus->resource[0..4] set, so things are a bit more 479 * tricky. 480 */ 481 482 if (fsl_pcie_bus_fixup) 483 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP); 484 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK); 485 486 if (bus->parent == hose->bus && (is_pcie || no_link)) { 487 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) { 488 struct resource *res = bus->resource[i]; 489 struct resource *par; 490 491 if (!res) 492 continue; 493 if (i == 0) 494 par = &hose->io_resource; 495 else if (i < 4) 496 par = &hose->mem_resources[i-1]; 497 else par = NULL; 498 499 res->start = par ? par->start : 0; 500 res->end = par ? par->end : 0; 501 res->flags = par ? par->flags : 0; 502 } 503 } 504 } 505 506 int fsl_add_bridge(struct platform_device *pdev, int is_primary) 507 { 508 int len; 509 struct pci_controller *hose; 510 struct resource rsrc; 511 const int *bus_range; 512 u8 hdr_type, progif; 513 struct device_node *dev; 514 struct ccsr_pci __iomem *pci; 515 516 dev = pdev->dev.of_node; 517 518 if (!of_device_is_available(dev)) { 519 pr_warning("%s: disabled\n", dev->full_name); 520 return -ENODEV; 521 } 522 523 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 524 525 /* Fetch host bridge registers address */ 526 if (of_address_to_resource(dev, 0, &rsrc)) { 527 printk(KERN_WARNING "Can't get pci register base!"); 528 return -ENOMEM; 529 } 530 531 /* Get bus range if any */ 532 bus_range = of_get_property(dev, "bus-range", &len); 533 if (bus_range == NULL || len < 2 * sizeof(int)) 534 printk(KERN_WARNING "Can't get bus-range for %s, assume" 535 " bus 0\n", dev->full_name); 536 537 pci_add_flags(PCI_REASSIGN_ALL_BUS); 538 hose = pcibios_alloc_controller(dev); 539 if (!hose) 540 return -ENOMEM; 541 542 /* set platform device as the parent */ 543 hose->parent = &pdev->dev; 544 hose->first_busno = bus_range ? bus_range[0] : 0x0; 545 hose->last_busno = bus_range ? bus_range[1] : 0xff; 546 547 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", 548 (u64)rsrc.start, (u64)resource_size(&rsrc)); 549 550 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc)); 551 if (!hose->private_data) 552 goto no_bridge; 553 554 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, 555 PPC_INDIRECT_TYPE_BIG_ENDIAN); 556 557 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) 558 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; 559 560 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 561 /* use fsl_indirect_read_config for PCIe */ 562 hose->ops = &fsl_indirect_pcie_ops; 563 /* For PCIE read HEADER_TYPE to identify controler mode */ 564 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type); 565 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) 566 goto no_bridge; 567 568 } else { 569 /* For PCI read PROG to identify controller mode */ 570 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif); 571 if ((progif & 1) && 572 !of_property_read_bool(dev, "fsl,pci-agent-force-enum")) 573 goto no_bridge; 574 } 575 576 setup_pci_cmd(hose); 577 578 /* check PCI express link status */ 579 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 580 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | 581 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; 582 if (fsl_pcie_check_link(hose)) 583 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 584 } 585 586 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 587 "Firmware bus number: %d->%d\n", 588 (unsigned long long)rsrc.start, hose->first_busno, 589 hose->last_busno); 590 591 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 592 hose, hose->cfg_addr, hose->cfg_data); 593 594 /* Interpret the "ranges" property */ 595 /* This also maps the I/O region and sets isa_io/mem_base */ 596 pci_process_bridge_OF_ranges(hose, dev, is_primary); 597 598 /* Setup PEX window registers */ 599 setup_pci_atmu(hose); 600 601 /* Set up controller operations */ 602 setup_swiotlb_ops(hose); 603 604 return 0; 605 606 no_bridge: 607 iounmap(hose->private_data); 608 /* unmap cfg_data & cfg_addr separately if not on same page */ 609 if (((unsigned long)hose->cfg_data & PAGE_MASK) != 610 ((unsigned long)hose->cfg_addr & PAGE_MASK)) 611 iounmap(hose->cfg_data); 612 iounmap(hose->cfg_addr); 613 pcibios_free_controller(hose); 614 return -ENODEV; 615 } 616 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ 617 618 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, 619 quirk_fsl_pcie_early); 620 621 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) 622 struct mpc83xx_pcie_priv { 623 void __iomem *cfg_type0; 624 void __iomem *cfg_type1; 625 u32 dev_base; 626 }; 627 628 struct pex_inbound_window { 629 u32 ar; 630 u32 tar; 631 u32 barl; 632 u32 barh; 633 }; 634 635 /* 636 * With the convention of u-boot, the PCIE outbound window 0 serves 637 * as configuration transactions outbound. 638 */ 639 #define PEX_OUTWIN0_BAR 0xCA4 640 #define PEX_OUTWIN0_TAL 0xCA8 641 #define PEX_OUTWIN0_TAH 0xCAC 642 #define PEX_RC_INWIN_BASE 0xE60 643 #define PEX_RCIWARn_EN 0x1 644 645 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) 646 { 647 struct pci_controller *hose = pci_bus_to_host(bus); 648 649 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) 650 return PCIBIOS_DEVICE_NOT_FOUND; 651 /* 652 * Workaround for the HW bug: for Type 0 configure transactions the 653 * PCI-E controller does not check the device number bits and just 654 * assumes that the device number bits are 0. 655 */ 656 if (bus->number == hose->first_busno || 657 bus->primary == hose->first_busno) { 658 if (devfn & 0xf8) 659 return PCIBIOS_DEVICE_NOT_FOUND; 660 } 661 662 if (ppc_md.pci_exclude_device) { 663 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 664 return PCIBIOS_DEVICE_NOT_FOUND; 665 } 666 667 return PCIBIOS_SUCCESSFUL; 668 } 669 670 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, 671 unsigned int devfn, int offset) 672 { 673 struct pci_controller *hose = pci_bus_to_host(bus); 674 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 675 u32 dev_base = bus->number << 24 | devfn << 16; 676 int ret; 677 678 ret = mpc83xx_pcie_exclude_device(bus, devfn); 679 if (ret) 680 return NULL; 681 682 offset &= 0xfff; 683 684 /* Type 0 */ 685 if (bus->number == hose->first_busno) 686 return pcie->cfg_type0 + offset; 687 688 if (pcie->dev_base == dev_base) 689 goto mapped; 690 691 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); 692 693 pcie->dev_base = dev_base; 694 mapped: 695 return pcie->cfg_type1 + offset; 696 } 697 698 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 699 int offset, int len, u32 val) 700 { 701 struct pci_controller *hose = pci_bus_to_host(bus); 702 703 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */ 704 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno) 705 val &= 0xffffff00; 706 707 return pci_generic_config_write(bus, devfn, offset, len, val); 708 } 709 710 static struct pci_ops mpc83xx_pcie_ops = { 711 .map_bus = mpc83xx_pcie_remap_cfg, 712 .read = pci_generic_config_read, 713 .write = mpc83xx_pcie_write_config, 714 }; 715 716 static int __init mpc83xx_pcie_setup(struct pci_controller *hose, 717 struct resource *reg) 718 { 719 struct mpc83xx_pcie_priv *pcie; 720 u32 cfg_bar; 721 int ret = -ENOMEM; 722 723 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); 724 if (!pcie) 725 return ret; 726 727 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); 728 if (!pcie->cfg_type0) 729 goto err0; 730 731 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); 732 if (!cfg_bar) { 733 /* PCI-E isn't configured. */ 734 ret = -ENODEV; 735 goto err1; 736 } 737 738 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); 739 if (!pcie->cfg_type1) 740 goto err1; 741 742 WARN_ON(hose->dn->data); 743 hose->dn->data = pcie; 744 hose->ops = &mpc83xx_pcie_ops; 745 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; 746 747 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); 748 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); 749 750 if (fsl_pcie_check_link(hose)) 751 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 752 753 return 0; 754 err1: 755 iounmap(pcie->cfg_type0); 756 err0: 757 kfree(pcie); 758 return ret; 759 760 } 761 762 int __init mpc83xx_add_bridge(struct device_node *dev) 763 { 764 int ret; 765 int len; 766 struct pci_controller *hose; 767 struct resource rsrc_reg; 768 struct resource rsrc_cfg; 769 const int *bus_range; 770 int primary; 771 772 is_mpc83xx_pci = 1; 773 774 if (!of_device_is_available(dev)) { 775 pr_warning("%s: disabled by the firmware.\n", 776 dev->full_name); 777 return -ENODEV; 778 } 779 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 780 781 /* Fetch host bridge registers address */ 782 if (of_address_to_resource(dev, 0, &rsrc_reg)) { 783 printk(KERN_WARNING "Can't get pci register base!\n"); 784 return -ENOMEM; 785 } 786 787 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg)); 788 789 if (of_address_to_resource(dev, 1, &rsrc_cfg)) { 790 printk(KERN_WARNING 791 "No pci config register base in dev tree, " 792 "using default\n"); 793 /* 794 * MPC83xx supports up to two host controllers 795 * one at 0x8500 has config space registers at 0x8300 796 * one at 0x8600 has config space registers at 0x8380 797 */ 798 if ((rsrc_reg.start & 0xfffff) == 0x8500) 799 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300; 800 else if ((rsrc_reg.start & 0xfffff) == 0x8600) 801 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380; 802 } 803 /* 804 * Controller at offset 0x8500 is primary 805 */ 806 if ((rsrc_reg.start & 0xfffff) == 0x8500) 807 primary = 1; 808 else 809 primary = 0; 810 811 /* Get bus range if any */ 812 bus_range = of_get_property(dev, "bus-range", &len); 813 if (bus_range == NULL || len < 2 * sizeof(int)) { 814 printk(KERN_WARNING "Can't get bus-range for %s, assume" 815 " bus 0\n", dev->full_name); 816 } 817 818 pci_add_flags(PCI_REASSIGN_ALL_BUS); 819 hose = pcibios_alloc_controller(dev); 820 if (!hose) 821 return -ENOMEM; 822 823 hose->first_busno = bus_range ? bus_range[0] : 0; 824 hose->last_busno = bus_range ? bus_range[1] : 0xff; 825 826 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { 827 ret = mpc83xx_pcie_setup(hose, &rsrc_reg); 828 if (ret) 829 goto err0; 830 } else { 831 setup_indirect_pci(hose, rsrc_cfg.start, 832 rsrc_cfg.start + 4, 0); 833 } 834 835 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 836 "Firmware bus number: %d->%d\n", 837 (unsigned long long)rsrc_reg.start, hose->first_busno, 838 hose->last_busno); 839 840 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 841 hose, hose->cfg_addr, hose->cfg_data); 842 843 /* Interpret the "ranges" property */ 844 /* This also maps the I/O region and sets isa_io/mem_base */ 845 pci_process_bridge_OF_ranges(hose, dev, primary); 846 847 return 0; 848 err0: 849 pcibios_free_controller(hose); 850 return ret; 851 } 852 #endif /* CONFIG_PPC_83xx */ 853 854 u64 fsl_pci_immrbar_base(struct pci_controller *hose) 855 { 856 #ifdef CONFIG_PPC_83xx 857 if (is_mpc83xx_pci) { 858 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 859 struct pex_inbound_window *in; 860 int i; 861 862 /* Walk the Root Complex Inbound windows to match IMMR base */ 863 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE; 864 for (i = 0; i < 4; i++) { 865 /* not enabled, skip */ 866 if (!(in_le32(&in[i].ar) & PEX_RCIWARn_EN)) 867 continue; 868 869 if (get_immrbase() == in_le32(&in[i].tar)) 870 return (u64)in_le32(&in[i].barh) << 32 | 871 in_le32(&in[i].barl); 872 } 873 874 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n"); 875 } 876 #endif 877 878 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 879 if (!is_mpc83xx_pci) { 880 u32 base; 881 882 pci_bus_read_config_dword(hose->bus, 883 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); 884 885 /* 886 * For PEXCSRBAR, bit 3-0 indicate prefetchable and 887 * address type. So when getting base address, these 888 * bits should be masked 889 */ 890 base &= PCI_BASE_ADDRESS_MEM_MASK; 891 892 return base; 893 } 894 #endif 895 896 return 0; 897 } 898 899 #ifdef CONFIG_E500 900 static int mcheck_handle_load(struct pt_regs *regs, u32 inst) 901 { 902 unsigned int rd, ra, rb, d; 903 904 rd = get_rt(inst); 905 ra = get_ra(inst); 906 rb = get_rb(inst); 907 d = get_d(inst); 908 909 switch (get_op(inst)) { 910 case 31: 911 switch (get_xop(inst)) { 912 case OP_31_XOP_LWZX: 913 case OP_31_XOP_LWBRX: 914 regs->gpr[rd] = 0xffffffff; 915 break; 916 917 case OP_31_XOP_LWZUX: 918 regs->gpr[rd] = 0xffffffff; 919 regs->gpr[ra] += regs->gpr[rb]; 920 break; 921 922 case OP_31_XOP_LBZX: 923 regs->gpr[rd] = 0xff; 924 break; 925 926 case OP_31_XOP_LBZUX: 927 regs->gpr[rd] = 0xff; 928 regs->gpr[ra] += regs->gpr[rb]; 929 break; 930 931 case OP_31_XOP_LHZX: 932 case OP_31_XOP_LHBRX: 933 regs->gpr[rd] = 0xffff; 934 break; 935 936 case OP_31_XOP_LHZUX: 937 regs->gpr[rd] = 0xffff; 938 regs->gpr[ra] += regs->gpr[rb]; 939 break; 940 941 case OP_31_XOP_LHAX: 942 regs->gpr[rd] = ~0UL; 943 break; 944 945 case OP_31_XOP_LHAUX: 946 regs->gpr[rd] = ~0UL; 947 regs->gpr[ra] += regs->gpr[rb]; 948 break; 949 950 default: 951 return 0; 952 } 953 break; 954 955 case OP_LWZ: 956 regs->gpr[rd] = 0xffffffff; 957 break; 958 959 case OP_LWZU: 960 regs->gpr[rd] = 0xffffffff; 961 regs->gpr[ra] += (s16)d; 962 break; 963 964 case OP_LBZ: 965 regs->gpr[rd] = 0xff; 966 break; 967 968 case OP_LBZU: 969 regs->gpr[rd] = 0xff; 970 regs->gpr[ra] += (s16)d; 971 break; 972 973 case OP_LHZ: 974 regs->gpr[rd] = 0xffff; 975 break; 976 977 case OP_LHZU: 978 regs->gpr[rd] = 0xffff; 979 regs->gpr[ra] += (s16)d; 980 break; 981 982 case OP_LHA: 983 regs->gpr[rd] = ~0UL; 984 break; 985 986 case OP_LHAU: 987 regs->gpr[rd] = ~0UL; 988 regs->gpr[ra] += (s16)d; 989 break; 990 991 default: 992 return 0; 993 } 994 995 return 1; 996 } 997 998 static int is_in_pci_mem_space(phys_addr_t addr) 999 { 1000 struct pci_controller *hose; 1001 struct resource *res; 1002 int i; 1003 1004 list_for_each_entry(hose, &hose_list, list_node) { 1005 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)) 1006 continue; 1007 1008 for (i = 0; i < 3; i++) { 1009 res = &hose->mem_resources[i]; 1010 if ((res->flags & IORESOURCE_MEM) && 1011 addr >= res->start && addr <= res->end) 1012 return 1; 1013 } 1014 } 1015 return 0; 1016 } 1017 1018 int fsl_pci_mcheck_exception(struct pt_regs *regs) 1019 { 1020 u32 inst; 1021 int ret; 1022 phys_addr_t addr = 0; 1023 1024 /* Let KVM/QEMU deal with the exception */ 1025 if (regs->msr & MSR_GS) 1026 return 0; 1027 1028 #ifdef CONFIG_PHYS_64BIT 1029 addr = mfspr(SPRN_MCARU); 1030 addr <<= 32; 1031 #endif 1032 addr += mfspr(SPRN_MCAR); 1033 1034 if (is_in_pci_mem_space(addr)) { 1035 if (user_mode(regs)) { 1036 pagefault_disable(); 1037 ret = get_user(regs->nip, &inst); 1038 pagefault_enable(); 1039 } else { 1040 ret = probe_kernel_address((void *)regs->nip, inst); 1041 } 1042 1043 if (!ret && mcheck_handle_load(regs, inst)) { 1044 regs->nip += 4; 1045 return 1; 1046 } 1047 } 1048 1049 return 0; 1050 } 1051 #endif 1052 1053 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 1054 static const struct of_device_id pci_ids[] = { 1055 { .compatible = "fsl,mpc8540-pci", }, 1056 { .compatible = "fsl,mpc8548-pcie", }, 1057 { .compatible = "fsl,mpc8610-pci", }, 1058 { .compatible = "fsl,mpc8641-pcie", }, 1059 { .compatible = "fsl,qoriq-pcie", }, 1060 { .compatible = "fsl,qoriq-pcie-v2.1", }, 1061 { .compatible = "fsl,qoriq-pcie-v2.2", }, 1062 { .compatible = "fsl,qoriq-pcie-v2.3", }, 1063 { .compatible = "fsl,qoriq-pcie-v2.4", }, 1064 { .compatible = "fsl,qoriq-pcie-v3.0", }, 1065 1066 /* 1067 * The following entries are for compatibility with older device 1068 * trees. 1069 */ 1070 { .compatible = "fsl,p1022-pcie", }, 1071 { .compatible = "fsl,p4080-pcie", }, 1072 1073 {}, 1074 }; 1075 1076 struct device_node *fsl_pci_primary; 1077 1078 void fsl_pci_assign_primary(void) 1079 { 1080 struct device_node *np; 1081 1082 /* Callers can specify the primary bus using other means. */ 1083 if (fsl_pci_primary) 1084 return; 1085 1086 /* If a PCI host bridge contains an ISA node, it's primary. */ 1087 np = of_find_node_by_type(NULL, "isa"); 1088 while ((fsl_pci_primary = of_get_parent(np))) { 1089 of_node_put(np); 1090 np = fsl_pci_primary; 1091 1092 if (of_match_node(pci_ids, np) && of_device_is_available(np)) 1093 return; 1094 } 1095 1096 /* 1097 * If there's no PCI host bridge with ISA, arbitrarily 1098 * designate one as primary. This can go away once 1099 * various bugs with primary-less systems are fixed. 1100 */ 1101 for_each_matching_node(np, pci_ids) { 1102 if (of_device_is_available(np)) { 1103 fsl_pci_primary = np; 1104 of_node_put(np); 1105 return; 1106 } 1107 } 1108 } 1109 1110 #ifdef CONFIG_PM_SLEEP 1111 static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id) 1112 { 1113 struct pci_controller *hose = dev_id; 1114 struct ccsr_pci __iomem *pci = hose->private_data; 1115 u32 dr; 1116 1117 dr = in_be32(&pci->pex_pme_mes_dr); 1118 if (!dr) 1119 return IRQ_NONE; 1120 1121 out_be32(&pci->pex_pme_mes_dr, dr); 1122 1123 return IRQ_HANDLED; 1124 } 1125 1126 static int fsl_pci_pme_probe(struct pci_controller *hose) 1127 { 1128 struct ccsr_pci __iomem *pci; 1129 struct pci_dev *dev; 1130 int pme_irq; 1131 int res; 1132 u16 pms; 1133 1134 /* Get hose's pci_dev */ 1135 dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list); 1136 1137 /* PME Disable */ 1138 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); 1139 pms &= ~PCI_PM_CTRL_PME_ENABLE; 1140 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); 1141 1142 pme_irq = irq_of_parse_and_map(hose->dn, 0); 1143 if (!pme_irq) { 1144 dev_err(&dev->dev, "Failed to map PME interrupt.\n"); 1145 1146 return -ENXIO; 1147 } 1148 1149 res = devm_request_irq(hose->parent, pme_irq, 1150 fsl_pci_pme_handle, 1151 IRQF_SHARED, 1152 "[PCI] PME", hose); 1153 if (res < 0) { 1154 dev_err(&dev->dev, "Unable to request irq %d for PME\n", pme_irq); 1155 irq_dispose_mapping(pme_irq); 1156 1157 return -ENODEV; 1158 } 1159 1160 pci = hose->private_data; 1161 1162 /* Enable PTOD, ENL23D & EXL23D */ 1163 clrbits32(&pci->pex_pme_mes_disr, 1164 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); 1165 1166 out_be32(&pci->pex_pme_mes_ier, 0); 1167 setbits32(&pci->pex_pme_mes_ier, 1168 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); 1169 1170 /* PME Enable */ 1171 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); 1172 pms |= PCI_PM_CTRL_PME_ENABLE; 1173 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); 1174 1175 return 0; 1176 } 1177 1178 static void send_pme_turnoff_message(struct pci_controller *hose) 1179 { 1180 struct ccsr_pci __iomem *pci = hose->private_data; 1181 u32 dr; 1182 int i; 1183 1184 /* Send PME_Turn_Off Message Request */ 1185 setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR); 1186 1187 /* Wait trun off done */ 1188 for (i = 0; i < 150; i++) { 1189 dr = in_be32(&pci->pex_pme_mes_dr); 1190 if (dr) { 1191 out_be32(&pci->pex_pme_mes_dr, dr); 1192 break; 1193 } 1194 1195 udelay(1000); 1196 } 1197 } 1198 1199 static void fsl_pci_syscore_do_suspend(struct pci_controller *hose) 1200 { 1201 send_pme_turnoff_message(hose); 1202 } 1203 1204 static int fsl_pci_syscore_suspend(void) 1205 { 1206 struct pci_controller *hose, *tmp; 1207 1208 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 1209 fsl_pci_syscore_do_suspend(hose); 1210 1211 return 0; 1212 } 1213 1214 static void fsl_pci_syscore_do_resume(struct pci_controller *hose) 1215 { 1216 struct ccsr_pci __iomem *pci = hose->private_data; 1217 u32 dr; 1218 int i; 1219 1220 /* Send Exit L2 State Message */ 1221 setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S); 1222 1223 /* Wait exit done */ 1224 for (i = 0; i < 150; i++) { 1225 dr = in_be32(&pci->pex_pme_mes_dr); 1226 if (dr) { 1227 out_be32(&pci->pex_pme_mes_dr, dr); 1228 break; 1229 } 1230 1231 udelay(1000); 1232 } 1233 1234 setup_pci_atmu(hose); 1235 } 1236 1237 static void fsl_pci_syscore_resume(void) 1238 { 1239 struct pci_controller *hose, *tmp; 1240 1241 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 1242 fsl_pci_syscore_do_resume(hose); 1243 } 1244 1245 static struct syscore_ops pci_syscore_pm_ops = { 1246 .suspend = fsl_pci_syscore_suspend, 1247 .resume = fsl_pci_syscore_resume, 1248 }; 1249 #endif 1250 1251 void fsl_pcibios_fixup_phb(struct pci_controller *phb) 1252 { 1253 #ifdef CONFIG_PM_SLEEP 1254 fsl_pci_pme_probe(phb); 1255 #endif 1256 } 1257 1258 static int fsl_pci_probe(struct platform_device *pdev) 1259 { 1260 struct device_node *node; 1261 int ret; 1262 1263 node = pdev->dev.of_node; 1264 ret = fsl_add_bridge(pdev, fsl_pci_primary == node); 1265 1266 mpc85xx_pci_err_probe(pdev); 1267 1268 return 0; 1269 } 1270 1271 static struct platform_driver fsl_pci_driver = { 1272 .driver = { 1273 .name = "fsl-pci", 1274 .of_match_table = pci_ids, 1275 }, 1276 .probe = fsl_pci_probe, 1277 }; 1278 1279 static int __init fsl_pci_init(void) 1280 { 1281 #ifdef CONFIG_PM_SLEEP 1282 register_syscore_ops(&pci_syscore_pm_ops); 1283 #endif 1284 return platform_driver_register(&fsl_pci_driver); 1285 } 1286 arch_initcall(fsl_pci_init); 1287 #endif 1288