xref: /openbmc/linux/arch/powerpc/sysdev/fsl_msi.c (revision af8f260a) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
4  *
5  * Author: Tony Li <tony.li@freescale.com>
6  *	   Jason Jin <Jason.jin@freescale.com>
7  *
8  * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
9  */
10 #include <linux/irq.h>
11 #include <linux/msi.h>
12 #include <linux/pci.h>
13 #include <linux/slab.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/of_platform.h>
17 #include <linux/interrupt.h>
18 #include <linux/irqdomain.h>
19 #include <linux/seq_file.h>
20 #include <sysdev/fsl_soc.h>
21 #include <asm/hw_irq.h>
22 #include <asm/ppc-pci.h>
23 #include <asm/mpic.h>
24 #include <asm/fsl_hcalls.h>
25 
26 #include "fsl_msi.h"
27 #include "fsl_pci.h"
28 
29 #define MSIIR_OFFSET_MASK	0xfffff
30 #define MSIIR_IBS_SHIFT		0
31 #define MSIIR_SRS_SHIFT		5
32 #define MSIIR1_IBS_SHIFT	4
33 #define MSIIR1_SRS_SHIFT	0
34 #define MSI_SRS_MASK		0xf
35 #define MSI_IBS_MASK		0x1f
36 
37 #define msi_hwirq(msi, msir_index, intr_index) \
38 		((msir_index) << (msi)->srs_shift | \
39 		 ((intr_index) << (msi)->ibs_shift))
40 
41 static LIST_HEAD(msi_head);
42 
43 struct fsl_msi_feature {
44 	u32 fsl_pic_ip;
45 	u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
46 };
47 
48 struct fsl_msi_cascade_data {
49 	struct fsl_msi *msi_data;
50 	int index;
51 	int virq;
52 };
53 
54 static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
55 {
56 	return in_be32(base + (reg >> 2));
57 }
58 
59 /*
60  * We do not need this actually. The MSIR register has been read once
61  * in the cascade interrupt. So, this MSI interrupt has been acked
62 */
63 static void fsl_msi_end_irq(struct irq_data *d)
64 {
65 }
66 
67 static void fsl_msi_print_chip(struct irq_data *irqd, struct seq_file *p)
68 {
69 	struct fsl_msi *msi_data = irqd->domain->host_data;
70 	irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
71 	int cascade_virq, srs;
72 
73 	srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK;
74 	cascade_virq = msi_data->cascade_array[srs]->virq;
75 
76 	seq_printf(p, " fsl-msi-%d", cascade_virq);
77 }
78 
79 
80 static struct irq_chip fsl_msi_chip = {
81 	.irq_mask	= pci_msi_mask_irq,
82 	.irq_unmask	= pci_msi_unmask_irq,
83 	.irq_ack	= fsl_msi_end_irq,
84 	.irq_print_chip = fsl_msi_print_chip,
85 };
86 
87 static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq,
88 				irq_hw_number_t hw)
89 {
90 	struct fsl_msi *msi_data = h->host_data;
91 	struct irq_chip *chip = &fsl_msi_chip;
92 
93 	irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
94 
95 	irq_set_chip_data(virq, msi_data);
96 	irq_set_chip_and_handler(virq, chip, handle_edge_irq);
97 
98 	return 0;
99 }
100 
101 static const struct irq_domain_ops fsl_msi_host_ops = {
102 	.map = fsl_msi_host_map,
103 };
104 
105 static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
106 {
107 	int rc, hwirq;
108 
109 	rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS_MAX,
110 			      irq_domain_get_of_node(msi_data->irqhost));
111 	if (rc)
112 		return rc;
113 
114 	/*
115 	 * Reserve all the hwirqs
116 	 * The available hwirqs will be released in fsl_msi_setup_hwirq()
117 	 */
118 	for (hwirq = 0; hwirq < NR_MSI_IRQS_MAX; hwirq++)
119 		msi_bitmap_reserve_hwirq(&msi_data->bitmap, hwirq);
120 
121 	return 0;
122 }
123 
124 static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
125 {
126 	struct msi_desc *entry;
127 	struct fsl_msi *msi_data;
128 	irq_hw_number_t hwirq;
129 
130 	msi_for_each_desc(entry, &pdev->dev, MSI_DESC_ASSOCIATED) {
131 		hwirq = virq_to_hw(entry->irq);
132 		msi_data = irq_get_chip_data(entry->irq);
133 		irq_set_msi_desc(entry->irq, NULL);
134 		irq_dispose_mapping(entry->irq);
135 		msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
136 	}
137 }
138 
139 static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
140 				struct msi_msg *msg,
141 				struct fsl_msi *fsl_msi_data)
142 {
143 	struct fsl_msi *msi_data = fsl_msi_data;
144 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
145 	u64 address; /* Physical address of the MSIIR */
146 	int len;
147 	const __be64 *reg;
148 
149 	/* If the msi-address-64 property exists, then use it */
150 	reg = of_get_property(hose->dn, "msi-address-64", &len);
151 	if (reg && (len == sizeof(u64)))
152 		address = be64_to_cpup(reg);
153 	else
154 		address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset;
155 
156 	msg->address_lo = lower_32_bits(address);
157 	msg->address_hi = upper_32_bits(address);
158 
159 	/*
160 	 * MPIC version 2.0 has erratum PIC1. It causes
161 	 * that neither MSI nor MSI-X can work fine.
162 	 * This is a workaround to allow MSI-X to function
163 	 * properly. It only works for MSI-X, we prevent
164 	 * MSI on buggy chips in fsl_setup_msi_irqs().
165 	 */
166 	if (msi_data->feature & MSI_HW_ERRATA_ENDIAN)
167 		msg->data = __swab32(hwirq);
168 	else
169 		msg->data = hwirq;
170 
171 	pr_debug("%s: allocated srs: %d, ibs: %d\n", __func__,
172 		 (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK,
173 		 (hwirq >> msi_data->ibs_shift) & MSI_IBS_MASK);
174 }
175 
176 static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
177 {
178 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
179 	struct device_node *np;
180 	phandle phandle = 0;
181 	int rc, hwirq = -ENOMEM;
182 	unsigned int virq;
183 	struct msi_desc *entry;
184 	struct msi_msg msg;
185 	struct fsl_msi *msi_data;
186 
187 	if (type == PCI_CAP_ID_MSI) {
188 		/*
189 		 * MPIC version 2.0 has erratum PIC1. For now MSI
190 		 * could not work. So check to prevent MSI from
191 		 * being used on the board with this erratum.
192 		 */
193 		list_for_each_entry(msi_data, &msi_head, list)
194 			if (msi_data->feature & MSI_HW_ERRATA_ENDIAN)
195 				return -EINVAL;
196 	}
197 
198 	/*
199 	 * If the PCI node has an fsl,msi property, then we need to use it
200 	 * to find the specific MSI.
201 	 */
202 	np = of_parse_phandle(hose->dn, "fsl,msi", 0);
203 	if (np) {
204 		if (of_device_is_compatible(np, "fsl,mpic-msi") ||
205 		    of_device_is_compatible(np, "fsl,vmpic-msi") ||
206 		    of_device_is_compatible(np, "fsl,vmpic-msi-v4.3"))
207 			phandle = np->phandle;
208 		else {
209 			dev_err(&pdev->dev,
210 				"node %pOF has an invalid fsl,msi phandle %u\n",
211 				hose->dn, np->phandle);
212 			return -EINVAL;
213 		}
214 	}
215 
216 	msi_for_each_desc(entry, &pdev->dev, MSI_DESC_NOTASSOCIATED) {
217 		/*
218 		 * Loop over all the MSI devices until we find one that has an
219 		 * available interrupt.
220 		 */
221 		list_for_each_entry(msi_data, &msi_head, list) {
222 			/*
223 			 * If the PCI node has an fsl,msi property, then we
224 			 * restrict our search to the corresponding MSI node.
225 			 * The simplest way is to skip over MSI nodes with the
226 			 * wrong phandle. Under the Freescale hypervisor, this
227 			 * has the additional benefit of skipping over MSI
228 			 * nodes that are not mapped in the PAMU.
229 			 */
230 			if (phandle && (phandle != msi_data->phandle))
231 				continue;
232 
233 			hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
234 			if (hwirq >= 0)
235 				break;
236 		}
237 
238 		if (hwirq < 0) {
239 			rc = hwirq;
240 			dev_err(&pdev->dev, "could not allocate MSI interrupt\n");
241 			goto out_free;
242 		}
243 
244 		virq = irq_create_mapping(msi_data->irqhost, hwirq);
245 
246 		if (!virq) {
247 			dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq);
248 			msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
249 			rc = -ENOSPC;
250 			goto out_free;
251 		}
252 		/* chip_data is msi_data via host->hostdata in host->map() */
253 		irq_set_msi_desc(virq, entry);
254 
255 		fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
256 		pci_write_msi_msg(virq, &msg);
257 	}
258 	return 0;
259 
260 out_free:
261 	/* free by the caller of this function */
262 	return rc;
263 }
264 
265 static irqreturn_t fsl_msi_cascade(int irq, void *data)
266 {
267 	struct fsl_msi *msi_data;
268 	int msir_index = -1;
269 	u32 msir_value = 0;
270 	u32 intr_index;
271 	u32 have_shift = 0;
272 	struct fsl_msi_cascade_data *cascade_data = data;
273 	irqreturn_t ret = IRQ_NONE;
274 
275 	msi_data = cascade_data->msi_data;
276 
277 	msir_index = cascade_data->index;
278 
279 	switch (msi_data->feature & FSL_PIC_IP_MASK) {
280 	case FSL_PIC_IP_MPIC:
281 		msir_value = fsl_msi_read(msi_data->msi_regs,
282 			msir_index * 0x10);
283 		break;
284 	case FSL_PIC_IP_IPIC:
285 		msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
286 		break;
287 #ifdef CONFIG_EPAPR_PARAVIRT
288 	case FSL_PIC_IP_VMPIC: {
289 		unsigned int ret;
290 		ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value);
291 		if (ret) {
292 			pr_err("fsl-msi: fh_vmpic_get_msir() failed for "
293 			       "irq %u (ret=%u)\n", irq, ret);
294 			msir_value = 0;
295 		}
296 		break;
297 	}
298 #endif
299 	}
300 
301 	while (msir_value) {
302 		int err;
303 		intr_index = ffs(msir_value) - 1;
304 
305 		err = generic_handle_domain_irq(msi_data->irqhost,
306 				msi_hwirq(msi_data, msir_index,
307 					  intr_index + have_shift));
308 		if (!err)
309 			ret = IRQ_HANDLED;
310 
311 		have_shift += intr_index + 1;
312 		msir_value = msir_value >> (intr_index + 1);
313 	}
314 
315 	return ret;
316 }
317 
318 static int fsl_of_msi_remove(struct platform_device *ofdev)
319 {
320 	struct fsl_msi *msi = platform_get_drvdata(ofdev);
321 	int virq, i;
322 
323 	if (msi->list.prev != NULL)
324 		list_del(&msi->list);
325 	for (i = 0; i < NR_MSI_REG_MAX; i++) {
326 		if (msi->cascade_array[i]) {
327 			virq = msi->cascade_array[i]->virq;
328 
329 			BUG_ON(!virq);
330 
331 			free_irq(virq, msi->cascade_array[i]);
332 			kfree(msi->cascade_array[i]);
333 			irq_dispose_mapping(virq);
334 		}
335 	}
336 	if (msi->bitmap.bitmap)
337 		msi_bitmap_free(&msi->bitmap);
338 	if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC)
339 		iounmap(msi->msi_regs);
340 	kfree(msi);
341 
342 	return 0;
343 }
344 
345 static struct lock_class_key fsl_msi_irq_class;
346 static struct lock_class_key fsl_msi_irq_request_class;
347 
348 static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
349 			       int offset, int irq_index)
350 {
351 	struct fsl_msi_cascade_data *cascade_data = NULL;
352 	int virt_msir, i, ret;
353 
354 	virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
355 	if (!virt_msir) {
356 		dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n",
357 			__func__, irq_index);
358 		return 0;
359 	}
360 
361 	cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL);
362 	if (!cascade_data) {
363 		dev_err(&dev->dev, "No memory for MSI cascade data\n");
364 		return -ENOMEM;
365 	}
366 	irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class,
367 			      &fsl_msi_irq_request_class);
368 	cascade_data->index = offset;
369 	cascade_data->msi_data = msi;
370 	cascade_data->virq = virt_msir;
371 	msi->cascade_array[irq_index] = cascade_data;
372 
373 	ret = request_irq(virt_msir, fsl_msi_cascade, IRQF_NO_THREAD,
374 			  "fsl-msi-cascade", cascade_data);
375 	if (ret) {
376 		dev_err(&dev->dev, "failed to request_irq(%d), ret = %d\n",
377 			virt_msir, ret);
378 		return ret;
379 	}
380 
381 	/* Release the hwirqs corresponding to this MSI register */
382 	for (i = 0; i < IRQS_PER_MSI_REG; i++)
383 		msi_bitmap_free_hwirqs(&msi->bitmap,
384 				       msi_hwirq(msi, offset, i), 1);
385 
386 	return 0;
387 }
388 
389 static const struct of_device_id fsl_of_msi_ids[];
390 static int fsl_of_msi_probe(struct platform_device *dev)
391 {
392 	const struct of_device_id *match;
393 	struct fsl_msi *msi;
394 	struct resource res, msiir;
395 	int err, i, j, irq_index, count;
396 	const u32 *p;
397 	const struct fsl_msi_feature *features;
398 	int len;
399 	u32 offset;
400 	struct pci_controller *phb;
401 
402 	match = of_match_device(fsl_of_msi_ids, &dev->dev);
403 	if (!match)
404 		return -EINVAL;
405 	features = match->data;
406 
407 	printk(KERN_DEBUG "Setting up Freescale MSI support\n");
408 
409 	msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
410 	if (!msi) {
411 		dev_err(&dev->dev, "No memory for MSI structure\n");
412 		return -ENOMEM;
413 	}
414 	platform_set_drvdata(dev, msi);
415 
416 	msi->irqhost = irq_domain_add_linear(dev->dev.of_node,
417 				      NR_MSI_IRQS_MAX, &fsl_msi_host_ops, msi);
418 
419 	if (msi->irqhost == NULL) {
420 		dev_err(&dev->dev, "No memory for MSI irqhost\n");
421 		err = -ENOMEM;
422 		goto error_out;
423 	}
424 
425 	/*
426 	 * Under the Freescale hypervisor, the msi nodes don't have a 'reg'
427 	 * property.  Instead, we use hypercalls to access the MSI.
428 	 */
429 	if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) {
430 		err = of_address_to_resource(dev->dev.of_node, 0, &res);
431 		if (err) {
432 			dev_err(&dev->dev, "invalid resource for node %pOF\n",
433 				dev->dev.of_node);
434 			goto error_out;
435 		}
436 
437 		msi->msi_regs = ioremap(res.start, resource_size(&res));
438 		if (!msi->msi_regs) {
439 			err = -ENOMEM;
440 			dev_err(&dev->dev, "could not map node %pOF\n",
441 				dev->dev.of_node);
442 			goto error_out;
443 		}
444 		msi->msiir_offset =
445 			features->msiir_offset + (res.start & 0xfffff);
446 
447 		/*
448 		 * First read the MSIIR/MSIIR1 offset from dts
449 		 * On failure use the hardcode MSIIR offset
450 		 */
451 		if (of_address_to_resource(dev->dev.of_node, 1, &msiir))
452 			msi->msiir_offset = features->msiir_offset +
453 					    (res.start & MSIIR_OFFSET_MASK);
454 		else
455 			msi->msiir_offset = msiir.start & MSIIR_OFFSET_MASK;
456 	}
457 
458 	msi->feature = features->fsl_pic_ip;
459 
460 	/* For erratum PIC1 on MPIC version 2.0*/
461 	if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) == FSL_PIC_IP_MPIC
462 			&& (fsl_mpic_primary_get_version() == 0x0200))
463 		msi->feature |= MSI_HW_ERRATA_ENDIAN;
464 
465 	/*
466 	 * Remember the phandle, so that we can match with any PCI nodes
467 	 * that have an "fsl,msi" property.
468 	 */
469 	msi->phandle = dev->dev.of_node->phandle;
470 
471 	err = fsl_msi_init_allocator(msi);
472 	if (err) {
473 		dev_err(&dev->dev, "Error allocating MSI bitmap\n");
474 		goto error_out;
475 	}
476 
477 	p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
478 
479 	if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3") ||
480 	    of_device_is_compatible(dev->dev.of_node, "fsl,vmpic-msi-v4.3")) {
481 		msi->srs_shift = MSIIR1_SRS_SHIFT;
482 		msi->ibs_shift = MSIIR1_IBS_SHIFT;
483 		if (p)
484 			dev_warn(&dev->dev, "%s: dose not support msi-available-ranges property\n",
485 				__func__);
486 
487 		for (irq_index = 0; irq_index < NR_MSI_REG_MSIIR1;
488 		     irq_index++) {
489 			err = fsl_msi_setup_hwirq(msi, dev,
490 						  irq_index, irq_index);
491 			if (err)
492 				goto error_out;
493 		}
494 	} else {
495 		static const u32 all_avail[] =
496 			{ 0, NR_MSI_REG_MSIIR * IRQS_PER_MSI_REG };
497 
498 		msi->srs_shift = MSIIR_SRS_SHIFT;
499 		msi->ibs_shift = MSIIR_IBS_SHIFT;
500 
501 		if (p && len % (2 * sizeof(u32)) != 0) {
502 			dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
503 				__func__);
504 			err = -EINVAL;
505 			goto error_out;
506 		}
507 
508 		if (!p) {
509 			p = all_avail;
510 			len = sizeof(all_avail);
511 		}
512 
513 		for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
514 			if (p[i * 2] % IRQS_PER_MSI_REG ||
515 			    p[i * 2 + 1] % IRQS_PER_MSI_REG) {
516 				pr_warn("%s: %pOF: msi available range of %u at %u is not IRQ-aligned\n",
517 				       __func__, dev->dev.of_node,
518 				       p[i * 2 + 1], p[i * 2]);
519 				err = -EINVAL;
520 				goto error_out;
521 			}
522 
523 			offset = p[i * 2] / IRQS_PER_MSI_REG;
524 			count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
525 
526 			for (j = 0; j < count; j++, irq_index++) {
527 				err = fsl_msi_setup_hwirq(msi, dev, offset + j,
528 							  irq_index);
529 				if (err)
530 					goto error_out;
531 			}
532 		}
533 	}
534 
535 	list_add_tail(&msi->list, &msi_head);
536 
537 	/*
538 	 * Apply the MSI ops to all the controllers.
539 	 * It doesn't hurt to reassign the same ops,
540 	 * but bail out if we find another MSI driver.
541 	 */
542 	list_for_each_entry(phb, &hose_list, list_node) {
543 		if (!phb->controller_ops.setup_msi_irqs) {
544 			phb->controller_ops.setup_msi_irqs = fsl_setup_msi_irqs;
545 			phb->controller_ops.teardown_msi_irqs = fsl_teardown_msi_irqs;
546 		} else if (phb->controller_ops.setup_msi_irqs != fsl_setup_msi_irqs) {
547 			dev_err(&dev->dev, "Different MSI driver already installed!\n");
548 			err = -ENODEV;
549 			goto error_out;
550 		}
551 	}
552 	return 0;
553 error_out:
554 	fsl_of_msi_remove(dev);
555 	return err;
556 }
557 
558 static const struct fsl_msi_feature mpic_msi_feature = {
559 	.fsl_pic_ip = FSL_PIC_IP_MPIC,
560 	.msiir_offset = 0x140,
561 };
562 
563 static const struct fsl_msi_feature ipic_msi_feature = {
564 	.fsl_pic_ip = FSL_PIC_IP_IPIC,
565 	.msiir_offset = 0x38,
566 };
567 
568 static const struct fsl_msi_feature vmpic_msi_feature = {
569 	.fsl_pic_ip = FSL_PIC_IP_VMPIC,
570 	.msiir_offset = 0,
571 };
572 
573 static const struct of_device_id fsl_of_msi_ids[] = {
574 	{
575 		.compatible = "fsl,mpic-msi",
576 		.data = &mpic_msi_feature,
577 	},
578 	{
579 		.compatible = "fsl,mpic-msi-v4.3",
580 		.data = &mpic_msi_feature,
581 	},
582 	{
583 		.compatible = "fsl,ipic-msi",
584 		.data = &ipic_msi_feature,
585 	},
586 #ifdef CONFIG_EPAPR_PARAVIRT
587 	{
588 		.compatible = "fsl,vmpic-msi",
589 		.data = &vmpic_msi_feature,
590 	},
591 	{
592 		.compatible = "fsl,vmpic-msi-v4.3",
593 		.data = &vmpic_msi_feature,
594 	},
595 #endif
596 	{}
597 };
598 
599 static struct platform_driver fsl_of_msi_driver = {
600 	.driver = {
601 		.name = "fsl-msi",
602 		.of_match_table = fsl_of_msi_ids,
603 	},
604 	.probe = fsl_of_msi_probe,
605 	.remove = fsl_of_msi_remove,
606 };
607 
608 static __init int fsl_of_msi_init(void)
609 {
610 	return platform_driver_register(&fsl_of_msi_driver);
611 }
612 
613 subsys_initcall(fsl_of_msi_init);
614