1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. 4 * 5 * Author: Tony Li <tony.li@freescale.com> 6 * Jason Jin <Jason.jin@freescale.com> 7 * 8 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c 9 */ 10 #include <linux/irq.h> 11 #include <linux/msi.h> 12 #include <linux/pci.h> 13 #include <linux/slab.h> 14 #include <linux/of_platform.h> 15 #include <linux/interrupt.h> 16 #include <linux/seq_file.h> 17 #include <sysdev/fsl_soc.h> 18 #include <asm/prom.h> 19 #include <asm/hw_irq.h> 20 #include <asm/ppc-pci.h> 21 #include <asm/mpic.h> 22 #include <asm/fsl_hcalls.h> 23 24 #include "fsl_msi.h" 25 #include "fsl_pci.h" 26 27 #define MSIIR_OFFSET_MASK 0xfffff 28 #define MSIIR_IBS_SHIFT 0 29 #define MSIIR_SRS_SHIFT 5 30 #define MSIIR1_IBS_SHIFT 4 31 #define MSIIR1_SRS_SHIFT 0 32 #define MSI_SRS_MASK 0xf 33 #define MSI_IBS_MASK 0x1f 34 35 #define msi_hwirq(msi, msir_index, intr_index) \ 36 ((msir_index) << (msi)->srs_shift | \ 37 ((intr_index) << (msi)->ibs_shift)) 38 39 static LIST_HEAD(msi_head); 40 41 struct fsl_msi_feature { 42 u32 fsl_pic_ip; 43 u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */ 44 }; 45 46 struct fsl_msi_cascade_data { 47 struct fsl_msi *msi_data; 48 int index; 49 int virq; 50 }; 51 52 static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg) 53 { 54 return in_be32(base + (reg >> 2)); 55 } 56 57 /* 58 * We do not need this actually. The MSIR register has been read once 59 * in the cascade interrupt. So, this MSI interrupt has been acked 60 */ 61 static void fsl_msi_end_irq(struct irq_data *d) 62 { 63 } 64 65 static void fsl_msi_print_chip(struct irq_data *irqd, struct seq_file *p) 66 { 67 struct fsl_msi *msi_data = irqd->domain->host_data; 68 irq_hw_number_t hwirq = irqd_to_hwirq(irqd); 69 int cascade_virq, srs; 70 71 srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK; 72 cascade_virq = msi_data->cascade_array[srs]->virq; 73 74 seq_printf(p, " fsl-msi-%d", cascade_virq); 75 } 76 77 78 static struct irq_chip fsl_msi_chip = { 79 .irq_mask = pci_msi_mask_irq, 80 .irq_unmask = pci_msi_unmask_irq, 81 .irq_ack = fsl_msi_end_irq, 82 .irq_print_chip = fsl_msi_print_chip, 83 }; 84 85 static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq, 86 irq_hw_number_t hw) 87 { 88 struct fsl_msi *msi_data = h->host_data; 89 struct irq_chip *chip = &fsl_msi_chip; 90 91 irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING); 92 93 irq_set_chip_data(virq, msi_data); 94 irq_set_chip_and_handler(virq, chip, handle_edge_irq); 95 96 return 0; 97 } 98 99 static const struct irq_domain_ops fsl_msi_host_ops = { 100 .map = fsl_msi_host_map, 101 }; 102 103 static int fsl_msi_init_allocator(struct fsl_msi *msi_data) 104 { 105 int rc, hwirq; 106 107 rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS_MAX, 108 irq_domain_get_of_node(msi_data->irqhost)); 109 if (rc) 110 return rc; 111 112 /* 113 * Reserve all the hwirqs 114 * The available hwirqs will be released in fsl_msi_setup_hwirq() 115 */ 116 for (hwirq = 0; hwirq < NR_MSI_IRQS_MAX; hwirq++) 117 msi_bitmap_reserve_hwirq(&msi_data->bitmap, hwirq); 118 119 return 0; 120 } 121 122 static void fsl_teardown_msi_irqs(struct pci_dev *pdev) 123 { 124 struct msi_desc *entry; 125 struct fsl_msi *msi_data; 126 irq_hw_number_t hwirq; 127 128 msi_for_each_desc(entry, &pdev->dev, MSI_DESC_ASSOCIATED) { 129 hwirq = virq_to_hw(entry->irq); 130 msi_data = irq_get_chip_data(entry->irq); 131 irq_set_msi_desc(entry->irq, NULL); 132 irq_dispose_mapping(entry->irq); 133 msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1); 134 } 135 } 136 137 static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq, 138 struct msi_msg *msg, 139 struct fsl_msi *fsl_msi_data) 140 { 141 struct fsl_msi *msi_data = fsl_msi_data; 142 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 143 u64 address; /* Physical address of the MSIIR */ 144 int len; 145 const __be64 *reg; 146 147 /* If the msi-address-64 property exists, then use it */ 148 reg = of_get_property(hose->dn, "msi-address-64", &len); 149 if (reg && (len == sizeof(u64))) 150 address = be64_to_cpup(reg); 151 else 152 address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset; 153 154 msg->address_lo = lower_32_bits(address); 155 msg->address_hi = upper_32_bits(address); 156 157 /* 158 * MPIC version 2.0 has erratum PIC1. It causes 159 * that neither MSI nor MSI-X can work fine. 160 * This is a workaround to allow MSI-X to function 161 * properly. It only works for MSI-X, we prevent 162 * MSI on buggy chips in fsl_setup_msi_irqs(). 163 */ 164 if (msi_data->feature & MSI_HW_ERRATA_ENDIAN) 165 msg->data = __swab32(hwirq); 166 else 167 msg->data = hwirq; 168 169 pr_debug("%s: allocated srs: %d, ibs: %d\n", __func__, 170 (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK, 171 (hwirq >> msi_data->ibs_shift) & MSI_IBS_MASK); 172 } 173 174 static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) 175 { 176 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 177 struct device_node *np; 178 phandle phandle = 0; 179 int rc, hwirq = -ENOMEM; 180 unsigned int virq; 181 struct msi_desc *entry; 182 struct msi_msg msg; 183 struct fsl_msi *msi_data; 184 185 if (type == PCI_CAP_ID_MSI) { 186 /* 187 * MPIC version 2.0 has erratum PIC1. For now MSI 188 * could not work. So check to prevent MSI from 189 * being used on the board with this erratum. 190 */ 191 list_for_each_entry(msi_data, &msi_head, list) 192 if (msi_data->feature & MSI_HW_ERRATA_ENDIAN) 193 return -EINVAL; 194 } 195 196 /* 197 * If the PCI node has an fsl,msi property, then we need to use it 198 * to find the specific MSI. 199 */ 200 np = of_parse_phandle(hose->dn, "fsl,msi", 0); 201 if (np) { 202 if (of_device_is_compatible(np, "fsl,mpic-msi") || 203 of_device_is_compatible(np, "fsl,vmpic-msi") || 204 of_device_is_compatible(np, "fsl,vmpic-msi-v4.3")) 205 phandle = np->phandle; 206 else { 207 dev_err(&pdev->dev, 208 "node %pOF has an invalid fsl,msi phandle %u\n", 209 hose->dn, np->phandle); 210 return -EINVAL; 211 } 212 } 213 214 msi_for_each_desc(entry, &pdev->dev, MSI_DESC_NOTASSOCIATED) { 215 /* 216 * Loop over all the MSI devices until we find one that has an 217 * available interrupt. 218 */ 219 list_for_each_entry(msi_data, &msi_head, list) { 220 /* 221 * If the PCI node has an fsl,msi property, then we 222 * restrict our search to the corresponding MSI node. 223 * The simplest way is to skip over MSI nodes with the 224 * wrong phandle. Under the Freescale hypervisor, this 225 * has the additional benefit of skipping over MSI 226 * nodes that are not mapped in the PAMU. 227 */ 228 if (phandle && (phandle != msi_data->phandle)) 229 continue; 230 231 hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1); 232 if (hwirq >= 0) 233 break; 234 } 235 236 if (hwirq < 0) { 237 rc = hwirq; 238 dev_err(&pdev->dev, "could not allocate MSI interrupt\n"); 239 goto out_free; 240 } 241 242 virq = irq_create_mapping(msi_data->irqhost, hwirq); 243 244 if (!virq) { 245 dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq); 246 msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1); 247 rc = -ENOSPC; 248 goto out_free; 249 } 250 /* chip_data is msi_data via host->hostdata in host->map() */ 251 irq_set_msi_desc(virq, entry); 252 253 fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data); 254 pci_write_msi_msg(virq, &msg); 255 } 256 return 0; 257 258 out_free: 259 /* free by the caller of this function */ 260 return rc; 261 } 262 263 static irqreturn_t fsl_msi_cascade(int irq, void *data) 264 { 265 struct fsl_msi *msi_data; 266 int msir_index = -1; 267 u32 msir_value = 0; 268 u32 intr_index; 269 u32 have_shift = 0; 270 struct fsl_msi_cascade_data *cascade_data = data; 271 irqreturn_t ret = IRQ_NONE; 272 273 msi_data = cascade_data->msi_data; 274 275 msir_index = cascade_data->index; 276 277 switch (msi_data->feature & FSL_PIC_IP_MASK) { 278 case FSL_PIC_IP_MPIC: 279 msir_value = fsl_msi_read(msi_data->msi_regs, 280 msir_index * 0x10); 281 break; 282 case FSL_PIC_IP_IPIC: 283 msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4); 284 break; 285 #ifdef CONFIG_EPAPR_PARAVIRT 286 case FSL_PIC_IP_VMPIC: { 287 unsigned int ret; 288 ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value); 289 if (ret) { 290 pr_err("fsl-msi: fh_vmpic_get_msir() failed for " 291 "irq %u (ret=%u)\n", irq, ret); 292 msir_value = 0; 293 } 294 break; 295 } 296 #endif 297 } 298 299 while (msir_value) { 300 int err; 301 intr_index = ffs(msir_value) - 1; 302 303 err = generic_handle_domain_irq(msi_data->irqhost, 304 msi_hwirq(msi_data, msir_index, 305 intr_index + have_shift)); 306 if (!err) 307 ret = IRQ_HANDLED; 308 309 have_shift += intr_index + 1; 310 msir_value = msir_value >> (intr_index + 1); 311 } 312 313 return ret; 314 } 315 316 static int fsl_of_msi_remove(struct platform_device *ofdev) 317 { 318 struct fsl_msi *msi = platform_get_drvdata(ofdev); 319 int virq, i; 320 321 if (msi->list.prev != NULL) 322 list_del(&msi->list); 323 for (i = 0; i < NR_MSI_REG_MAX; i++) { 324 if (msi->cascade_array[i]) { 325 virq = msi->cascade_array[i]->virq; 326 327 BUG_ON(!virq); 328 329 free_irq(virq, msi->cascade_array[i]); 330 kfree(msi->cascade_array[i]); 331 irq_dispose_mapping(virq); 332 } 333 } 334 if (msi->bitmap.bitmap) 335 msi_bitmap_free(&msi->bitmap); 336 if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) 337 iounmap(msi->msi_regs); 338 kfree(msi); 339 340 return 0; 341 } 342 343 static struct lock_class_key fsl_msi_irq_class; 344 static struct lock_class_key fsl_msi_irq_request_class; 345 346 static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev, 347 int offset, int irq_index) 348 { 349 struct fsl_msi_cascade_data *cascade_data = NULL; 350 int virt_msir, i, ret; 351 352 virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index); 353 if (!virt_msir) { 354 dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n", 355 __func__, irq_index); 356 return 0; 357 } 358 359 cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL); 360 if (!cascade_data) { 361 dev_err(&dev->dev, "No memory for MSI cascade data\n"); 362 return -ENOMEM; 363 } 364 irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class, 365 &fsl_msi_irq_request_class); 366 cascade_data->index = offset; 367 cascade_data->msi_data = msi; 368 cascade_data->virq = virt_msir; 369 msi->cascade_array[irq_index] = cascade_data; 370 371 ret = request_irq(virt_msir, fsl_msi_cascade, IRQF_NO_THREAD, 372 "fsl-msi-cascade", cascade_data); 373 if (ret) { 374 dev_err(&dev->dev, "failed to request_irq(%d), ret = %d\n", 375 virt_msir, ret); 376 return ret; 377 } 378 379 /* Release the hwirqs corresponding to this MSI register */ 380 for (i = 0; i < IRQS_PER_MSI_REG; i++) 381 msi_bitmap_free_hwirqs(&msi->bitmap, 382 msi_hwirq(msi, offset, i), 1); 383 384 return 0; 385 } 386 387 static const struct of_device_id fsl_of_msi_ids[]; 388 static int fsl_of_msi_probe(struct platform_device *dev) 389 { 390 const struct of_device_id *match; 391 struct fsl_msi *msi; 392 struct resource res, msiir; 393 int err, i, j, irq_index, count; 394 const u32 *p; 395 const struct fsl_msi_feature *features; 396 int len; 397 u32 offset; 398 struct pci_controller *phb; 399 400 match = of_match_device(fsl_of_msi_ids, &dev->dev); 401 if (!match) 402 return -EINVAL; 403 features = match->data; 404 405 printk(KERN_DEBUG "Setting up Freescale MSI support\n"); 406 407 msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL); 408 if (!msi) { 409 dev_err(&dev->dev, "No memory for MSI structure\n"); 410 return -ENOMEM; 411 } 412 platform_set_drvdata(dev, msi); 413 414 msi->irqhost = irq_domain_add_linear(dev->dev.of_node, 415 NR_MSI_IRQS_MAX, &fsl_msi_host_ops, msi); 416 417 if (msi->irqhost == NULL) { 418 dev_err(&dev->dev, "No memory for MSI irqhost\n"); 419 err = -ENOMEM; 420 goto error_out; 421 } 422 423 /* 424 * Under the Freescale hypervisor, the msi nodes don't have a 'reg' 425 * property. Instead, we use hypercalls to access the MSI. 426 */ 427 if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) { 428 err = of_address_to_resource(dev->dev.of_node, 0, &res); 429 if (err) { 430 dev_err(&dev->dev, "invalid resource for node %pOF\n", 431 dev->dev.of_node); 432 goto error_out; 433 } 434 435 msi->msi_regs = ioremap(res.start, resource_size(&res)); 436 if (!msi->msi_regs) { 437 err = -ENOMEM; 438 dev_err(&dev->dev, "could not map node %pOF\n", 439 dev->dev.of_node); 440 goto error_out; 441 } 442 msi->msiir_offset = 443 features->msiir_offset + (res.start & 0xfffff); 444 445 /* 446 * First read the MSIIR/MSIIR1 offset from dts 447 * On failure use the hardcode MSIIR offset 448 */ 449 if (of_address_to_resource(dev->dev.of_node, 1, &msiir)) 450 msi->msiir_offset = features->msiir_offset + 451 (res.start & MSIIR_OFFSET_MASK); 452 else 453 msi->msiir_offset = msiir.start & MSIIR_OFFSET_MASK; 454 } 455 456 msi->feature = features->fsl_pic_ip; 457 458 /* For erratum PIC1 on MPIC version 2.0*/ 459 if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) == FSL_PIC_IP_MPIC 460 && (fsl_mpic_primary_get_version() == 0x0200)) 461 msi->feature |= MSI_HW_ERRATA_ENDIAN; 462 463 /* 464 * Remember the phandle, so that we can match with any PCI nodes 465 * that have an "fsl,msi" property. 466 */ 467 msi->phandle = dev->dev.of_node->phandle; 468 469 err = fsl_msi_init_allocator(msi); 470 if (err) { 471 dev_err(&dev->dev, "Error allocating MSI bitmap\n"); 472 goto error_out; 473 } 474 475 p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len); 476 477 if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3") || 478 of_device_is_compatible(dev->dev.of_node, "fsl,vmpic-msi-v4.3")) { 479 msi->srs_shift = MSIIR1_SRS_SHIFT; 480 msi->ibs_shift = MSIIR1_IBS_SHIFT; 481 if (p) 482 dev_warn(&dev->dev, "%s: dose not support msi-available-ranges property\n", 483 __func__); 484 485 for (irq_index = 0; irq_index < NR_MSI_REG_MSIIR1; 486 irq_index++) { 487 err = fsl_msi_setup_hwirq(msi, dev, 488 irq_index, irq_index); 489 if (err) 490 goto error_out; 491 } 492 } else { 493 static const u32 all_avail[] = 494 { 0, NR_MSI_REG_MSIIR * IRQS_PER_MSI_REG }; 495 496 msi->srs_shift = MSIIR_SRS_SHIFT; 497 msi->ibs_shift = MSIIR_IBS_SHIFT; 498 499 if (p && len % (2 * sizeof(u32)) != 0) { 500 dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n", 501 __func__); 502 err = -EINVAL; 503 goto error_out; 504 } 505 506 if (!p) { 507 p = all_avail; 508 len = sizeof(all_avail); 509 } 510 511 for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) { 512 if (p[i * 2] % IRQS_PER_MSI_REG || 513 p[i * 2 + 1] % IRQS_PER_MSI_REG) { 514 pr_warn("%s: %pOF: msi available range of %u at %u is not IRQ-aligned\n", 515 __func__, dev->dev.of_node, 516 p[i * 2 + 1], p[i * 2]); 517 err = -EINVAL; 518 goto error_out; 519 } 520 521 offset = p[i * 2] / IRQS_PER_MSI_REG; 522 count = p[i * 2 + 1] / IRQS_PER_MSI_REG; 523 524 for (j = 0; j < count; j++, irq_index++) { 525 err = fsl_msi_setup_hwirq(msi, dev, offset + j, 526 irq_index); 527 if (err) 528 goto error_out; 529 } 530 } 531 } 532 533 list_add_tail(&msi->list, &msi_head); 534 535 /* 536 * Apply the MSI ops to all the controllers. 537 * It doesn't hurt to reassign the same ops, 538 * but bail out if we find another MSI driver. 539 */ 540 list_for_each_entry(phb, &hose_list, list_node) { 541 if (!phb->controller_ops.setup_msi_irqs) { 542 phb->controller_ops.setup_msi_irqs = fsl_setup_msi_irqs; 543 phb->controller_ops.teardown_msi_irqs = fsl_teardown_msi_irqs; 544 } else if (phb->controller_ops.setup_msi_irqs != fsl_setup_msi_irqs) { 545 dev_err(&dev->dev, "Different MSI driver already installed!\n"); 546 err = -ENODEV; 547 goto error_out; 548 } 549 } 550 return 0; 551 error_out: 552 fsl_of_msi_remove(dev); 553 return err; 554 } 555 556 static const struct fsl_msi_feature mpic_msi_feature = { 557 .fsl_pic_ip = FSL_PIC_IP_MPIC, 558 .msiir_offset = 0x140, 559 }; 560 561 static const struct fsl_msi_feature ipic_msi_feature = { 562 .fsl_pic_ip = FSL_PIC_IP_IPIC, 563 .msiir_offset = 0x38, 564 }; 565 566 static const struct fsl_msi_feature vmpic_msi_feature = { 567 .fsl_pic_ip = FSL_PIC_IP_VMPIC, 568 .msiir_offset = 0, 569 }; 570 571 static const struct of_device_id fsl_of_msi_ids[] = { 572 { 573 .compatible = "fsl,mpic-msi", 574 .data = &mpic_msi_feature, 575 }, 576 { 577 .compatible = "fsl,mpic-msi-v4.3", 578 .data = &mpic_msi_feature, 579 }, 580 { 581 .compatible = "fsl,ipic-msi", 582 .data = &ipic_msi_feature, 583 }, 584 #ifdef CONFIG_EPAPR_PARAVIRT 585 { 586 .compatible = "fsl,vmpic-msi", 587 .data = &vmpic_msi_feature, 588 }, 589 { 590 .compatible = "fsl,vmpic-msi-v4.3", 591 .data = &vmpic_msi_feature, 592 }, 593 #endif 594 {} 595 }; 596 597 static struct platform_driver fsl_of_msi_driver = { 598 .driver = { 599 .name = "fsl-msi", 600 .of_match_table = fsl_of_msi_ids, 601 }, 602 .probe = fsl_of_msi_probe, 603 .remove = fsl_of_msi_remove, 604 }; 605 606 static __init int fsl_of_msi_init(void) 607 { 608 return platform_driver_register(&fsl_of_msi_driver); 609 } 610 611 subsys_initcall(fsl_of_msi_init); 612