1 /* 2 * Common CPM code 3 * 4 * Author: Scott Wood <scottwood@freescale.com> 5 * 6 * Copyright 2007-2008,2010 Freescale Semiconductor, Inc. 7 * 8 * Some parts derived from commproc.c/cpm2_common.c, which is: 9 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net) 10 * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com> 11 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) 12 * 2006 (c) MontaVista Software, Inc. 13 * Vitaly Bordug <vbordug@ru.mvista.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of version 2 of the GNU General Public License as 17 * published by the Free Software Foundation. 18 */ 19 20 #include <linux/init.h> 21 #include <linux/of_device.h> 22 #include <linux/spinlock.h> 23 #include <linux/export.h> 24 #include <linux/of.h> 25 #include <linux/of_address.h> 26 #include <linux/slab.h> 27 28 #include <asm/udbg.h> 29 #include <asm/io.h> 30 #include <asm/cpm.h> 31 #include <asm/fixmap.h> 32 #include <soc/fsl/qe/qe.h> 33 34 #include <mm/mmu_decl.h> 35 36 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO) 37 #include <linux/of_gpio.h> 38 #endif 39 40 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM 41 static u32 __iomem *cpm_udbg_txdesc; 42 static u8 __iomem *cpm_udbg_txbuf; 43 44 static void udbg_putc_cpm(char c) 45 { 46 if (c == '\n') 47 udbg_putc_cpm('\r'); 48 49 while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000) 50 ; 51 52 out_8(cpm_udbg_txbuf, c); 53 out_be32(&cpm_udbg_txdesc[0], 0xa0000001); 54 } 55 56 void __init udbg_init_cpm(void) 57 { 58 #ifdef CONFIG_PPC_8xx 59 cpm_udbg_txdesc = (u32 __iomem __force *) 60 (CONFIG_PPC_EARLY_DEBUG_CPM_ADDR - PHYS_IMMR_BASE + 61 VIRT_IMMR_BASE); 62 cpm_udbg_txbuf = (u8 __iomem __force *) 63 (in_be32(&cpm_udbg_txdesc[1]) - PHYS_IMMR_BASE + 64 VIRT_IMMR_BASE); 65 #else 66 cpm_udbg_txdesc = (u32 __iomem __force *) 67 CONFIG_PPC_EARLY_DEBUG_CPM_ADDR; 68 cpm_udbg_txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]); 69 #endif 70 71 if (cpm_udbg_txdesc) { 72 #ifdef CONFIG_CPM2 73 setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG); 74 #endif 75 udbg_putc = udbg_putc_cpm; 76 } 77 } 78 #endif 79 80 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO) 81 82 struct cpm2_ioports { 83 u32 dir, par, sor, odr, dat; 84 u32 res[3]; 85 }; 86 87 struct cpm2_gpio32_chip { 88 struct of_mm_gpio_chip mm_gc; 89 spinlock_t lock; 90 91 /* shadowed data register to clear/set bits safely */ 92 u32 cpdata; 93 }; 94 95 static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc) 96 { 97 struct cpm2_gpio32_chip *cpm2_gc = 98 container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc); 99 struct cpm2_ioports __iomem *iop = mm_gc->regs; 100 101 cpm2_gc->cpdata = in_be32(&iop->dat); 102 } 103 104 static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio) 105 { 106 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 107 struct cpm2_ioports __iomem *iop = mm_gc->regs; 108 u32 pin_mask; 109 110 pin_mask = 1 << (31 - gpio); 111 112 return !!(in_be32(&iop->dat) & pin_mask); 113 } 114 115 static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask, 116 int value) 117 { 118 struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(&mm_gc->gc); 119 struct cpm2_ioports __iomem *iop = mm_gc->regs; 120 121 if (value) 122 cpm2_gc->cpdata |= pin_mask; 123 else 124 cpm2_gc->cpdata &= ~pin_mask; 125 126 out_be32(&iop->dat, cpm2_gc->cpdata); 127 } 128 129 static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value) 130 { 131 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 132 struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc); 133 unsigned long flags; 134 u32 pin_mask = 1 << (31 - gpio); 135 136 spin_lock_irqsave(&cpm2_gc->lock, flags); 137 138 __cpm2_gpio32_set(mm_gc, pin_mask, value); 139 140 spin_unlock_irqrestore(&cpm2_gc->lock, flags); 141 } 142 143 static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 144 { 145 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 146 struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc); 147 struct cpm2_ioports __iomem *iop = mm_gc->regs; 148 unsigned long flags; 149 u32 pin_mask = 1 << (31 - gpio); 150 151 spin_lock_irqsave(&cpm2_gc->lock, flags); 152 153 setbits32(&iop->dir, pin_mask); 154 __cpm2_gpio32_set(mm_gc, pin_mask, val); 155 156 spin_unlock_irqrestore(&cpm2_gc->lock, flags); 157 158 return 0; 159 } 160 161 static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) 162 { 163 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 164 struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc); 165 struct cpm2_ioports __iomem *iop = mm_gc->regs; 166 unsigned long flags; 167 u32 pin_mask = 1 << (31 - gpio); 168 169 spin_lock_irqsave(&cpm2_gc->lock, flags); 170 171 clrbits32(&iop->dir, pin_mask); 172 173 spin_unlock_irqrestore(&cpm2_gc->lock, flags); 174 175 return 0; 176 } 177 178 int cpm2_gpiochip_add32(struct device_node *np) 179 { 180 struct cpm2_gpio32_chip *cpm2_gc; 181 struct of_mm_gpio_chip *mm_gc; 182 struct gpio_chip *gc; 183 184 cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL); 185 if (!cpm2_gc) 186 return -ENOMEM; 187 188 spin_lock_init(&cpm2_gc->lock); 189 190 mm_gc = &cpm2_gc->mm_gc; 191 gc = &mm_gc->gc; 192 193 mm_gc->save_regs = cpm2_gpio32_save_regs; 194 gc->ngpio = 32; 195 gc->direction_input = cpm2_gpio32_dir_in; 196 gc->direction_output = cpm2_gpio32_dir_out; 197 gc->get = cpm2_gpio32_get; 198 gc->set = cpm2_gpio32_set; 199 200 return of_mm_gpiochip_add_data(np, mm_gc, cpm2_gc); 201 } 202 #endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */ 203