1 /* 2 * Common CPM code 3 * 4 * Author: Scott Wood <scottwood@freescale.com> 5 * 6 * Copyright 2007 Freescale Semiconductor, Inc. 7 * 8 * Some parts derived from commproc.c/cpm2_common.c, which is: 9 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net) 10 * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com> 11 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) 12 * 2006 (c) MontaVista Software, Inc. 13 * Vitaly Bordug <vbordug@ru.mvista.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of version 2 of the GNU General Public License as 17 * published by the Free Software Foundation. 18 */ 19 20 #include <linux/init.h> 21 #include <linux/of_device.h> 22 #include <linux/spinlock.h> 23 #include <linux/of.h> 24 25 #include <asm/udbg.h> 26 #include <asm/io.h> 27 #include <asm/system.h> 28 #include <asm/rheap.h> 29 #include <asm/cpm.h> 30 31 #include <mm/mmu_decl.h> 32 33 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO) 34 #include <linux/of_gpio.h> 35 #endif 36 37 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM 38 static u32 __iomem *cpm_udbg_txdesc = 39 (u32 __iomem __force *)CONFIG_PPC_EARLY_DEBUG_CPM_ADDR; 40 41 static void udbg_putc_cpm(char c) 42 { 43 u8 __iomem *txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]); 44 45 if (c == '\n') 46 udbg_putc_cpm('\r'); 47 48 while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000) 49 ; 50 51 out_8(txbuf, c); 52 out_be32(&cpm_udbg_txdesc[0], 0xa0000001); 53 } 54 55 void __init udbg_init_cpm(void) 56 { 57 if (cpm_udbg_txdesc) { 58 #ifdef CONFIG_CPM2 59 setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG); 60 #endif 61 udbg_putc = udbg_putc_cpm; 62 } 63 } 64 #endif 65 66 static spinlock_t cpm_muram_lock; 67 static rh_block_t cpm_boot_muram_rh_block[16]; 68 static rh_info_t cpm_muram_info; 69 static u8 __iomem *muram_vbase; 70 static phys_addr_t muram_pbase; 71 72 /* Max address size we deal with */ 73 #define OF_MAX_ADDR_CELLS 4 74 75 int cpm_muram_init(void) 76 { 77 struct device_node *np; 78 struct resource r; 79 u32 zero[OF_MAX_ADDR_CELLS] = {}; 80 resource_size_t max = 0; 81 int i = 0; 82 int ret = 0; 83 84 if (muram_pbase) 85 return 0; 86 87 spin_lock_init(&cpm_muram_lock); 88 /* initialize the info header */ 89 rh_init(&cpm_muram_info, 1, 90 sizeof(cpm_boot_muram_rh_block) / 91 sizeof(cpm_boot_muram_rh_block[0]), 92 cpm_boot_muram_rh_block); 93 94 np = of_find_compatible_node(NULL, NULL, "fsl,cpm-muram-data"); 95 if (!np) { 96 /* try legacy bindings */ 97 np = of_find_node_by_name(NULL, "data-only"); 98 if (!np) { 99 printk(KERN_ERR "Cannot find CPM muram data node"); 100 ret = -ENODEV; 101 goto out; 102 } 103 } 104 105 muram_pbase = of_translate_address(np, zero); 106 if (muram_pbase == (phys_addr_t)OF_BAD_ADDR) { 107 printk(KERN_ERR "Cannot translate zero through CPM muram node"); 108 ret = -ENODEV; 109 goto out; 110 } 111 112 while (of_address_to_resource(np, i++, &r) == 0) { 113 if (r.end > max) 114 max = r.end; 115 116 rh_attach_region(&cpm_muram_info, r.start - muram_pbase, 117 r.end - r.start + 1); 118 } 119 120 muram_vbase = ioremap(muram_pbase, max - muram_pbase + 1); 121 if (!muram_vbase) { 122 printk(KERN_ERR "Cannot map CPM muram"); 123 ret = -ENOMEM; 124 } 125 126 out: 127 of_node_put(np); 128 return ret; 129 } 130 131 /** 132 * cpm_muram_alloc - allocate the requested size worth of multi-user ram 133 * @size: number of bytes to allocate 134 * @align: requested alignment, in bytes 135 * 136 * This function returns an offset into the muram area. 137 * Use cpm_dpram_addr() to get the virtual address of the area. 138 * Use cpm_muram_free() to free the allocation. 139 */ 140 unsigned long cpm_muram_alloc(unsigned long size, unsigned long align) 141 { 142 unsigned long start; 143 unsigned long flags; 144 145 spin_lock_irqsave(&cpm_muram_lock, flags); 146 cpm_muram_info.alignment = align; 147 start = rh_alloc(&cpm_muram_info, size, "commproc"); 148 spin_unlock_irqrestore(&cpm_muram_lock, flags); 149 150 return start; 151 } 152 EXPORT_SYMBOL(cpm_muram_alloc); 153 154 /** 155 * cpm_muram_free - free a chunk of multi-user ram 156 * @offset: The beginning of the chunk as returned by cpm_muram_alloc(). 157 */ 158 int cpm_muram_free(unsigned long offset) 159 { 160 int ret; 161 unsigned long flags; 162 163 spin_lock_irqsave(&cpm_muram_lock, flags); 164 ret = rh_free(&cpm_muram_info, offset); 165 spin_unlock_irqrestore(&cpm_muram_lock, flags); 166 167 return ret; 168 } 169 EXPORT_SYMBOL(cpm_muram_free); 170 171 /** 172 * cpm_muram_alloc_fixed - reserve a specific region of multi-user ram 173 * @offset: the offset into the muram area to reserve 174 * @size: the number of bytes to reserve 175 * 176 * This function returns "start" on success, -ENOMEM on failure. 177 * Use cpm_dpram_addr() to get the virtual address of the area. 178 * Use cpm_muram_free() to free the allocation. 179 */ 180 unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size) 181 { 182 unsigned long start; 183 unsigned long flags; 184 185 spin_lock_irqsave(&cpm_muram_lock, flags); 186 cpm_muram_info.alignment = 1; 187 start = rh_alloc_fixed(&cpm_muram_info, offset, size, "commproc"); 188 spin_unlock_irqrestore(&cpm_muram_lock, flags); 189 190 return start; 191 } 192 EXPORT_SYMBOL(cpm_muram_alloc_fixed); 193 194 /** 195 * cpm_muram_addr - turn a muram offset into a virtual address 196 * @offset: muram offset to convert 197 */ 198 void __iomem *cpm_muram_addr(unsigned long offset) 199 { 200 return muram_vbase + offset; 201 } 202 EXPORT_SYMBOL(cpm_muram_addr); 203 204 unsigned long cpm_muram_offset(void __iomem *addr) 205 { 206 return addr - (void __iomem *)muram_vbase; 207 } 208 EXPORT_SYMBOL(cpm_muram_offset); 209 210 /** 211 * cpm_muram_dma - turn a muram virtual address into a DMA address 212 * @offset: virtual address from cpm_muram_addr() to convert 213 */ 214 dma_addr_t cpm_muram_dma(void __iomem *addr) 215 { 216 return muram_pbase + ((u8 __iomem *)addr - muram_vbase); 217 } 218 EXPORT_SYMBOL(cpm_muram_dma); 219 220 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO) 221 222 struct cpm2_ioports { 223 u32 dir, par, sor, odr, dat; 224 u32 res[3]; 225 }; 226 227 struct cpm2_gpio32_chip { 228 struct of_mm_gpio_chip mm_gc; 229 spinlock_t lock; 230 231 /* shadowed data register to clear/set bits safely */ 232 u32 cpdata; 233 }; 234 235 static inline struct cpm2_gpio32_chip * 236 to_cpm2_gpio32_chip(struct of_mm_gpio_chip *mm_gc) 237 { 238 return container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc); 239 } 240 241 static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc) 242 { 243 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc); 244 struct cpm2_ioports __iomem *iop = mm_gc->regs; 245 246 cpm2_gc->cpdata = in_be32(&iop->dat); 247 } 248 249 static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio) 250 { 251 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 252 struct cpm2_ioports __iomem *iop = mm_gc->regs; 253 u32 pin_mask; 254 255 pin_mask = 1 << (31 - gpio); 256 257 return !!(in_be32(&iop->dat) & pin_mask); 258 } 259 260 static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask, 261 int value) 262 { 263 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc); 264 struct cpm2_ioports __iomem *iop = mm_gc->regs; 265 266 if (value) 267 cpm2_gc->cpdata |= pin_mask; 268 else 269 cpm2_gc->cpdata &= ~pin_mask; 270 271 out_be32(&iop->dat, cpm2_gc->cpdata); 272 } 273 274 static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value) 275 { 276 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 277 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc); 278 unsigned long flags; 279 u32 pin_mask = 1 << (31 - gpio); 280 281 spin_lock_irqsave(&cpm2_gc->lock, flags); 282 283 __cpm2_gpio32_set(mm_gc, pin_mask, value); 284 285 spin_unlock_irqrestore(&cpm2_gc->lock, flags); 286 } 287 288 static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 289 { 290 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 291 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc); 292 struct cpm2_ioports __iomem *iop = mm_gc->regs; 293 unsigned long flags; 294 u32 pin_mask = 1 << (31 - gpio); 295 296 spin_lock_irqsave(&cpm2_gc->lock, flags); 297 298 setbits32(&iop->dir, pin_mask); 299 __cpm2_gpio32_set(mm_gc, pin_mask, val); 300 301 spin_unlock_irqrestore(&cpm2_gc->lock, flags); 302 303 return 0; 304 } 305 306 static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) 307 { 308 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 309 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc); 310 struct cpm2_ioports __iomem *iop = mm_gc->regs; 311 unsigned long flags; 312 u32 pin_mask = 1 << (31 - gpio); 313 314 spin_lock_irqsave(&cpm2_gc->lock, flags); 315 316 clrbits32(&iop->dir, pin_mask); 317 318 spin_unlock_irqrestore(&cpm2_gc->lock, flags); 319 320 return 0; 321 } 322 323 int cpm2_gpiochip_add32(struct device_node *np) 324 { 325 struct cpm2_gpio32_chip *cpm2_gc; 326 struct of_mm_gpio_chip *mm_gc; 327 struct of_gpio_chip *of_gc; 328 struct gpio_chip *gc; 329 330 cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL); 331 if (!cpm2_gc) 332 return -ENOMEM; 333 334 spin_lock_init(&cpm2_gc->lock); 335 336 mm_gc = &cpm2_gc->mm_gc; 337 of_gc = &mm_gc->of_gc; 338 gc = &of_gc->gc; 339 340 mm_gc->save_regs = cpm2_gpio32_save_regs; 341 of_gc->gpio_cells = 2; 342 gc->ngpio = 32; 343 gc->direction_input = cpm2_gpio32_dir_in; 344 gc->direction_output = cpm2_gpio32_dir_out; 345 gc->get = cpm2_gpio32_get; 346 gc->set = cpm2_gpio32_set; 347 348 return of_mm_gpiochip_add(np, mm_gc); 349 } 350 #endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */ 351