1 /* 2 * Common CPM code 3 * 4 * Author: Scott Wood <scottwood@freescale.com> 5 * 6 * Copyright 2007 Freescale Semiconductor, Inc. 7 * 8 * Some parts derived from commproc.c/cpm2_common.c, which is: 9 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net) 10 * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com> 11 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) 12 * 2006 (c) MontaVista Software, Inc. 13 * Vitaly Bordug <vbordug@ru.mvista.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of version 2 of the GNU General Public License as 17 * published by the Free Software Foundation. 18 */ 19 20 #include <linux/init.h> 21 #include <linux/of_device.h> 22 #include <linux/spinlock.h> 23 #include <linux/of.h> 24 25 #include <asm/udbg.h> 26 #include <asm/io.h> 27 #include <asm/system.h> 28 #include <asm/rheap.h> 29 #include <asm/cpm.h> 30 31 #include <mm/mmu_decl.h> 32 33 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO) 34 #include <linux/of_gpio.h> 35 #endif 36 37 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM 38 static u32 __iomem *cpm_udbg_txdesc = 39 (u32 __iomem __force *)CONFIG_PPC_EARLY_DEBUG_CPM_ADDR; 40 41 static void udbg_putc_cpm(char c) 42 { 43 u8 __iomem *txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]); 44 45 if (c == '\n') 46 udbg_putc_cpm('\r'); 47 48 while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000) 49 ; 50 51 out_8(txbuf, c); 52 out_be32(&cpm_udbg_txdesc[0], 0xa0000001); 53 } 54 55 void __init udbg_init_cpm(void) 56 { 57 if (cpm_udbg_txdesc) { 58 #ifdef CONFIG_CPM2 59 setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG); 60 #endif 61 udbg_putc = udbg_putc_cpm; 62 } 63 } 64 #endif 65 66 static spinlock_t cpm_muram_lock; 67 static rh_block_t cpm_boot_muram_rh_block[16]; 68 static rh_info_t cpm_muram_info; 69 static u8 __iomem *muram_vbase; 70 static phys_addr_t muram_pbase; 71 72 /* Max address size we deal with */ 73 #define OF_MAX_ADDR_CELLS 4 74 75 int __init cpm_muram_init(void) 76 { 77 struct device_node *np; 78 struct resource r; 79 u32 zero[OF_MAX_ADDR_CELLS] = {}; 80 resource_size_t max = 0; 81 int i = 0; 82 int ret = 0; 83 84 spin_lock_init(&cpm_muram_lock); 85 /* initialize the info header */ 86 rh_init(&cpm_muram_info, 1, 87 sizeof(cpm_boot_muram_rh_block) / 88 sizeof(cpm_boot_muram_rh_block[0]), 89 cpm_boot_muram_rh_block); 90 91 np = of_find_compatible_node(NULL, NULL, "fsl,cpm-muram-data"); 92 if (!np) { 93 /* try legacy bindings */ 94 np = of_find_node_by_name(NULL, "data-only"); 95 if (!np) { 96 printk(KERN_ERR "Cannot find CPM muram data node"); 97 ret = -ENODEV; 98 goto out; 99 } 100 } 101 102 muram_pbase = of_translate_address(np, zero); 103 if (muram_pbase == (phys_addr_t)OF_BAD_ADDR) { 104 printk(KERN_ERR "Cannot translate zero through CPM muram node"); 105 ret = -ENODEV; 106 goto out; 107 } 108 109 while (of_address_to_resource(np, i++, &r) == 0) { 110 if (r.end > max) 111 max = r.end; 112 113 rh_attach_region(&cpm_muram_info, r.start - muram_pbase, 114 r.end - r.start + 1); 115 } 116 117 muram_vbase = ioremap(muram_pbase, max - muram_pbase + 1); 118 if (!muram_vbase) { 119 printk(KERN_ERR "Cannot map CPM muram"); 120 ret = -ENOMEM; 121 } 122 123 out: 124 of_node_put(np); 125 return ret; 126 } 127 128 /** 129 * cpm_muram_alloc - allocate the requested size worth of multi-user ram 130 * @size: number of bytes to allocate 131 * @align: requested alignment, in bytes 132 * 133 * This function returns an offset into the muram area. 134 * Use cpm_dpram_addr() to get the virtual address of the area. 135 * Use cpm_muram_free() to free the allocation. 136 */ 137 unsigned long cpm_muram_alloc(unsigned long size, unsigned long align) 138 { 139 unsigned long start; 140 unsigned long flags; 141 142 spin_lock_irqsave(&cpm_muram_lock, flags); 143 cpm_muram_info.alignment = align; 144 start = rh_alloc(&cpm_muram_info, size, "commproc"); 145 spin_unlock_irqrestore(&cpm_muram_lock, flags); 146 147 return start; 148 } 149 EXPORT_SYMBOL(cpm_muram_alloc); 150 151 /** 152 * cpm_muram_free - free a chunk of multi-user ram 153 * @offset: The beginning of the chunk as returned by cpm_muram_alloc(). 154 */ 155 int cpm_muram_free(unsigned long offset) 156 { 157 int ret; 158 unsigned long flags; 159 160 spin_lock_irqsave(&cpm_muram_lock, flags); 161 ret = rh_free(&cpm_muram_info, offset); 162 spin_unlock_irqrestore(&cpm_muram_lock, flags); 163 164 return ret; 165 } 166 EXPORT_SYMBOL(cpm_muram_free); 167 168 /** 169 * cpm_muram_alloc_fixed - reserve a specific region of multi-user ram 170 * @offset: the offset into the muram area to reserve 171 * @size: the number of bytes to reserve 172 * 173 * This function returns "start" on success, -ENOMEM on failure. 174 * Use cpm_dpram_addr() to get the virtual address of the area. 175 * Use cpm_muram_free() to free the allocation. 176 */ 177 unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size) 178 { 179 unsigned long start; 180 unsigned long flags; 181 182 spin_lock_irqsave(&cpm_muram_lock, flags); 183 cpm_muram_info.alignment = 1; 184 start = rh_alloc_fixed(&cpm_muram_info, offset, size, "commproc"); 185 spin_unlock_irqrestore(&cpm_muram_lock, flags); 186 187 return start; 188 } 189 EXPORT_SYMBOL(cpm_muram_alloc_fixed); 190 191 /** 192 * cpm_muram_addr - turn a muram offset into a virtual address 193 * @offset: muram offset to convert 194 */ 195 void __iomem *cpm_muram_addr(unsigned long offset) 196 { 197 return muram_vbase + offset; 198 } 199 EXPORT_SYMBOL(cpm_muram_addr); 200 201 unsigned long cpm_muram_offset(void __iomem *addr) 202 { 203 return addr - (void __iomem *)muram_vbase; 204 } 205 EXPORT_SYMBOL(cpm_muram_offset); 206 207 /** 208 * cpm_muram_dma - turn a muram virtual address into a DMA address 209 * @offset: virtual address from cpm_muram_addr() to convert 210 */ 211 dma_addr_t cpm_muram_dma(void __iomem *addr) 212 { 213 return muram_pbase + ((u8 __iomem *)addr - muram_vbase); 214 } 215 EXPORT_SYMBOL(cpm_muram_dma); 216 217 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO) 218 219 struct cpm2_ioports { 220 u32 dir, par, sor, odr, dat; 221 u32 res[3]; 222 }; 223 224 struct cpm2_gpio32_chip { 225 struct of_mm_gpio_chip mm_gc; 226 spinlock_t lock; 227 228 /* shadowed data register to clear/set bits safely */ 229 u32 cpdata; 230 }; 231 232 static inline struct cpm2_gpio32_chip * 233 to_cpm2_gpio32_chip(struct of_mm_gpio_chip *mm_gc) 234 { 235 return container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc); 236 } 237 238 static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc) 239 { 240 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc); 241 struct cpm2_ioports __iomem *iop = mm_gc->regs; 242 243 cpm2_gc->cpdata = in_be32(&iop->dat); 244 } 245 246 static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio) 247 { 248 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 249 struct cpm2_ioports __iomem *iop = mm_gc->regs; 250 u32 pin_mask; 251 252 pin_mask = 1 << (31 - gpio); 253 254 return !!(in_be32(&iop->dat) & pin_mask); 255 } 256 257 static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask, 258 int value) 259 { 260 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc); 261 struct cpm2_ioports __iomem *iop = mm_gc->regs; 262 263 if (value) 264 cpm2_gc->cpdata |= pin_mask; 265 else 266 cpm2_gc->cpdata &= ~pin_mask; 267 268 out_be32(&iop->dat, cpm2_gc->cpdata); 269 } 270 271 static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value) 272 { 273 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 274 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc); 275 unsigned long flags; 276 u32 pin_mask = 1 << (31 - gpio); 277 278 spin_lock_irqsave(&cpm2_gc->lock, flags); 279 280 __cpm2_gpio32_set(mm_gc, pin_mask, value); 281 282 spin_unlock_irqrestore(&cpm2_gc->lock, flags); 283 } 284 285 static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 286 { 287 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 288 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc); 289 struct cpm2_ioports __iomem *iop = mm_gc->regs; 290 unsigned long flags; 291 u32 pin_mask = 1 << (31 - gpio); 292 293 spin_lock_irqsave(&cpm2_gc->lock, flags); 294 295 setbits32(&iop->dir, pin_mask); 296 __cpm2_gpio32_set(mm_gc, pin_mask, val); 297 298 spin_unlock_irqrestore(&cpm2_gc->lock, flags); 299 300 return 0; 301 } 302 303 static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) 304 { 305 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 306 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc); 307 struct cpm2_ioports __iomem *iop = mm_gc->regs; 308 unsigned long flags; 309 u32 pin_mask = 1 << (31 - gpio); 310 311 spin_lock_irqsave(&cpm2_gc->lock, flags); 312 313 clrbits32(&iop->dir, pin_mask); 314 315 spin_unlock_irqrestore(&cpm2_gc->lock, flags); 316 317 return 0; 318 } 319 320 int cpm2_gpiochip_add32(struct device_node *np) 321 { 322 struct cpm2_gpio32_chip *cpm2_gc; 323 struct of_mm_gpio_chip *mm_gc; 324 struct of_gpio_chip *of_gc; 325 struct gpio_chip *gc; 326 327 cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL); 328 if (!cpm2_gc) 329 return -ENOMEM; 330 331 spin_lock_init(&cpm2_gc->lock); 332 333 mm_gc = &cpm2_gc->mm_gc; 334 of_gc = &mm_gc->of_gc; 335 gc = &of_gc->gc; 336 337 mm_gc->save_regs = cpm2_gpio32_save_regs; 338 of_gc->gpio_cells = 2; 339 gc->ngpio = 32; 340 gc->direction_input = cpm2_gpio32_dir_in; 341 gc->direction_output = cpm2_gpio32_dir_out; 342 gc->get = cpm2_gpio32_get; 343 gc->set = cpm2_gpio32_set; 344 345 return of_mm_gpiochip_add(np, mm_gc); 346 } 347 #endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */ 348