1 /* 2 * Common CPM code 3 * 4 * Author: Scott Wood <scottwood@freescale.com> 5 * 6 * Copyright 2007-2008,2010 Freescale Semiconductor, Inc. 7 * 8 * Some parts derived from commproc.c/cpm2_common.c, which is: 9 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net) 10 * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com> 11 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) 12 * 2006 (c) MontaVista Software, Inc. 13 * Vitaly Bordug <vbordug@ru.mvista.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of version 2 of the GNU General Public License as 17 * published by the Free Software Foundation. 18 */ 19 20 #include <linux/init.h> 21 #include <linux/of_device.h> 22 #include <linux/spinlock.h> 23 #include <linux/export.h> 24 #include <linux/of.h> 25 #include <linux/slab.h> 26 27 #include <asm/udbg.h> 28 #include <asm/io.h> 29 #include <asm/rheap.h> 30 #include <asm/cpm.h> 31 32 #include <mm/mmu_decl.h> 33 34 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO) 35 #include <linux/of_gpio.h> 36 #endif 37 38 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM 39 static u32 __iomem *cpm_udbg_txdesc = 40 (u32 __iomem __force *)CONFIG_PPC_EARLY_DEBUG_CPM_ADDR; 41 42 static void udbg_putc_cpm(char c) 43 { 44 u8 __iomem *txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]); 45 46 if (c == '\n') 47 udbg_putc_cpm('\r'); 48 49 while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000) 50 ; 51 52 out_8(txbuf, c); 53 out_be32(&cpm_udbg_txdesc[0], 0xa0000001); 54 } 55 56 void __init udbg_init_cpm(void) 57 { 58 if (cpm_udbg_txdesc) { 59 #ifdef CONFIG_CPM2 60 setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG); 61 #endif 62 udbg_putc = udbg_putc_cpm; 63 } 64 } 65 #endif 66 67 static spinlock_t cpm_muram_lock; 68 static rh_block_t cpm_boot_muram_rh_block[16]; 69 static rh_info_t cpm_muram_info; 70 static u8 __iomem *muram_vbase; 71 static phys_addr_t muram_pbase; 72 73 /* Max address size we deal with */ 74 #define OF_MAX_ADDR_CELLS 4 75 76 int cpm_muram_init(void) 77 { 78 struct device_node *np; 79 struct resource r; 80 u32 zero[OF_MAX_ADDR_CELLS] = {}; 81 resource_size_t max = 0; 82 int i = 0; 83 int ret = 0; 84 85 if (muram_pbase) 86 return 0; 87 88 spin_lock_init(&cpm_muram_lock); 89 /* initialize the info header */ 90 rh_init(&cpm_muram_info, 1, 91 sizeof(cpm_boot_muram_rh_block) / 92 sizeof(cpm_boot_muram_rh_block[0]), 93 cpm_boot_muram_rh_block); 94 95 np = of_find_compatible_node(NULL, NULL, "fsl,cpm-muram-data"); 96 if (!np) { 97 /* try legacy bindings */ 98 np = of_find_node_by_name(NULL, "data-only"); 99 if (!np) { 100 printk(KERN_ERR "Cannot find CPM muram data node"); 101 ret = -ENODEV; 102 goto out; 103 } 104 } 105 106 muram_pbase = of_translate_address(np, zero); 107 if (muram_pbase == (phys_addr_t)OF_BAD_ADDR) { 108 printk(KERN_ERR "Cannot translate zero through CPM muram node"); 109 ret = -ENODEV; 110 goto out; 111 } 112 113 while (of_address_to_resource(np, i++, &r) == 0) { 114 if (r.end > max) 115 max = r.end; 116 117 rh_attach_region(&cpm_muram_info, r.start - muram_pbase, 118 resource_size(&r)); 119 } 120 121 muram_vbase = ioremap(muram_pbase, max - muram_pbase + 1); 122 if (!muram_vbase) { 123 printk(KERN_ERR "Cannot map CPM muram"); 124 ret = -ENOMEM; 125 } 126 127 out: 128 of_node_put(np); 129 return ret; 130 } 131 132 /** 133 * cpm_muram_alloc - allocate the requested size worth of multi-user ram 134 * @size: number of bytes to allocate 135 * @align: requested alignment, in bytes 136 * 137 * This function returns an offset into the muram area. 138 * Use cpm_dpram_addr() to get the virtual address of the area. 139 * Use cpm_muram_free() to free the allocation. 140 */ 141 unsigned long cpm_muram_alloc(unsigned long size, unsigned long align) 142 { 143 unsigned long start; 144 unsigned long flags; 145 146 spin_lock_irqsave(&cpm_muram_lock, flags); 147 cpm_muram_info.alignment = align; 148 start = rh_alloc(&cpm_muram_info, size, "commproc"); 149 memset(cpm_muram_addr(start), 0, size); 150 spin_unlock_irqrestore(&cpm_muram_lock, flags); 151 152 return start; 153 } 154 EXPORT_SYMBOL(cpm_muram_alloc); 155 156 /** 157 * cpm_muram_free - free a chunk of multi-user ram 158 * @offset: The beginning of the chunk as returned by cpm_muram_alloc(). 159 */ 160 int cpm_muram_free(unsigned long offset) 161 { 162 int ret; 163 unsigned long flags; 164 165 spin_lock_irqsave(&cpm_muram_lock, flags); 166 ret = rh_free(&cpm_muram_info, offset); 167 spin_unlock_irqrestore(&cpm_muram_lock, flags); 168 169 return ret; 170 } 171 EXPORT_SYMBOL(cpm_muram_free); 172 173 /** 174 * cpm_muram_alloc_fixed - reserve a specific region of multi-user ram 175 * @offset: the offset into the muram area to reserve 176 * @size: the number of bytes to reserve 177 * 178 * This function returns "start" on success, -ENOMEM on failure. 179 * Use cpm_dpram_addr() to get the virtual address of the area. 180 * Use cpm_muram_free() to free the allocation. 181 */ 182 unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size) 183 { 184 unsigned long start; 185 unsigned long flags; 186 187 spin_lock_irqsave(&cpm_muram_lock, flags); 188 cpm_muram_info.alignment = 1; 189 start = rh_alloc_fixed(&cpm_muram_info, offset, size, "commproc"); 190 spin_unlock_irqrestore(&cpm_muram_lock, flags); 191 192 return start; 193 } 194 EXPORT_SYMBOL(cpm_muram_alloc_fixed); 195 196 /** 197 * cpm_muram_addr - turn a muram offset into a virtual address 198 * @offset: muram offset to convert 199 */ 200 void __iomem *cpm_muram_addr(unsigned long offset) 201 { 202 return muram_vbase + offset; 203 } 204 EXPORT_SYMBOL(cpm_muram_addr); 205 206 unsigned long cpm_muram_offset(void __iomem *addr) 207 { 208 return addr - (void __iomem *)muram_vbase; 209 } 210 EXPORT_SYMBOL(cpm_muram_offset); 211 212 /** 213 * cpm_muram_dma - turn a muram virtual address into a DMA address 214 * @offset: virtual address from cpm_muram_addr() to convert 215 */ 216 dma_addr_t cpm_muram_dma(void __iomem *addr) 217 { 218 return muram_pbase + ((u8 __iomem *)addr - muram_vbase); 219 } 220 EXPORT_SYMBOL(cpm_muram_dma); 221 222 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO) 223 224 struct cpm2_ioports { 225 u32 dir, par, sor, odr, dat; 226 u32 res[3]; 227 }; 228 229 struct cpm2_gpio32_chip { 230 struct of_mm_gpio_chip mm_gc; 231 spinlock_t lock; 232 233 /* shadowed data register to clear/set bits safely */ 234 u32 cpdata; 235 }; 236 237 static inline struct cpm2_gpio32_chip * 238 to_cpm2_gpio32_chip(struct of_mm_gpio_chip *mm_gc) 239 { 240 return container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc); 241 } 242 243 static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc) 244 { 245 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc); 246 struct cpm2_ioports __iomem *iop = mm_gc->regs; 247 248 cpm2_gc->cpdata = in_be32(&iop->dat); 249 } 250 251 static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio) 252 { 253 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 254 struct cpm2_ioports __iomem *iop = mm_gc->regs; 255 u32 pin_mask; 256 257 pin_mask = 1 << (31 - gpio); 258 259 return !!(in_be32(&iop->dat) & pin_mask); 260 } 261 262 static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask, 263 int value) 264 { 265 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc); 266 struct cpm2_ioports __iomem *iop = mm_gc->regs; 267 268 if (value) 269 cpm2_gc->cpdata |= pin_mask; 270 else 271 cpm2_gc->cpdata &= ~pin_mask; 272 273 out_be32(&iop->dat, cpm2_gc->cpdata); 274 } 275 276 static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value) 277 { 278 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 279 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc); 280 unsigned long flags; 281 u32 pin_mask = 1 << (31 - gpio); 282 283 spin_lock_irqsave(&cpm2_gc->lock, flags); 284 285 __cpm2_gpio32_set(mm_gc, pin_mask, value); 286 287 spin_unlock_irqrestore(&cpm2_gc->lock, flags); 288 } 289 290 static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 291 { 292 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 293 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc); 294 struct cpm2_ioports __iomem *iop = mm_gc->regs; 295 unsigned long flags; 296 u32 pin_mask = 1 << (31 - gpio); 297 298 spin_lock_irqsave(&cpm2_gc->lock, flags); 299 300 setbits32(&iop->dir, pin_mask); 301 __cpm2_gpio32_set(mm_gc, pin_mask, val); 302 303 spin_unlock_irqrestore(&cpm2_gc->lock, flags); 304 305 return 0; 306 } 307 308 static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) 309 { 310 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 311 struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc); 312 struct cpm2_ioports __iomem *iop = mm_gc->regs; 313 unsigned long flags; 314 u32 pin_mask = 1 << (31 - gpio); 315 316 spin_lock_irqsave(&cpm2_gc->lock, flags); 317 318 clrbits32(&iop->dir, pin_mask); 319 320 spin_unlock_irqrestore(&cpm2_gc->lock, flags); 321 322 return 0; 323 } 324 325 int cpm2_gpiochip_add32(struct device_node *np) 326 { 327 struct cpm2_gpio32_chip *cpm2_gc; 328 struct of_mm_gpio_chip *mm_gc; 329 struct gpio_chip *gc; 330 331 cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL); 332 if (!cpm2_gc) 333 return -ENOMEM; 334 335 spin_lock_init(&cpm2_gc->lock); 336 337 mm_gc = &cpm2_gc->mm_gc; 338 gc = &mm_gc->gc; 339 340 mm_gc->save_regs = cpm2_gpio32_save_regs; 341 gc->ngpio = 32; 342 gc->direction_input = cpm2_gpio32_dir_in; 343 gc->direction_output = cpm2_gpio32_dir_out; 344 gc->get = cpm2_gpio32_get; 345 gc->set = cpm2_gpio32_set; 346 347 return of_mm_gpiochip_add(np, mm_gc); 348 } 349 #endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */ 350