1 /* 2 * Platform information definitions. 3 * 4 * Copied from arch/ppc/syslib/cpm2_pic.c with minor subsequent updates 5 * to make in work in arch/powerpc/. Original (c) belongs to Dan Malek. 6 * 7 * Author: Vitaly Bordug <vbordug@ru.mvista.com> 8 * 9 * 1999-2001 (c) Dan Malek <dan@embeddedalley.com> 10 * 2006 (c) MontaVista Software, Inc. 11 * 12 * This file is licensed under the terms of the GNU General Public License 13 * version 2. This program is licensed "as is" without any warranty of any 14 * kind, whether express or implied. 15 */ 16 17 /* The CPM2 internal interrupt controller. It is usually 18 * the only interrupt controller. 19 * There are two 32-bit registers (high/low) for up to 64 20 * possible interrupts. 21 * 22 * Now, the fun starts.....Interrupt Numbers DO NOT MAP 23 * in a simple arithmetic fashion to mask or pending registers. 24 * That is, interrupt 4 does not map to bit position 4. 25 * We create two tables, indexed by vector number, to indicate 26 * which register to use and which bit in the register to use. 27 */ 28 29 #include <linux/stddef.h> 30 #include <linux/init.h> 31 #include <linux/sched.h> 32 #include <linux/signal.h> 33 #include <linux/irq.h> 34 35 #include <asm/immap_cpm2.h> 36 #include <asm/mpc8260.h> 37 #include <asm/io.h> 38 #include <asm/prom.h> 39 #include <asm/fs_pd.h> 40 41 #include "cpm2_pic.h" 42 43 /* External IRQS */ 44 #define CPM2_IRQ_EXT1 19 45 #define CPM2_IRQ_EXT7 25 46 47 /* Port C IRQS */ 48 #define CPM2_IRQ_PORTC15 48 49 #define CPM2_IRQ_PORTC0 63 50 51 static intctl_cpm2_t __iomem *cpm2_intctl; 52 53 static struct irq_domain *cpm2_pic_host; 54 static unsigned long ppc_cached_irq_mask[2]; /* 2 32-bit registers */ 55 56 static const u_char irq_to_siureg[] = { 57 1, 1, 1, 1, 1, 1, 1, 1, 58 1, 1, 1, 1, 1, 1, 1, 1, 59 0, 0, 0, 0, 0, 0, 0, 0, 60 0, 0, 0, 0, 0, 0, 0, 0, 61 1, 1, 1, 1, 1, 1, 1, 1, 62 1, 1, 1, 1, 1, 1, 1, 1, 63 0, 0, 0, 0, 0, 0, 0, 0, 64 0, 0, 0, 0, 0, 0, 0, 0 65 }; 66 67 /* bit numbers do not match the docs, these are precomputed so the bit for 68 * a given irq is (1 << irq_to_siubit[irq]) */ 69 static const u_char irq_to_siubit[] = { 70 0, 15, 14, 13, 12, 11, 10, 9, 71 8, 7, 6, 5, 4, 3, 2, 1, 72 2, 1, 0, 14, 13, 12, 11, 10, 73 9, 8, 7, 6, 5, 4, 3, 0, 74 31, 30, 29, 28, 27, 26, 25, 24, 75 23, 22, 21, 20, 19, 18, 17, 16, 76 16, 17, 18, 19, 20, 21, 22, 23, 77 24, 25, 26, 27, 28, 29, 30, 31, 78 }; 79 80 static void cpm2_mask_irq(struct irq_data *d) 81 { 82 int bit, word; 83 unsigned int irq_nr = irqd_to_hwirq(d); 84 85 bit = irq_to_siubit[irq_nr]; 86 word = irq_to_siureg[irq_nr]; 87 88 ppc_cached_irq_mask[word] &= ~(1 << bit); 89 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]); 90 } 91 92 static void cpm2_unmask_irq(struct irq_data *d) 93 { 94 int bit, word; 95 unsigned int irq_nr = irqd_to_hwirq(d); 96 97 bit = irq_to_siubit[irq_nr]; 98 word = irq_to_siureg[irq_nr]; 99 100 ppc_cached_irq_mask[word] |= 1 << bit; 101 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]); 102 } 103 104 static void cpm2_ack(struct irq_data *d) 105 { 106 int bit, word; 107 unsigned int irq_nr = irqd_to_hwirq(d); 108 109 bit = irq_to_siubit[irq_nr]; 110 word = irq_to_siureg[irq_nr]; 111 112 out_be32(&cpm2_intctl->ic_sipnrh + word, 1 << bit); 113 } 114 115 static void cpm2_end_irq(struct irq_data *d) 116 { 117 int bit, word; 118 unsigned int irq_nr = irqd_to_hwirq(d); 119 120 bit = irq_to_siubit[irq_nr]; 121 word = irq_to_siureg[irq_nr]; 122 123 ppc_cached_irq_mask[word] |= 1 << bit; 124 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]); 125 126 /* 127 * Work around large numbers of spurious IRQs on PowerPC 82xx 128 * systems. 129 */ 130 mb(); 131 } 132 133 static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) 134 { 135 unsigned int src = irqd_to_hwirq(d); 136 unsigned int vold, vnew, edibit; 137 138 /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or 139 * IRQ_TYPE_EDGE_BOTH (default). All others are IRQ_TYPE_EDGE_FALLING 140 * or IRQ_TYPE_LEVEL_LOW (default) 141 */ 142 if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0) { 143 if (flow_type == IRQ_TYPE_NONE) 144 flow_type = IRQ_TYPE_EDGE_BOTH; 145 146 if (flow_type != IRQ_TYPE_EDGE_BOTH && 147 flow_type != IRQ_TYPE_EDGE_FALLING) 148 goto err_sense; 149 } else { 150 if (flow_type == IRQ_TYPE_NONE) 151 flow_type = IRQ_TYPE_LEVEL_LOW; 152 153 if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) 154 goto err_sense; 155 } 156 157 irqd_set_trigger_type(d, flow_type); 158 if (flow_type & IRQ_TYPE_LEVEL_LOW) 159 __irq_set_handler_locked(d->irq, handle_level_irq); 160 else 161 __irq_set_handler_locked(d->irq, handle_edge_irq); 162 163 /* internal IRQ senses are LEVEL_LOW 164 * EXT IRQ and Port C IRQ senses are programmable 165 */ 166 if (src >= CPM2_IRQ_EXT1 && src <= CPM2_IRQ_EXT7) 167 edibit = (14 - (src - CPM2_IRQ_EXT1)); 168 else 169 if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0) 170 edibit = (31 - (CPM2_IRQ_PORTC0 - src)); 171 else 172 return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 173 IRQ_SET_MASK_OK_NOCOPY : -EINVAL; 174 175 vold = in_be32(&cpm2_intctl->ic_siexr); 176 177 if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) 178 vnew = vold | (1 << edibit); 179 else 180 vnew = vold & ~(1 << edibit); 181 182 if (vold != vnew) 183 out_be32(&cpm2_intctl->ic_siexr, vnew); 184 return IRQ_SET_MASK_OK_NOCOPY; 185 186 err_sense: 187 pr_err("CPM2 PIC: sense type 0x%x not supported\n", flow_type); 188 return -EINVAL; 189 } 190 191 static struct irq_chip cpm2_pic = { 192 .name = "CPM2 SIU", 193 .irq_mask = cpm2_mask_irq, 194 .irq_unmask = cpm2_unmask_irq, 195 .irq_ack = cpm2_ack, 196 .irq_eoi = cpm2_end_irq, 197 .irq_set_type = cpm2_set_irq_type, 198 .flags = IRQCHIP_EOI_IF_HANDLED, 199 }; 200 201 unsigned int cpm2_get_irq(void) 202 { 203 int irq; 204 unsigned long bits; 205 206 /* For CPM2, read the SIVEC register and shift the bits down 207 * to get the irq number. */ 208 bits = in_be32(&cpm2_intctl->ic_sivec); 209 irq = bits >> 26; 210 211 if (irq == 0) 212 return(-1); 213 return irq_linear_revmap(cpm2_pic_host, irq); 214 } 215 216 static int cpm2_pic_host_map(struct irq_domain *h, unsigned int virq, 217 irq_hw_number_t hw) 218 { 219 pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw); 220 221 irq_set_status_flags(virq, IRQ_LEVEL); 222 irq_set_chip_and_handler(virq, &cpm2_pic, handle_level_irq); 223 return 0; 224 } 225 226 static const struct irq_domain_ops cpm2_pic_host_ops = { 227 .map = cpm2_pic_host_map, 228 .xlate = irq_domain_xlate_onetwocell, 229 }; 230 231 void cpm2_pic_init(struct device_node *node) 232 { 233 int i; 234 235 cpm2_intctl = cpm2_map(im_intctl); 236 237 /* Clear the CPM IRQ controller, in case it has any bits set 238 * from the bootloader 239 */ 240 241 /* Mask out everything */ 242 243 out_be32(&cpm2_intctl->ic_simrh, 0x00000000); 244 out_be32(&cpm2_intctl->ic_simrl, 0x00000000); 245 246 wmb(); 247 248 /* Ack everything */ 249 out_be32(&cpm2_intctl->ic_sipnrh, 0xffffffff); 250 out_be32(&cpm2_intctl->ic_sipnrl, 0xffffffff); 251 wmb(); 252 253 /* Dummy read of the vector */ 254 i = in_be32(&cpm2_intctl->ic_sivec); 255 rmb(); 256 257 /* Initialize the default interrupt mapping priorities, 258 * in case the boot rom changed something on us. 259 */ 260 out_be16(&cpm2_intctl->ic_sicr, 0); 261 out_be32(&cpm2_intctl->ic_scprrh, 0x05309770); 262 out_be32(&cpm2_intctl->ic_scprrl, 0x05309770); 263 264 /* create a legacy host */ 265 cpm2_pic_host = irq_domain_add_linear(node, 64, &cpm2_pic_host_ops, NULL); 266 if (cpm2_pic_host == NULL) { 267 printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n"); 268 return; 269 } 270 } 271