1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 64-bit pSeries and RS/6000 setup code. 4 * 5 * Copyright (C) 1995 Linus Torvalds 6 * Adapted from 'alpha' version by Gary Thomas 7 * Modified by Cort Dougan (cort@cs.nmt.edu) 8 * Modified by PPC64 Team, IBM Corp 9 */ 10 11 /* 12 * bootup setup stuff.. 13 */ 14 15 #include <linux/cpu.h> 16 #include <linux/errno.h> 17 #include <linux/sched.h> 18 #include <linux/kernel.h> 19 #include <linux/mm.h> 20 #include <linux/stddef.h> 21 #include <linux/unistd.h> 22 #include <linux/user.h> 23 #include <linux/tty.h> 24 #include <linux/major.h> 25 #include <linux/interrupt.h> 26 #include <linux/reboot.h> 27 #include <linux/init.h> 28 #include <linux/ioport.h> 29 #include <linux/console.h> 30 #include <linux/pci.h> 31 #include <linux/utsname.h> 32 #include <linux/adb.h> 33 #include <linux/export.h> 34 #include <linux/delay.h> 35 #include <linux/irq.h> 36 #include <linux/seq_file.h> 37 #include <linux/root_dev.h> 38 #include <linux/of.h> 39 #include <linux/of_pci.h> 40 #include <linux/memblock.h> 41 #include <linux/swiotlb.h> 42 43 #include <asm/mmu.h> 44 #include <asm/processor.h> 45 #include <asm/io.h> 46 #include <asm/pgtable.h> 47 #include <asm/prom.h> 48 #include <asm/rtas.h> 49 #include <asm/pci-bridge.h> 50 #include <asm/iommu.h> 51 #include <asm/dma.h> 52 #include <asm/machdep.h> 53 #include <asm/irq.h> 54 #include <asm/time.h> 55 #include <asm/nvram.h> 56 #include <asm/pmc.h> 57 #include <asm/xics.h> 58 #include <asm/xive.h> 59 #include <asm/ppc-pci.h> 60 #include <asm/i8259.h> 61 #include <asm/udbg.h> 62 #include <asm/smp.h> 63 #include <asm/firmware.h> 64 #include <asm/eeh.h> 65 #include <asm/reg.h> 66 #include <asm/plpar_wrappers.h> 67 #include <asm/kexec.h> 68 #include <asm/isa-bridge.h> 69 #include <asm/security_features.h> 70 #include <asm/asm-const.h> 71 #include <asm/swiotlb.h> 72 #include <asm/svm.h> 73 74 #include "pseries.h" 75 #include "../../../../drivers/pci/pci.h" 76 77 int CMO_PrPSP = -1; 78 int CMO_SecPSP = -1; 79 unsigned long CMO_PageSize = (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K); 80 EXPORT_SYMBOL(CMO_PageSize); 81 82 int fwnmi_active; /* TRUE if an FWNMI handler is present */ 83 84 static void pSeries_show_cpuinfo(struct seq_file *m) 85 { 86 struct device_node *root; 87 const char *model = ""; 88 89 root = of_find_node_by_path("/"); 90 if (root) 91 model = of_get_property(root, "model", NULL); 92 seq_printf(m, "machine\t\t: CHRP %s\n", model); 93 of_node_put(root); 94 if (radix_enabled()) 95 seq_printf(m, "MMU\t\t: Radix\n"); 96 else 97 seq_printf(m, "MMU\t\t: Hash\n"); 98 } 99 100 /* Initialize firmware assisted non-maskable interrupts if 101 * the firmware supports this feature. 102 */ 103 static void __init fwnmi_init(void) 104 { 105 unsigned long system_reset_addr, machine_check_addr; 106 u8 *mce_data_buf; 107 unsigned int i; 108 int nr_cpus = num_possible_cpus(); 109 #ifdef CONFIG_PPC_BOOK3S_64 110 struct slb_entry *slb_ptr; 111 size_t size; 112 #endif 113 114 int ibm_nmi_register = rtas_token("ibm,nmi-register"); 115 if (ibm_nmi_register == RTAS_UNKNOWN_SERVICE) 116 return; 117 118 /* If the kernel's not linked at zero we point the firmware at low 119 * addresses anyway, and use a trampoline to get to the real code. */ 120 system_reset_addr = __pa(system_reset_fwnmi) - PHYSICAL_START; 121 machine_check_addr = __pa(machine_check_fwnmi) - PHYSICAL_START; 122 123 if (0 == rtas_call(ibm_nmi_register, 2, 1, NULL, system_reset_addr, 124 machine_check_addr)) 125 fwnmi_active = 1; 126 127 /* 128 * Allocate a chunk for per cpu buffer to hold rtas errorlog. 129 * It will be used in real mode mce handler, hence it needs to be 130 * below RMA. 131 */ 132 mce_data_buf = memblock_alloc_try_nid_raw(RTAS_ERROR_LOG_MAX * nr_cpus, 133 RTAS_ERROR_LOG_MAX, MEMBLOCK_LOW_LIMIT, 134 ppc64_rma_size, NUMA_NO_NODE); 135 if (!mce_data_buf) 136 panic("Failed to allocate %d bytes below %pa for MCE buffer\n", 137 RTAS_ERROR_LOG_MAX * nr_cpus, &ppc64_rma_size); 138 139 for_each_possible_cpu(i) { 140 paca_ptrs[i]->mce_data_buf = mce_data_buf + 141 (RTAS_ERROR_LOG_MAX * i); 142 } 143 144 #ifdef CONFIG_PPC_BOOK3S_64 145 if (!radix_enabled()) { 146 /* Allocate per cpu area to save old slb contents during MCE */ 147 size = sizeof(struct slb_entry) * mmu_slb_size * nr_cpus; 148 slb_ptr = memblock_alloc_try_nid_raw(size, 149 sizeof(struct slb_entry), MEMBLOCK_LOW_LIMIT, 150 ppc64_rma_size, NUMA_NO_NODE); 151 if (!slb_ptr) 152 panic("Failed to allocate %zu bytes below %pa for slb area\n", 153 size, &ppc64_rma_size); 154 155 for_each_possible_cpu(i) 156 paca_ptrs[i]->mce_faulty_slbs = slb_ptr + (mmu_slb_size * i); 157 } 158 #endif 159 } 160 161 static void pseries_8259_cascade(struct irq_desc *desc) 162 { 163 struct irq_chip *chip = irq_desc_get_chip(desc); 164 unsigned int cascade_irq = i8259_irq(); 165 166 if (cascade_irq) 167 generic_handle_irq(cascade_irq); 168 169 chip->irq_eoi(&desc->irq_data); 170 } 171 172 static void __init pseries_setup_i8259_cascade(void) 173 { 174 struct device_node *np, *old, *found = NULL; 175 unsigned int cascade; 176 const u32 *addrp; 177 unsigned long intack = 0; 178 int naddr; 179 180 for_each_node_by_type(np, "interrupt-controller") { 181 if (of_device_is_compatible(np, "chrp,iic")) { 182 found = np; 183 break; 184 } 185 } 186 187 if (found == NULL) { 188 printk(KERN_DEBUG "pic: no ISA interrupt controller\n"); 189 return; 190 } 191 192 cascade = irq_of_parse_and_map(found, 0); 193 if (!cascade) { 194 printk(KERN_ERR "pic: failed to map cascade interrupt"); 195 return; 196 } 197 pr_debug("pic: cascade mapped to irq %d\n", cascade); 198 199 for (old = of_node_get(found); old != NULL ; old = np) { 200 np = of_get_parent(old); 201 of_node_put(old); 202 if (np == NULL) 203 break; 204 if (!of_node_name_eq(np, "pci")) 205 continue; 206 addrp = of_get_property(np, "8259-interrupt-acknowledge", NULL); 207 if (addrp == NULL) 208 continue; 209 naddr = of_n_addr_cells(np); 210 intack = addrp[naddr-1]; 211 if (naddr > 1) 212 intack |= ((unsigned long)addrp[naddr-2]) << 32; 213 } 214 if (intack) 215 printk(KERN_DEBUG "pic: PCI 8259 intack at 0x%016lx\n", intack); 216 i8259_init(found, intack); 217 of_node_put(found); 218 irq_set_chained_handler(cascade, pseries_8259_cascade); 219 } 220 221 static void __init pseries_init_irq(void) 222 { 223 /* Try using a XIVE if available, otherwise use a XICS */ 224 if (!xive_spapr_init()) { 225 xics_init(); 226 pseries_setup_i8259_cascade(); 227 } 228 } 229 230 static void pseries_lpar_enable_pmcs(void) 231 { 232 unsigned long set, reset; 233 234 set = 1UL << 63; 235 reset = 0; 236 plpar_hcall_norets(H_PERFMON, set, reset); 237 } 238 239 static int pci_dn_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data) 240 { 241 struct of_reconfig_data *rd = data; 242 struct device_node *parent, *np = rd->dn; 243 struct pci_dn *pdn; 244 int err = NOTIFY_OK; 245 246 switch (action) { 247 case OF_RECONFIG_ATTACH_NODE: 248 parent = of_get_parent(np); 249 pdn = parent ? PCI_DN(parent) : NULL; 250 if (pdn) 251 pci_add_device_node_info(pdn->phb, np); 252 253 of_node_put(parent); 254 break; 255 case OF_RECONFIG_DETACH_NODE: 256 pdn = PCI_DN(np); 257 if (pdn) 258 list_del(&pdn->list); 259 break; 260 default: 261 err = NOTIFY_DONE; 262 break; 263 } 264 return err; 265 } 266 267 static struct notifier_block pci_dn_reconfig_nb = { 268 .notifier_call = pci_dn_reconfig_notifier, 269 }; 270 271 struct kmem_cache *dtl_cache; 272 273 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE 274 /* 275 * Allocate space for the dispatch trace log for all possible cpus 276 * and register the buffers with the hypervisor. This is used for 277 * computing time stolen by the hypervisor. 278 */ 279 static int alloc_dispatch_logs(void) 280 { 281 if (!firmware_has_feature(FW_FEATURE_SPLPAR)) 282 return 0; 283 284 if (!dtl_cache) 285 return 0; 286 287 alloc_dtl_buffers(0); 288 289 /* Register the DTL for the current (boot) cpu */ 290 register_dtl_buffer(smp_processor_id()); 291 292 return 0; 293 } 294 #else /* !CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ 295 static inline int alloc_dispatch_logs(void) 296 { 297 return 0; 298 } 299 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ 300 301 static int alloc_dispatch_log_kmem_cache(void) 302 { 303 void (*ctor)(void *) = get_dtl_cache_ctor(); 304 305 dtl_cache = kmem_cache_create("dtl", DISPATCH_LOG_BYTES, 306 DISPATCH_LOG_BYTES, 0, ctor); 307 if (!dtl_cache) { 308 pr_warn("Failed to create dispatch trace log buffer cache\n"); 309 pr_warn("Stolen time statistics will be unreliable\n"); 310 return 0; 311 } 312 313 return alloc_dispatch_logs(); 314 } 315 machine_early_initcall(pseries, alloc_dispatch_log_kmem_cache); 316 317 static void pseries_lpar_idle(void) 318 { 319 /* 320 * Default handler to go into low thread priority and possibly 321 * low power mode by ceding processor to hypervisor 322 */ 323 324 if (!prep_irq_for_idle()) 325 return; 326 327 /* Indicate to hypervisor that we are idle. */ 328 get_lppaca()->idle = 1; 329 330 /* 331 * Yield the processor to the hypervisor. We return if 332 * an external interrupt occurs (which are driven prior 333 * to returning here) or if a prod occurs from another 334 * processor. When returning here, external interrupts 335 * are enabled. 336 */ 337 cede_processor(); 338 339 get_lppaca()->idle = 0; 340 } 341 342 /* 343 * Enable relocation on during exceptions. This has partition wide scope and 344 * may take a while to complete, if it takes longer than one second we will 345 * just give up rather than wasting any more time on this - if that turns out 346 * to ever be a problem in practice we can move this into a kernel thread to 347 * finish off the process later in boot. 348 */ 349 void pseries_enable_reloc_on_exc(void) 350 { 351 long rc; 352 unsigned int delay, total_delay = 0; 353 354 while (1) { 355 rc = enable_reloc_on_exceptions(); 356 if (!H_IS_LONG_BUSY(rc)) { 357 if (rc == H_P2) { 358 pr_info("Relocation on exceptions not" 359 " supported\n"); 360 } else if (rc != H_SUCCESS) { 361 pr_warn("Unable to enable relocation" 362 " on exceptions: %ld\n", rc); 363 } 364 break; 365 } 366 367 delay = get_longbusy_msecs(rc); 368 total_delay += delay; 369 if (total_delay > 1000) { 370 pr_warn("Warning: Giving up waiting to enable " 371 "relocation on exceptions (%u msec)!\n", 372 total_delay); 373 return; 374 } 375 376 mdelay(delay); 377 } 378 } 379 EXPORT_SYMBOL(pseries_enable_reloc_on_exc); 380 381 void pseries_disable_reloc_on_exc(void) 382 { 383 long rc; 384 385 while (1) { 386 rc = disable_reloc_on_exceptions(); 387 if (!H_IS_LONG_BUSY(rc)) 388 break; 389 mdelay(get_longbusy_msecs(rc)); 390 } 391 if (rc != H_SUCCESS) 392 pr_warn("Warning: Failed to disable relocation on exceptions: %ld\n", 393 rc); 394 } 395 EXPORT_SYMBOL(pseries_disable_reloc_on_exc); 396 397 #ifdef CONFIG_KEXEC_CORE 398 static void pSeries_machine_kexec(struct kimage *image) 399 { 400 if (firmware_has_feature(FW_FEATURE_SET_MODE)) 401 pseries_disable_reloc_on_exc(); 402 403 default_machine_kexec(image); 404 } 405 #endif 406 407 #ifdef __LITTLE_ENDIAN__ 408 void pseries_big_endian_exceptions(void) 409 { 410 long rc; 411 412 while (1) { 413 rc = enable_big_endian_exceptions(); 414 if (!H_IS_LONG_BUSY(rc)) 415 break; 416 mdelay(get_longbusy_msecs(rc)); 417 } 418 419 /* 420 * At this point it is unlikely panic() will get anything 421 * out to the user, since this is called very late in kexec 422 * but at least this will stop us from continuing on further 423 * and creating an even more difficult to debug situation. 424 * 425 * There is a known problem when kdump'ing, if cpus are offline 426 * the above call will fail. Rather than panicking again, keep 427 * going and hope the kdump kernel is also little endian, which 428 * it usually is. 429 */ 430 if (rc && !kdump_in_progress()) 431 panic("Could not enable big endian exceptions"); 432 } 433 434 void pseries_little_endian_exceptions(void) 435 { 436 long rc; 437 438 while (1) { 439 rc = enable_little_endian_exceptions(); 440 if (!H_IS_LONG_BUSY(rc)) 441 break; 442 mdelay(get_longbusy_msecs(rc)); 443 } 444 if (rc) { 445 ppc_md.progress("H_SET_MODE LE exception fail", 0); 446 panic("Could not enable little endian exceptions"); 447 } 448 } 449 #endif 450 451 static void __init find_and_init_phbs(void) 452 { 453 struct device_node *node; 454 struct pci_controller *phb; 455 struct device_node *root = of_find_node_by_path("/"); 456 457 for_each_child_of_node(root, node) { 458 if (!of_node_is_type(node, "pci") && 459 !of_node_is_type(node, "pciex")) 460 continue; 461 462 phb = pcibios_alloc_controller(node); 463 if (!phb) 464 continue; 465 rtas_setup_phb(phb); 466 pci_process_bridge_OF_ranges(phb, node, 0); 467 isa_bridge_find_early(phb); 468 phb->controller_ops = pseries_pci_controller_ops; 469 } 470 471 of_node_put(root); 472 473 /* 474 * PCI_PROBE_ONLY and PCI_REASSIGN_ALL_BUS can be set via properties 475 * in chosen. 476 */ 477 of_pci_check_probe_only(); 478 } 479 480 static void init_cpu_char_feature_flags(struct h_cpu_char_result *result) 481 { 482 /* 483 * The features below are disabled by default, so we instead look to see 484 * if firmware has *enabled* them, and set them if so. 485 */ 486 if (result->character & H_CPU_CHAR_SPEC_BAR_ORI31) 487 security_ftr_set(SEC_FTR_SPEC_BAR_ORI31); 488 489 if (result->character & H_CPU_CHAR_BCCTRL_SERIALISED) 490 security_ftr_set(SEC_FTR_BCCTRL_SERIALISED); 491 492 if (result->character & H_CPU_CHAR_L1D_FLUSH_ORI30) 493 security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30); 494 495 if (result->character & H_CPU_CHAR_L1D_FLUSH_TRIG2) 496 security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2); 497 498 if (result->character & H_CPU_CHAR_L1D_THREAD_PRIV) 499 security_ftr_set(SEC_FTR_L1D_THREAD_PRIV); 500 501 if (result->character & H_CPU_CHAR_COUNT_CACHE_DISABLED) 502 security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED); 503 504 if (result->character & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) 505 security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST); 506 507 if (result->behaviour & H_CPU_BEHAV_FLUSH_COUNT_CACHE) 508 security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE); 509 510 /* 511 * The features below are enabled by default, so we instead look to see 512 * if firmware has *disabled* them, and clear them if so. 513 */ 514 if (!(result->behaviour & H_CPU_BEHAV_FAVOUR_SECURITY)) 515 security_ftr_clear(SEC_FTR_FAVOUR_SECURITY); 516 517 if (!(result->behaviour & H_CPU_BEHAV_L1D_FLUSH_PR)) 518 security_ftr_clear(SEC_FTR_L1D_FLUSH_PR); 519 520 if (!(result->behaviour & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR)) 521 security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR); 522 } 523 524 void pseries_setup_rfi_flush(void) 525 { 526 struct h_cpu_char_result result; 527 enum l1d_flush_type types; 528 bool enable; 529 long rc; 530 531 /* 532 * Set features to the defaults assumed by init_cpu_char_feature_flags() 533 * so it can set/clear again any features that might have changed after 534 * migration, and in case the hypercall fails and it is not even called. 535 */ 536 powerpc_security_features = SEC_FTR_DEFAULT; 537 538 rc = plpar_get_cpu_characteristics(&result); 539 if (rc == H_SUCCESS) 540 init_cpu_char_feature_flags(&result); 541 542 /* 543 * We're the guest so this doesn't apply to us, clear it to simplify 544 * handling of it elsewhere. 545 */ 546 security_ftr_clear(SEC_FTR_L1D_FLUSH_HV); 547 548 types = L1D_FLUSH_FALLBACK; 549 550 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2)) 551 types |= L1D_FLUSH_MTTRIG; 552 553 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30)) 554 types |= L1D_FLUSH_ORI; 555 556 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \ 557 security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR); 558 559 setup_rfi_flush(types, enable); 560 setup_count_cache_flush(); 561 } 562 563 #ifdef CONFIG_PCI_IOV 564 enum rtas_iov_fw_value_map { 565 NUM_RES_PROPERTY = 0, /* Number of Resources */ 566 LOW_INT = 1, /* Lowest 32 bits of Address */ 567 START_OF_ENTRIES = 2, /* Always start of entry */ 568 APERTURE_PROPERTY = 2, /* Start of entry+ to Aperture Size */ 569 WDW_SIZE_PROPERTY = 4, /* Start of entry+ to Window Size */ 570 NEXT_ENTRY = 7 /* Go to next entry on array */ 571 }; 572 573 enum get_iov_fw_value_index { 574 BAR_ADDRS = 1, /* Get Bar Address */ 575 APERTURE_SIZE = 2, /* Get Aperture Size */ 576 WDW_SIZE = 3 /* Get Window Size */ 577 }; 578 579 resource_size_t pseries_get_iov_fw_value(struct pci_dev *dev, int resno, 580 enum get_iov_fw_value_index value) 581 { 582 const int *indexes; 583 struct device_node *dn = pci_device_to_OF_node(dev); 584 int i, num_res, ret = 0; 585 586 indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL); 587 if (!indexes) 588 return 0; 589 590 /* 591 * First element in the array is the number of Bars 592 * returned. Search through the list to find the matching 593 * bar 594 */ 595 num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1); 596 if (resno >= num_res) 597 return 0; /* or an errror */ 598 599 i = START_OF_ENTRIES + NEXT_ENTRY * resno; 600 switch (value) { 601 case BAR_ADDRS: 602 ret = of_read_number(&indexes[i], 2); 603 break; 604 case APERTURE_SIZE: 605 ret = of_read_number(&indexes[i + APERTURE_PROPERTY], 2); 606 break; 607 case WDW_SIZE: 608 ret = of_read_number(&indexes[i + WDW_SIZE_PROPERTY], 2); 609 break; 610 } 611 612 return ret; 613 } 614 615 void of_pci_set_vf_bar_size(struct pci_dev *dev, const int *indexes) 616 { 617 struct resource *res; 618 resource_size_t base, size; 619 int i, r, num_res; 620 621 num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1); 622 num_res = min_t(int, num_res, PCI_SRIOV_NUM_BARS); 623 for (i = START_OF_ENTRIES, r = 0; r < num_res && r < PCI_SRIOV_NUM_BARS; 624 i += NEXT_ENTRY, r++) { 625 res = &dev->resource[r + PCI_IOV_RESOURCES]; 626 base = of_read_number(&indexes[i], 2); 627 size = of_read_number(&indexes[i + APERTURE_PROPERTY], 2); 628 res->flags = pci_parse_of_flags(of_read_number 629 (&indexes[i + LOW_INT], 1), 0); 630 res->flags |= (IORESOURCE_MEM_64 | IORESOURCE_PCI_FIXED); 631 res->name = pci_name(dev); 632 res->start = base; 633 res->end = base + size - 1; 634 } 635 } 636 637 void of_pci_parse_iov_addrs(struct pci_dev *dev, const int *indexes) 638 { 639 struct resource *res, *root, *conflict; 640 resource_size_t base, size; 641 int i, r, num_res; 642 643 /* 644 * First element in the array is the number of Bars 645 * returned. Search through the list to find the matching 646 * bars assign them from firmware into resources structure. 647 */ 648 num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1); 649 for (i = START_OF_ENTRIES, r = 0; r < num_res && r < PCI_SRIOV_NUM_BARS; 650 i += NEXT_ENTRY, r++) { 651 res = &dev->resource[r + PCI_IOV_RESOURCES]; 652 base = of_read_number(&indexes[i], 2); 653 size = of_read_number(&indexes[i + WDW_SIZE_PROPERTY], 2); 654 res->name = pci_name(dev); 655 res->start = base; 656 res->end = base + size - 1; 657 root = &iomem_resource; 658 dev_dbg(&dev->dev, 659 "pSeries IOV BAR %d: trying firmware assignment %pR\n", 660 r + PCI_IOV_RESOURCES, res); 661 conflict = request_resource_conflict(root, res); 662 if (conflict) { 663 dev_info(&dev->dev, 664 "BAR %d: %pR conflicts with %s %pR\n", 665 r + PCI_IOV_RESOURCES, res, 666 conflict->name, conflict); 667 res->flags |= IORESOURCE_UNSET; 668 } 669 } 670 } 671 672 static void pseries_disable_sriov_resources(struct pci_dev *pdev) 673 { 674 int i; 675 676 pci_warn(pdev, "No hypervisor support for SR-IOV on this device, IOV BARs disabled.\n"); 677 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 678 pdev->resource[i + PCI_IOV_RESOURCES].flags = 0; 679 } 680 681 static void pseries_pci_fixup_resources(struct pci_dev *pdev) 682 { 683 const int *indexes; 684 struct device_node *dn = pci_device_to_OF_node(pdev); 685 686 /*Firmware must support open sriov otherwise dont configure*/ 687 indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL); 688 if (indexes) 689 of_pci_set_vf_bar_size(pdev, indexes); 690 else 691 pseries_disable_sriov_resources(pdev); 692 } 693 694 static void pseries_pci_fixup_iov_resources(struct pci_dev *pdev) 695 { 696 const int *indexes; 697 struct device_node *dn = pci_device_to_OF_node(pdev); 698 699 if (!pdev->is_physfn || pci_dev_is_added(pdev)) 700 return; 701 /*Firmware must support open sriov otherwise dont configure*/ 702 indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL); 703 if (indexes) 704 of_pci_parse_iov_addrs(pdev, indexes); 705 else 706 pseries_disable_sriov_resources(pdev); 707 } 708 709 static resource_size_t pseries_pci_iov_resource_alignment(struct pci_dev *pdev, 710 int resno) 711 { 712 const __be32 *reg; 713 struct device_node *dn = pci_device_to_OF_node(pdev); 714 715 /*Firmware must support open sriov otherwise report regular alignment*/ 716 reg = of_get_property(dn, "ibm,is-open-sriov-pf", NULL); 717 if (!reg) 718 return pci_iov_resource_size(pdev, resno); 719 720 if (!pdev->is_physfn) 721 return 0; 722 return pseries_get_iov_fw_value(pdev, 723 resno - PCI_IOV_RESOURCES, 724 APERTURE_SIZE); 725 } 726 #endif 727 728 static void __init pSeries_setup_arch(void) 729 { 730 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT); 731 732 /* Discover PIC type and setup ppc_md accordingly */ 733 smp_init_pseries(); 734 735 736 /* openpic global configuration register (64-bit format). */ 737 /* openpic Interrupt Source Unit pointer (64-bit format). */ 738 /* python0 facility area (mmio) (64-bit format) REAL address. */ 739 740 /* init to some ~sane value until calibrate_delay() runs */ 741 loops_per_jiffy = 50000000; 742 743 fwnmi_init(); 744 745 pseries_setup_rfi_flush(); 746 setup_stf_barrier(); 747 748 /* By default, only probe PCI (can be overridden by rtas_pci) */ 749 pci_add_flags(PCI_PROBE_ONLY); 750 751 /* Find and initialize PCI host bridges */ 752 init_pci_config_tokens(); 753 find_and_init_phbs(); 754 of_reconfig_notifier_register(&pci_dn_reconfig_nb); 755 756 pSeries_nvram_init(); 757 758 if (firmware_has_feature(FW_FEATURE_LPAR)) { 759 vpa_init(boot_cpuid); 760 ppc_md.power_save = pseries_lpar_idle; 761 ppc_md.enable_pmcs = pseries_lpar_enable_pmcs; 762 #ifdef CONFIG_PCI_IOV 763 ppc_md.pcibios_fixup_resources = 764 pseries_pci_fixup_resources; 765 ppc_md.pcibios_fixup_sriov = 766 pseries_pci_fixup_iov_resources; 767 ppc_md.pcibios_iov_resource_alignment = 768 pseries_pci_iov_resource_alignment; 769 #endif 770 } else { 771 /* No special idle routine */ 772 ppc_md.enable_pmcs = power4_enable_pmcs; 773 } 774 775 ppc_md.pcibios_root_bridge_prepare = pseries_root_bridge_prepare; 776 777 if (swiotlb_force == SWIOTLB_FORCE) 778 ppc_swiotlb_enable = 1; 779 } 780 781 static void pseries_panic(char *str) 782 { 783 panic_flush_kmsg_end(); 784 rtas_os_term(str); 785 } 786 787 static int __init pSeries_init_panel(void) 788 { 789 /* Manually leave the kernel version on the panel. */ 790 #ifdef __BIG_ENDIAN__ 791 ppc_md.progress("Linux ppc64\n", 0); 792 #else 793 ppc_md.progress("Linux ppc64le\n", 0); 794 #endif 795 ppc_md.progress(init_utsname()->version, 0); 796 797 return 0; 798 } 799 machine_arch_initcall(pseries, pSeries_init_panel); 800 801 static int pseries_set_dabr(unsigned long dabr, unsigned long dabrx) 802 { 803 return plpar_hcall_norets(H_SET_DABR, dabr); 804 } 805 806 static int pseries_set_xdabr(unsigned long dabr, unsigned long dabrx) 807 { 808 /* Have to set at least one bit in the DABRX according to PAPR */ 809 if (dabrx == 0 && dabr == 0) 810 dabrx = DABRX_USER; 811 /* PAPR says we can only set kernel and user bits */ 812 dabrx &= DABRX_KERNEL | DABRX_USER; 813 814 return plpar_hcall_norets(H_SET_XDABR, dabr, dabrx); 815 } 816 817 static int pseries_set_dawr(unsigned long dawr, unsigned long dawrx) 818 { 819 /* PAPR says we can't set HYP */ 820 dawrx &= ~DAWRX_HYP; 821 822 return plpar_set_watchpoint0(dawr, dawrx); 823 } 824 825 #define CMO_CHARACTERISTICS_TOKEN 44 826 #define CMO_MAXLENGTH 1026 827 828 void pSeries_coalesce_init(void) 829 { 830 struct hvcall_mpp_x_data mpp_x_data; 831 832 if (firmware_has_feature(FW_FEATURE_CMO) && !h_get_mpp_x(&mpp_x_data)) 833 powerpc_firmware_features |= FW_FEATURE_XCMO; 834 else 835 powerpc_firmware_features &= ~FW_FEATURE_XCMO; 836 } 837 838 /** 839 * fw_cmo_feature_init - FW_FEATURE_CMO is not stored in ibm,hypertas-functions, 840 * handle that here. (Stolen from parse_system_parameter_string) 841 */ 842 static void pSeries_cmo_feature_init(void) 843 { 844 char *ptr, *key, *value, *end; 845 int call_status; 846 int page_order = IOMMU_PAGE_SHIFT_4K; 847 848 pr_debug(" -> fw_cmo_feature_init()\n"); 849 spin_lock(&rtas_data_buf_lock); 850 memset(rtas_data_buf, 0, RTAS_DATA_BUF_SIZE); 851 call_status = rtas_call(rtas_token("ibm,get-system-parameter"), 3, 1, 852 NULL, 853 CMO_CHARACTERISTICS_TOKEN, 854 __pa(rtas_data_buf), 855 RTAS_DATA_BUF_SIZE); 856 857 if (call_status != 0) { 858 spin_unlock(&rtas_data_buf_lock); 859 pr_debug("CMO not available\n"); 860 pr_debug(" <- fw_cmo_feature_init()\n"); 861 return; 862 } 863 864 end = rtas_data_buf + CMO_MAXLENGTH - 2; 865 ptr = rtas_data_buf + 2; /* step over strlen value */ 866 key = value = ptr; 867 868 while (*ptr && (ptr <= end)) { 869 /* Separate the key and value by replacing '=' with '\0' and 870 * point the value at the string after the '=' 871 */ 872 if (ptr[0] == '=') { 873 ptr[0] = '\0'; 874 value = ptr + 1; 875 } else if (ptr[0] == '\0' || ptr[0] == ',') { 876 /* Terminate the string containing the key/value pair */ 877 ptr[0] = '\0'; 878 879 if (key == value) { 880 pr_debug("Malformed key/value pair\n"); 881 /* Never found a '=', end processing */ 882 break; 883 } 884 885 if (0 == strcmp(key, "CMOPageSize")) 886 page_order = simple_strtol(value, NULL, 10); 887 else if (0 == strcmp(key, "PrPSP")) 888 CMO_PrPSP = simple_strtol(value, NULL, 10); 889 else if (0 == strcmp(key, "SecPSP")) 890 CMO_SecPSP = simple_strtol(value, NULL, 10); 891 value = key = ptr + 1; 892 } 893 ptr++; 894 } 895 896 /* Page size is returned as the power of 2 of the page size, 897 * convert to the page size in bytes before returning 898 */ 899 CMO_PageSize = 1 << page_order; 900 pr_debug("CMO_PageSize = %lu\n", CMO_PageSize); 901 902 if (CMO_PrPSP != -1 || CMO_SecPSP != -1) { 903 pr_info("CMO enabled\n"); 904 pr_debug("CMO enabled, PrPSP=%d, SecPSP=%d\n", CMO_PrPSP, 905 CMO_SecPSP); 906 powerpc_firmware_features |= FW_FEATURE_CMO; 907 pSeries_coalesce_init(); 908 } else 909 pr_debug("CMO not enabled, PrPSP=%d, SecPSP=%d\n", CMO_PrPSP, 910 CMO_SecPSP); 911 spin_unlock(&rtas_data_buf_lock); 912 pr_debug(" <- fw_cmo_feature_init()\n"); 913 } 914 915 /* 916 * Early initialization. Relocation is on but do not reference unbolted pages 917 */ 918 static void __init pseries_init(void) 919 { 920 pr_debug(" -> pseries_init()\n"); 921 922 #ifdef CONFIG_HVC_CONSOLE 923 if (firmware_has_feature(FW_FEATURE_LPAR)) 924 hvc_vio_init_early(); 925 #endif 926 if (firmware_has_feature(FW_FEATURE_XDABR)) 927 ppc_md.set_dabr = pseries_set_xdabr; 928 else if (firmware_has_feature(FW_FEATURE_DABR)) 929 ppc_md.set_dabr = pseries_set_dabr; 930 931 if (firmware_has_feature(FW_FEATURE_SET_MODE)) 932 ppc_md.set_dawr = pseries_set_dawr; 933 934 pSeries_cmo_feature_init(); 935 iommu_init_early_pSeries(); 936 937 pr_debug(" <- pseries_init()\n"); 938 } 939 940 /** 941 * pseries_power_off - tell firmware about how to power off the system. 942 * 943 * This function calls either the power-off rtas token in normal cases 944 * or the ibm,power-off-ups token (if present & requested) in case of 945 * a power failure. If power-off token is used, power on will only be 946 * possible with power button press. If ibm,power-off-ups token is used 947 * it will allow auto poweron after power is restored. 948 */ 949 static void pseries_power_off(void) 950 { 951 int rc; 952 int rtas_poweroff_ups_token = rtas_token("ibm,power-off-ups"); 953 954 if (rtas_flash_term_hook) 955 rtas_flash_term_hook(SYS_POWER_OFF); 956 957 if (rtas_poweron_auto == 0 || 958 rtas_poweroff_ups_token == RTAS_UNKNOWN_SERVICE) { 959 rc = rtas_call(rtas_token("power-off"), 2, 1, NULL, -1, -1); 960 printk(KERN_INFO "RTAS power-off returned %d\n", rc); 961 } else { 962 rc = rtas_call(rtas_poweroff_ups_token, 0, 1, NULL); 963 printk(KERN_INFO "RTAS ibm,power-off-ups returned %d\n", rc); 964 } 965 for (;;); 966 } 967 968 static int __init pSeries_probe(void) 969 { 970 if (!of_node_is_type(of_root, "chrp")) 971 return 0; 972 973 /* Cell blades firmware claims to be chrp while it's not. Until this 974 * is fixed, we need to avoid those here. 975 */ 976 if (of_machine_is_compatible("IBM,CPBW-1.0") || 977 of_machine_is_compatible("IBM,CBEA")) 978 return 0; 979 980 pm_power_off = pseries_power_off; 981 982 pr_debug("Machine is%s LPAR !\n", 983 (powerpc_firmware_features & FW_FEATURE_LPAR) ? "" : " not"); 984 985 pseries_init(); 986 987 return 1; 988 } 989 990 static int pSeries_pci_probe_mode(struct pci_bus *bus) 991 { 992 if (firmware_has_feature(FW_FEATURE_LPAR)) 993 return PCI_PROBE_DEVTREE; 994 return PCI_PROBE_NORMAL; 995 } 996 997 struct pci_controller_ops pseries_pci_controller_ops = { 998 .probe_mode = pSeries_pci_probe_mode, 999 }; 1000 1001 define_machine(pseries) { 1002 .name = "pSeries", 1003 .probe = pSeries_probe, 1004 .setup_arch = pSeries_setup_arch, 1005 .init_IRQ = pseries_init_irq, 1006 .show_cpuinfo = pSeries_show_cpuinfo, 1007 .log_error = pSeries_log_error, 1008 .pcibios_fixup = pSeries_final_fixup, 1009 .restart = rtas_restart, 1010 .halt = rtas_halt, 1011 .panic = pseries_panic, 1012 .get_boot_time = rtas_get_boot_time, 1013 .get_rtc_time = rtas_get_rtc_time, 1014 .set_rtc_time = rtas_set_rtc_time, 1015 .calibrate_decr = generic_calibrate_decr, 1016 .progress = rtas_progress, 1017 .system_reset_exception = pSeries_system_reset_exception, 1018 .machine_check_early = pseries_machine_check_realmode, 1019 .machine_check_exception = pSeries_machine_check_exception, 1020 #ifdef CONFIG_KEXEC_CORE 1021 .machine_kexec = pSeries_machine_kexec, 1022 .kexec_cpu_down = pseries_kexec_cpu_down, 1023 #endif 1024 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE 1025 .memory_block_size = pseries_memory_block_size, 1026 #endif 1027 }; 1028