1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 64-bit pSeries and RS/6000 setup code. 4 * 5 * Copyright (C) 1995 Linus Torvalds 6 * Adapted from 'alpha' version by Gary Thomas 7 * Modified by Cort Dougan (cort@cs.nmt.edu) 8 * Modified by PPC64 Team, IBM Corp 9 */ 10 11 /* 12 * bootup setup stuff.. 13 */ 14 15 #include <linux/cpu.h> 16 #include <linux/errno.h> 17 #include <linux/sched.h> 18 #include <linux/kernel.h> 19 #include <linux/mm.h> 20 #include <linux/stddef.h> 21 #include <linux/unistd.h> 22 #include <linux/user.h> 23 #include <linux/tty.h> 24 #include <linux/major.h> 25 #include <linux/interrupt.h> 26 #include <linux/reboot.h> 27 #include <linux/init.h> 28 #include <linux/ioport.h> 29 #include <linux/console.h> 30 #include <linux/pci.h> 31 #include <linux/utsname.h> 32 #include <linux/adb.h> 33 #include <linux/export.h> 34 #include <linux/delay.h> 35 #include <linux/irq.h> 36 #include <linux/seq_file.h> 37 #include <linux/root_dev.h> 38 #include <linux/of.h> 39 #include <linux/of_pci.h> 40 #include <linux/memblock.h> 41 #include <linux/swiotlb.h> 42 43 #include <asm/mmu.h> 44 #include <asm/processor.h> 45 #include <asm/io.h> 46 #include <asm/prom.h> 47 #include <asm/rtas.h> 48 #include <asm/pci-bridge.h> 49 #include <asm/iommu.h> 50 #include <asm/dma.h> 51 #include <asm/machdep.h> 52 #include <asm/irq.h> 53 #include <asm/time.h> 54 #include <asm/nvram.h> 55 #include <asm/pmc.h> 56 #include <asm/xics.h> 57 #include <asm/xive.h> 58 #include <asm/ppc-pci.h> 59 #include <asm/i8259.h> 60 #include <asm/udbg.h> 61 #include <asm/smp.h> 62 #include <asm/firmware.h> 63 #include <asm/eeh.h> 64 #include <asm/reg.h> 65 #include <asm/plpar_wrappers.h> 66 #include <asm/kexec.h> 67 #include <asm/isa-bridge.h> 68 #include <asm/security_features.h> 69 #include <asm/asm-const.h> 70 #include <asm/idle.h> 71 #include <asm/swiotlb.h> 72 #include <asm/svm.h> 73 #include <asm/dtl.h> 74 #include <asm/hvconsole.h> 75 76 #include "pseries.h" 77 #include "../../../../drivers/pci/pci.h" 78 79 DEFINE_STATIC_KEY_FALSE(shared_processor); 80 EXPORT_SYMBOL_GPL(shared_processor); 81 82 int CMO_PrPSP = -1; 83 int CMO_SecPSP = -1; 84 unsigned long CMO_PageSize = (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K); 85 EXPORT_SYMBOL(CMO_PageSize); 86 87 int fwnmi_active; /* TRUE if an FWNMI handler is present */ 88 int ibm_nmi_interlock_token; 89 u32 pseries_security_flavor; 90 91 static void pSeries_show_cpuinfo(struct seq_file *m) 92 { 93 struct device_node *root; 94 const char *model = ""; 95 96 root = of_find_node_by_path("/"); 97 if (root) 98 model = of_get_property(root, "model", NULL); 99 seq_printf(m, "machine\t\t: CHRP %s\n", model); 100 of_node_put(root); 101 if (radix_enabled()) 102 seq_printf(m, "MMU\t\t: Radix\n"); 103 else 104 seq_printf(m, "MMU\t\t: Hash\n"); 105 } 106 107 /* Initialize firmware assisted non-maskable interrupts if 108 * the firmware supports this feature. 109 */ 110 static void __init fwnmi_init(void) 111 { 112 unsigned long system_reset_addr, machine_check_addr; 113 u8 *mce_data_buf; 114 unsigned int i; 115 int nr_cpus = num_possible_cpus(); 116 #ifdef CONFIG_PPC_BOOK3S_64 117 struct slb_entry *slb_ptr; 118 size_t size; 119 #endif 120 int ibm_nmi_register_token; 121 122 ibm_nmi_register_token = rtas_token("ibm,nmi-register"); 123 if (ibm_nmi_register_token == RTAS_UNKNOWN_SERVICE) 124 return; 125 126 ibm_nmi_interlock_token = rtas_token("ibm,nmi-interlock"); 127 if (WARN_ON(ibm_nmi_interlock_token == RTAS_UNKNOWN_SERVICE)) 128 return; 129 130 /* If the kernel's not linked at zero we point the firmware at low 131 * addresses anyway, and use a trampoline to get to the real code. */ 132 system_reset_addr = __pa(system_reset_fwnmi) - PHYSICAL_START; 133 machine_check_addr = __pa(machine_check_fwnmi) - PHYSICAL_START; 134 135 if (0 == rtas_call(ibm_nmi_register_token, 2, 1, NULL, 136 system_reset_addr, machine_check_addr)) 137 fwnmi_active = 1; 138 139 /* 140 * Allocate a chunk for per cpu buffer to hold rtas errorlog. 141 * It will be used in real mode mce handler, hence it needs to be 142 * below RMA. 143 */ 144 mce_data_buf = memblock_alloc_try_nid_raw(RTAS_ERROR_LOG_MAX * nr_cpus, 145 RTAS_ERROR_LOG_MAX, MEMBLOCK_LOW_LIMIT, 146 ppc64_rma_size, NUMA_NO_NODE); 147 if (!mce_data_buf) 148 panic("Failed to allocate %d bytes below %pa for MCE buffer\n", 149 RTAS_ERROR_LOG_MAX * nr_cpus, &ppc64_rma_size); 150 151 for_each_possible_cpu(i) { 152 paca_ptrs[i]->mce_data_buf = mce_data_buf + 153 (RTAS_ERROR_LOG_MAX * i); 154 } 155 156 #ifdef CONFIG_PPC_BOOK3S_64 157 if (!radix_enabled()) { 158 /* Allocate per cpu area to save old slb contents during MCE */ 159 size = sizeof(struct slb_entry) * mmu_slb_size * nr_cpus; 160 slb_ptr = memblock_alloc_try_nid_raw(size, 161 sizeof(struct slb_entry), MEMBLOCK_LOW_LIMIT, 162 ppc64_rma_size, NUMA_NO_NODE); 163 if (!slb_ptr) 164 panic("Failed to allocate %zu bytes below %pa for slb area\n", 165 size, &ppc64_rma_size); 166 167 for_each_possible_cpu(i) 168 paca_ptrs[i]->mce_faulty_slbs = slb_ptr + (mmu_slb_size * i); 169 } 170 #endif 171 } 172 173 static void pseries_8259_cascade(struct irq_desc *desc) 174 { 175 struct irq_chip *chip = irq_desc_get_chip(desc); 176 unsigned int cascade_irq = i8259_irq(); 177 178 if (cascade_irq) 179 generic_handle_irq(cascade_irq); 180 181 chip->irq_eoi(&desc->irq_data); 182 } 183 184 static void __init pseries_setup_i8259_cascade(void) 185 { 186 struct device_node *np, *old, *found = NULL; 187 unsigned int cascade; 188 const u32 *addrp; 189 unsigned long intack = 0; 190 int naddr; 191 192 for_each_node_by_type(np, "interrupt-controller") { 193 if (of_device_is_compatible(np, "chrp,iic")) { 194 found = np; 195 break; 196 } 197 } 198 199 if (found == NULL) { 200 printk(KERN_DEBUG "pic: no ISA interrupt controller\n"); 201 return; 202 } 203 204 cascade = irq_of_parse_and_map(found, 0); 205 if (!cascade) { 206 printk(KERN_ERR "pic: failed to map cascade interrupt"); 207 return; 208 } 209 pr_debug("pic: cascade mapped to irq %d\n", cascade); 210 211 for (old = of_node_get(found); old != NULL ; old = np) { 212 np = of_get_parent(old); 213 of_node_put(old); 214 if (np == NULL) 215 break; 216 if (!of_node_name_eq(np, "pci")) 217 continue; 218 addrp = of_get_property(np, "8259-interrupt-acknowledge", NULL); 219 if (addrp == NULL) 220 continue; 221 naddr = of_n_addr_cells(np); 222 intack = addrp[naddr-1]; 223 if (naddr > 1) 224 intack |= ((unsigned long)addrp[naddr-2]) << 32; 225 } 226 if (intack) 227 printk(KERN_DEBUG "pic: PCI 8259 intack at 0x%016lx\n", intack); 228 i8259_init(found, intack); 229 of_node_put(found); 230 irq_set_chained_handler(cascade, pseries_8259_cascade); 231 } 232 233 static void __init pseries_init_irq(void) 234 { 235 /* Try using a XIVE if available, otherwise use a XICS */ 236 if (!xive_spapr_init()) { 237 xics_init(); 238 pseries_setup_i8259_cascade(); 239 } 240 } 241 242 static void pseries_lpar_enable_pmcs(void) 243 { 244 unsigned long set, reset; 245 246 set = 1UL << 63; 247 reset = 0; 248 plpar_hcall_norets(H_PERFMON, set, reset); 249 } 250 251 static int pci_dn_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data) 252 { 253 struct of_reconfig_data *rd = data; 254 struct device_node *parent, *np = rd->dn; 255 struct pci_dn *pdn; 256 int err = NOTIFY_OK; 257 258 switch (action) { 259 case OF_RECONFIG_ATTACH_NODE: 260 parent = of_get_parent(np); 261 pdn = parent ? PCI_DN(parent) : NULL; 262 if (pdn) 263 pci_add_device_node_info(pdn->phb, np); 264 265 of_node_put(parent); 266 break; 267 case OF_RECONFIG_DETACH_NODE: 268 pdn = PCI_DN(np); 269 if (pdn) 270 list_del(&pdn->list); 271 break; 272 default: 273 err = NOTIFY_DONE; 274 break; 275 } 276 return err; 277 } 278 279 static struct notifier_block pci_dn_reconfig_nb = { 280 .notifier_call = pci_dn_reconfig_notifier, 281 }; 282 283 struct kmem_cache *dtl_cache; 284 285 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE 286 /* 287 * Allocate space for the dispatch trace log for all possible cpus 288 * and register the buffers with the hypervisor. This is used for 289 * computing time stolen by the hypervisor. 290 */ 291 static int alloc_dispatch_logs(void) 292 { 293 if (!firmware_has_feature(FW_FEATURE_SPLPAR)) 294 return 0; 295 296 if (!dtl_cache) 297 return 0; 298 299 alloc_dtl_buffers(0); 300 301 /* Register the DTL for the current (boot) cpu */ 302 register_dtl_buffer(smp_processor_id()); 303 304 return 0; 305 } 306 #else /* !CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ 307 static inline int alloc_dispatch_logs(void) 308 { 309 return 0; 310 } 311 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ 312 313 static int alloc_dispatch_log_kmem_cache(void) 314 { 315 void (*ctor)(void *) = get_dtl_cache_ctor(); 316 317 dtl_cache = kmem_cache_create("dtl", DISPATCH_LOG_BYTES, 318 DISPATCH_LOG_BYTES, 0, ctor); 319 if (!dtl_cache) { 320 pr_warn("Failed to create dispatch trace log buffer cache\n"); 321 pr_warn("Stolen time statistics will be unreliable\n"); 322 return 0; 323 } 324 325 return alloc_dispatch_logs(); 326 } 327 machine_early_initcall(pseries, alloc_dispatch_log_kmem_cache); 328 329 DEFINE_PER_CPU(u64, idle_spurr_cycles); 330 DEFINE_PER_CPU(u64, idle_entry_purr_snap); 331 DEFINE_PER_CPU(u64, idle_entry_spurr_snap); 332 static void pseries_lpar_idle(void) 333 { 334 /* 335 * Default handler to go into low thread priority and possibly 336 * low power mode by ceding processor to hypervisor 337 */ 338 339 if (!prep_irq_for_idle()) 340 return; 341 342 /* Indicate to hypervisor that we are idle. */ 343 pseries_idle_prolog(); 344 345 /* 346 * Yield the processor to the hypervisor. We return if 347 * an external interrupt occurs (which are driven prior 348 * to returning here) or if a prod occurs from another 349 * processor. When returning here, external interrupts 350 * are enabled. 351 */ 352 cede_processor(); 353 354 pseries_idle_epilog(); 355 } 356 357 /* 358 * Enable relocation on during exceptions. This has partition wide scope and 359 * may take a while to complete, if it takes longer than one second we will 360 * just give up rather than wasting any more time on this - if that turns out 361 * to ever be a problem in practice we can move this into a kernel thread to 362 * finish off the process later in boot. 363 */ 364 bool pseries_enable_reloc_on_exc(void) 365 { 366 long rc; 367 unsigned int delay, total_delay = 0; 368 369 while (1) { 370 rc = enable_reloc_on_exceptions(); 371 if (!H_IS_LONG_BUSY(rc)) { 372 if (rc == H_P2) { 373 pr_info("Relocation on exceptions not" 374 " supported\n"); 375 return false; 376 } else if (rc != H_SUCCESS) { 377 pr_warn("Unable to enable relocation" 378 " on exceptions: %ld\n", rc); 379 return false; 380 } 381 return true; 382 } 383 384 delay = get_longbusy_msecs(rc); 385 total_delay += delay; 386 if (total_delay > 1000) { 387 pr_warn("Warning: Giving up waiting to enable " 388 "relocation on exceptions (%u msec)!\n", 389 total_delay); 390 return false; 391 } 392 393 mdelay(delay); 394 } 395 } 396 EXPORT_SYMBOL(pseries_enable_reloc_on_exc); 397 398 void pseries_disable_reloc_on_exc(void) 399 { 400 long rc; 401 402 while (1) { 403 rc = disable_reloc_on_exceptions(); 404 if (!H_IS_LONG_BUSY(rc)) 405 break; 406 mdelay(get_longbusy_msecs(rc)); 407 } 408 if (rc != H_SUCCESS) 409 pr_warn("Warning: Failed to disable relocation on exceptions: %ld\n", 410 rc); 411 } 412 EXPORT_SYMBOL(pseries_disable_reloc_on_exc); 413 414 #ifdef CONFIG_KEXEC_CORE 415 static void pSeries_machine_kexec(struct kimage *image) 416 { 417 if (firmware_has_feature(FW_FEATURE_SET_MODE)) 418 pseries_disable_reloc_on_exc(); 419 420 default_machine_kexec(image); 421 } 422 #endif 423 424 #ifdef __LITTLE_ENDIAN__ 425 void pseries_big_endian_exceptions(void) 426 { 427 long rc; 428 429 while (1) { 430 rc = enable_big_endian_exceptions(); 431 if (!H_IS_LONG_BUSY(rc)) 432 break; 433 mdelay(get_longbusy_msecs(rc)); 434 } 435 436 /* 437 * At this point it is unlikely panic() will get anything 438 * out to the user, since this is called very late in kexec 439 * but at least this will stop us from continuing on further 440 * and creating an even more difficult to debug situation. 441 * 442 * There is a known problem when kdump'ing, if cpus are offline 443 * the above call will fail. Rather than panicking again, keep 444 * going and hope the kdump kernel is also little endian, which 445 * it usually is. 446 */ 447 if (rc && !kdump_in_progress()) 448 panic("Could not enable big endian exceptions"); 449 } 450 451 void pseries_little_endian_exceptions(void) 452 { 453 long rc; 454 455 while (1) { 456 rc = enable_little_endian_exceptions(); 457 if (!H_IS_LONG_BUSY(rc)) 458 break; 459 mdelay(get_longbusy_msecs(rc)); 460 } 461 if (rc) { 462 ppc_md.progress("H_SET_MODE LE exception fail", 0); 463 panic("Could not enable little endian exceptions"); 464 } 465 } 466 #endif 467 468 static void __init pSeries_discover_phbs(void) 469 { 470 struct device_node *node; 471 struct pci_controller *phb; 472 struct device_node *root = of_find_node_by_path("/"); 473 474 for_each_child_of_node(root, node) { 475 if (!of_node_is_type(node, "pci") && 476 !of_node_is_type(node, "pciex")) 477 continue; 478 479 phb = pcibios_alloc_controller(node); 480 if (!phb) 481 continue; 482 rtas_setup_phb(phb); 483 pci_process_bridge_OF_ranges(phb, node, 0); 484 isa_bridge_find_early(phb); 485 phb->controller_ops = pseries_pci_controller_ops; 486 487 /* create pci_dn's for DT nodes under this PHB */ 488 pci_devs_phb_init_dynamic(phb); 489 } 490 491 of_node_put(root); 492 493 /* 494 * PCI_PROBE_ONLY and PCI_REASSIGN_ALL_BUS can be set via properties 495 * in chosen. 496 */ 497 of_pci_check_probe_only(); 498 } 499 500 static void init_cpu_char_feature_flags(struct h_cpu_char_result *result) 501 { 502 /* 503 * The features below are disabled by default, so we instead look to see 504 * if firmware has *enabled* them, and set them if so. 505 */ 506 if (result->character & H_CPU_CHAR_SPEC_BAR_ORI31) 507 security_ftr_set(SEC_FTR_SPEC_BAR_ORI31); 508 509 if (result->character & H_CPU_CHAR_BCCTRL_SERIALISED) 510 security_ftr_set(SEC_FTR_BCCTRL_SERIALISED); 511 512 if (result->character & H_CPU_CHAR_L1D_FLUSH_ORI30) 513 security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30); 514 515 if (result->character & H_CPU_CHAR_L1D_FLUSH_TRIG2) 516 security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2); 517 518 if (result->character & H_CPU_CHAR_L1D_THREAD_PRIV) 519 security_ftr_set(SEC_FTR_L1D_THREAD_PRIV); 520 521 if (result->character & H_CPU_CHAR_COUNT_CACHE_DISABLED) 522 security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED); 523 524 if (result->character & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) 525 security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST); 526 527 if (result->character & H_CPU_CHAR_BCCTR_LINK_FLUSH_ASSIST) 528 security_ftr_set(SEC_FTR_BCCTR_LINK_FLUSH_ASSIST); 529 530 if (result->behaviour & H_CPU_BEHAV_FLUSH_COUNT_CACHE) 531 security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE); 532 533 if (result->behaviour & H_CPU_BEHAV_FLUSH_LINK_STACK) 534 security_ftr_set(SEC_FTR_FLUSH_LINK_STACK); 535 536 /* 537 * The features below are enabled by default, so we instead look to see 538 * if firmware has *disabled* them, and clear them if so. 539 * H_CPU_BEHAV_FAVOUR_SECURITY_H could be set only if 540 * H_CPU_BEHAV_FAVOUR_SECURITY is. 541 */ 542 if (!(result->behaviour & H_CPU_BEHAV_FAVOUR_SECURITY)) 543 security_ftr_clear(SEC_FTR_FAVOUR_SECURITY); 544 else if (result->behaviour & H_CPU_BEHAV_FAVOUR_SECURITY_H) 545 pseries_security_flavor = 1; 546 else 547 pseries_security_flavor = 2; 548 549 if (!(result->behaviour & H_CPU_BEHAV_L1D_FLUSH_PR)) 550 security_ftr_clear(SEC_FTR_L1D_FLUSH_PR); 551 552 if (result->behaviour & H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY) 553 security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY); 554 555 if (result->behaviour & H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS) 556 security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS); 557 558 if (result->behaviour & H_CPU_BEHAV_NO_STF_BARRIER) 559 security_ftr_clear(SEC_FTR_STF_BARRIER); 560 561 if (!(result->behaviour & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR)) 562 security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR); 563 } 564 565 void pseries_setup_security_mitigations(void) 566 { 567 struct h_cpu_char_result result; 568 enum l1d_flush_type types; 569 bool enable; 570 long rc; 571 572 /* 573 * Set features to the defaults assumed by init_cpu_char_feature_flags() 574 * so it can set/clear again any features that might have changed after 575 * migration, and in case the hypercall fails and it is not even called. 576 */ 577 powerpc_security_features = SEC_FTR_DEFAULT; 578 579 rc = plpar_get_cpu_characteristics(&result); 580 if (rc == H_SUCCESS) 581 init_cpu_char_feature_flags(&result); 582 583 /* 584 * We're the guest so this doesn't apply to us, clear it to simplify 585 * handling of it elsewhere. 586 */ 587 security_ftr_clear(SEC_FTR_L1D_FLUSH_HV); 588 589 types = L1D_FLUSH_FALLBACK; 590 591 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2)) 592 types |= L1D_FLUSH_MTTRIG; 593 594 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30)) 595 types |= L1D_FLUSH_ORI; 596 597 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \ 598 security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR); 599 600 setup_rfi_flush(types, enable); 601 setup_count_cache_flush(); 602 603 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && 604 security_ftr_enabled(SEC_FTR_L1D_FLUSH_ENTRY); 605 setup_entry_flush(enable); 606 607 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && 608 security_ftr_enabled(SEC_FTR_L1D_FLUSH_UACCESS); 609 setup_uaccess_flush(enable); 610 611 setup_stf_barrier(); 612 } 613 614 #ifdef CONFIG_PCI_IOV 615 enum rtas_iov_fw_value_map { 616 NUM_RES_PROPERTY = 0, /* Number of Resources */ 617 LOW_INT = 1, /* Lowest 32 bits of Address */ 618 START_OF_ENTRIES = 2, /* Always start of entry */ 619 APERTURE_PROPERTY = 2, /* Start of entry+ to Aperture Size */ 620 WDW_SIZE_PROPERTY = 4, /* Start of entry+ to Window Size */ 621 NEXT_ENTRY = 7 /* Go to next entry on array */ 622 }; 623 624 enum get_iov_fw_value_index { 625 BAR_ADDRS = 1, /* Get Bar Address */ 626 APERTURE_SIZE = 2, /* Get Aperture Size */ 627 WDW_SIZE = 3 /* Get Window Size */ 628 }; 629 630 static resource_size_t pseries_get_iov_fw_value(struct pci_dev *dev, int resno, 631 enum get_iov_fw_value_index value) 632 { 633 const int *indexes; 634 struct device_node *dn = pci_device_to_OF_node(dev); 635 int i, num_res, ret = 0; 636 637 indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL); 638 if (!indexes) 639 return 0; 640 641 /* 642 * First element in the array is the number of Bars 643 * returned. Search through the list to find the matching 644 * bar 645 */ 646 num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1); 647 if (resno >= num_res) 648 return 0; /* or an errror */ 649 650 i = START_OF_ENTRIES + NEXT_ENTRY * resno; 651 switch (value) { 652 case BAR_ADDRS: 653 ret = of_read_number(&indexes[i], 2); 654 break; 655 case APERTURE_SIZE: 656 ret = of_read_number(&indexes[i + APERTURE_PROPERTY], 2); 657 break; 658 case WDW_SIZE: 659 ret = of_read_number(&indexes[i + WDW_SIZE_PROPERTY], 2); 660 break; 661 } 662 663 return ret; 664 } 665 666 static void of_pci_set_vf_bar_size(struct pci_dev *dev, const int *indexes) 667 { 668 struct resource *res; 669 resource_size_t base, size; 670 int i, r, num_res; 671 672 num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1); 673 num_res = min_t(int, num_res, PCI_SRIOV_NUM_BARS); 674 for (i = START_OF_ENTRIES, r = 0; r < num_res && r < PCI_SRIOV_NUM_BARS; 675 i += NEXT_ENTRY, r++) { 676 res = &dev->resource[r + PCI_IOV_RESOURCES]; 677 base = of_read_number(&indexes[i], 2); 678 size = of_read_number(&indexes[i + APERTURE_PROPERTY], 2); 679 res->flags = pci_parse_of_flags(of_read_number 680 (&indexes[i + LOW_INT], 1), 0); 681 res->flags |= (IORESOURCE_MEM_64 | IORESOURCE_PCI_FIXED); 682 res->name = pci_name(dev); 683 res->start = base; 684 res->end = base + size - 1; 685 } 686 } 687 688 static void of_pci_parse_iov_addrs(struct pci_dev *dev, const int *indexes) 689 { 690 struct resource *res, *root, *conflict; 691 resource_size_t base, size; 692 int i, r, num_res; 693 694 /* 695 * First element in the array is the number of Bars 696 * returned. Search through the list to find the matching 697 * bars assign them from firmware into resources structure. 698 */ 699 num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1); 700 for (i = START_OF_ENTRIES, r = 0; r < num_res && r < PCI_SRIOV_NUM_BARS; 701 i += NEXT_ENTRY, r++) { 702 res = &dev->resource[r + PCI_IOV_RESOURCES]; 703 base = of_read_number(&indexes[i], 2); 704 size = of_read_number(&indexes[i + WDW_SIZE_PROPERTY], 2); 705 res->name = pci_name(dev); 706 res->start = base; 707 res->end = base + size - 1; 708 root = &iomem_resource; 709 dev_dbg(&dev->dev, 710 "pSeries IOV BAR %d: trying firmware assignment %pR\n", 711 r + PCI_IOV_RESOURCES, res); 712 conflict = request_resource_conflict(root, res); 713 if (conflict) { 714 dev_info(&dev->dev, 715 "BAR %d: %pR conflicts with %s %pR\n", 716 r + PCI_IOV_RESOURCES, res, 717 conflict->name, conflict); 718 res->flags |= IORESOURCE_UNSET; 719 } 720 } 721 } 722 723 static void pseries_disable_sriov_resources(struct pci_dev *pdev) 724 { 725 int i; 726 727 pci_warn(pdev, "No hypervisor support for SR-IOV on this device, IOV BARs disabled.\n"); 728 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 729 pdev->resource[i + PCI_IOV_RESOURCES].flags = 0; 730 } 731 732 static void pseries_pci_fixup_resources(struct pci_dev *pdev) 733 { 734 const int *indexes; 735 struct device_node *dn = pci_device_to_OF_node(pdev); 736 737 /*Firmware must support open sriov otherwise dont configure*/ 738 indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL); 739 if (indexes) 740 of_pci_set_vf_bar_size(pdev, indexes); 741 else 742 pseries_disable_sriov_resources(pdev); 743 } 744 745 static void pseries_pci_fixup_iov_resources(struct pci_dev *pdev) 746 { 747 const int *indexes; 748 struct device_node *dn = pci_device_to_OF_node(pdev); 749 750 if (!pdev->is_physfn || pci_dev_is_added(pdev)) 751 return; 752 /*Firmware must support open sriov otherwise dont configure*/ 753 indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL); 754 if (indexes) 755 of_pci_parse_iov_addrs(pdev, indexes); 756 else 757 pseries_disable_sriov_resources(pdev); 758 } 759 760 static resource_size_t pseries_pci_iov_resource_alignment(struct pci_dev *pdev, 761 int resno) 762 { 763 const __be32 *reg; 764 struct device_node *dn = pci_device_to_OF_node(pdev); 765 766 /*Firmware must support open sriov otherwise report regular alignment*/ 767 reg = of_get_property(dn, "ibm,is-open-sriov-pf", NULL); 768 if (!reg) 769 return pci_iov_resource_size(pdev, resno); 770 771 if (!pdev->is_physfn) 772 return 0; 773 return pseries_get_iov_fw_value(pdev, 774 resno - PCI_IOV_RESOURCES, 775 APERTURE_SIZE); 776 } 777 #endif 778 779 static void __init pSeries_setup_arch(void) 780 { 781 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT); 782 783 /* Discover PIC type and setup ppc_md accordingly */ 784 smp_init_pseries(); 785 786 787 if (radix_enabled() && !mmu_has_feature(MMU_FTR_GTSE)) 788 if (!firmware_has_feature(FW_FEATURE_RPT_INVALIDATE)) 789 panic("BUG: Radix support requires either GTSE or RPT_INVALIDATE\n"); 790 791 792 /* openpic global configuration register (64-bit format). */ 793 /* openpic Interrupt Source Unit pointer (64-bit format). */ 794 /* python0 facility area (mmio) (64-bit format) REAL address. */ 795 796 /* init to some ~sane value until calibrate_delay() runs */ 797 loops_per_jiffy = 50000000; 798 799 fwnmi_init(); 800 801 pseries_setup_security_mitigations(); 802 pseries_lpar_read_hblkrm_characteristics(); 803 804 /* By default, only probe PCI (can be overridden by rtas_pci) */ 805 pci_add_flags(PCI_PROBE_ONLY); 806 807 /* Find and initialize PCI host bridges */ 808 init_pci_config_tokens(); 809 of_reconfig_notifier_register(&pci_dn_reconfig_nb); 810 811 pSeries_nvram_init(); 812 813 if (firmware_has_feature(FW_FEATURE_LPAR)) { 814 vpa_init(boot_cpuid); 815 816 if (lppaca_shared_proc(get_lppaca())) { 817 static_branch_enable(&shared_processor); 818 pv_spinlocks_init(); 819 } 820 821 ppc_md.power_save = pseries_lpar_idle; 822 ppc_md.enable_pmcs = pseries_lpar_enable_pmcs; 823 #ifdef CONFIG_PCI_IOV 824 ppc_md.pcibios_fixup_resources = 825 pseries_pci_fixup_resources; 826 ppc_md.pcibios_fixup_sriov = 827 pseries_pci_fixup_iov_resources; 828 ppc_md.pcibios_iov_resource_alignment = 829 pseries_pci_iov_resource_alignment; 830 #endif 831 } else { 832 /* No special idle routine */ 833 ppc_md.enable_pmcs = power4_enable_pmcs; 834 } 835 836 ppc_md.pcibios_root_bridge_prepare = pseries_root_bridge_prepare; 837 838 if (swiotlb_force == SWIOTLB_FORCE) 839 ppc_swiotlb_enable = 1; 840 } 841 842 static void pseries_panic(char *str) 843 { 844 panic_flush_kmsg_end(); 845 rtas_os_term(str); 846 } 847 848 static int __init pSeries_init_panel(void) 849 { 850 /* Manually leave the kernel version on the panel. */ 851 #ifdef __BIG_ENDIAN__ 852 ppc_md.progress("Linux ppc64\n", 0); 853 #else 854 ppc_md.progress("Linux ppc64le\n", 0); 855 #endif 856 ppc_md.progress(init_utsname()->version, 0); 857 858 return 0; 859 } 860 machine_arch_initcall(pseries, pSeries_init_panel); 861 862 static int pseries_set_dabr(unsigned long dabr, unsigned long dabrx) 863 { 864 return plpar_hcall_norets(H_SET_DABR, dabr); 865 } 866 867 static int pseries_set_xdabr(unsigned long dabr, unsigned long dabrx) 868 { 869 /* Have to set at least one bit in the DABRX according to PAPR */ 870 if (dabrx == 0 && dabr == 0) 871 dabrx = DABRX_USER; 872 /* PAPR says we can only set kernel and user bits */ 873 dabrx &= DABRX_KERNEL | DABRX_USER; 874 875 return plpar_hcall_norets(H_SET_XDABR, dabr, dabrx); 876 } 877 878 static int pseries_set_dawr(int nr, unsigned long dawr, unsigned long dawrx) 879 { 880 /* PAPR says we can't set HYP */ 881 dawrx &= ~DAWRX_HYP; 882 883 if (nr == 0) 884 return plpar_set_watchpoint0(dawr, dawrx); 885 else 886 return plpar_set_watchpoint1(dawr, dawrx); 887 } 888 889 #define CMO_CHARACTERISTICS_TOKEN 44 890 #define CMO_MAXLENGTH 1026 891 892 void pSeries_coalesce_init(void) 893 { 894 struct hvcall_mpp_x_data mpp_x_data; 895 896 if (firmware_has_feature(FW_FEATURE_CMO) && !h_get_mpp_x(&mpp_x_data)) 897 powerpc_firmware_features |= FW_FEATURE_XCMO; 898 else 899 powerpc_firmware_features &= ~FW_FEATURE_XCMO; 900 } 901 902 /** 903 * fw_cmo_feature_init - FW_FEATURE_CMO is not stored in ibm,hypertas-functions, 904 * handle that here. (Stolen from parse_system_parameter_string) 905 */ 906 static void pSeries_cmo_feature_init(void) 907 { 908 char *ptr, *key, *value, *end; 909 int call_status; 910 int page_order = IOMMU_PAGE_SHIFT_4K; 911 912 pr_debug(" -> fw_cmo_feature_init()\n"); 913 spin_lock(&rtas_data_buf_lock); 914 memset(rtas_data_buf, 0, RTAS_DATA_BUF_SIZE); 915 call_status = rtas_call(rtas_token("ibm,get-system-parameter"), 3, 1, 916 NULL, 917 CMO_CHARACTERISTICS_TOKEN, 918 __pa(rtas_data_buf), 919 RTAS_DATA_BUF_SIZE); 920 921 if (call_status != 0) { 922 spin_unlock(&rtas_data_buf_lock); 923 pr_debug("CMO not available\n"); 924 pr_debug(" <- fw_cmo_feature_init()\n"); 925 return; 926 } 927 928 end = rtas_data_buf + CMO_MAXLENGTH - 2; 929 ptr = rtas_data_buf + 2; /* step over strlen value */ 930 key = value = ptr; 931 932 while (*ptr && (ptr <= end)) { 933 /* Separate the key and value by replacing '=' with '\0' and 934 * point the value at the string after the '=' 935 */ 936 if (ptr[0] == '=') { 937 ptr[0] = '\0'; 938 value = ptr + 1; 939 } else if (ptr[0] == '\0' || ptr[0] == ',') { 940 /* Terminate the string containing the key/value pair */ 941 ptr[0] = '\0'; 942 943 if (key == value) { 944 pr_debug("Malformed key/value pair\n"); 945 /* Never found a '=', end processing */ 946 break; 947 } 948 949 if (0 == strcmp(key, "CMOPageSize")) 950 page_order = simple_strtol(value, NULL, 10); 951 else if (0 == strcmp(key, "PrPSP")) 952 CMO_PrPSP = simple_strtol(value, NULL, 10); 953 else if (0 == strcmp(key, "SecPSP")) 954 CMO_SecPSP = simple_strtol(value, NULL, 10); 955 value = key = ptr + 1; 956 } 957 ptr++; 958 } 959 960 /* Page size is returned as the power of 2 of the page size, 961 * convert to the page size in bytes before returning 962 */ 963 CMO_PageSize = 1 << page_order; 964 pr_debug("CMO_PageSize = %lu\n", CMO_PageSize); 965 966 if (CMO_PrPSP != -1 || CMO_SecPSP != -1) { 967 pr_info("CMO enabled\n"); 968 pr_debug("CMO enabled, PrPSP=%d, SecPSP=%d\n", CMO_PrPSP, 969 CMO_SecPSP); 970 powerpc_firmware_features |= FW_FEATURE_CMO; 971 pSeries_coalesce_init(); 972 } else 973 pr_debug("CMO not enabled, PrPSP=%d, SecPSP=%d\n", CMO_PrPSP, 974 CMO_SecPSP); 975 spin_unlock(&rtas_data_buf_lock); 976 pr_debug(" <- fw_cmo_feature_init()\n"); 977 } 978 979 /* 980 * Early initialization. Relocation is on but do not reference unbolted pages 981 */ 982 static void __init pseries_init(void) 983 { 984 pr_debug(" -> pseries_init()\n"); 985 986 #ifdef CONFIG_HVC_CONSOLE 987 if (firmware_has_feature(FW_FEATURE_LPAR)) 988 hvc_vio_init_early(); 989 #endif 990 if (firmware_has_feature(FW_FEATURE_XDABR)) 991 ppc_md.set_dabr = pseries_set_xdabr; 992 else if (firmware_has_feature(FW_FEATURE_DABR)) 993 ppc_md.set_dabr = pseries_set_dabr; 994 995 if (firmware_has_feature(FW_FEATURE_SET_MODE)) 996 ppc_md.set_dawr = pseries_set_dawr; 997 998 pSeries_cmo_feature_init(); 999 iommu_init_early_pSeries(); 1000 1001 pr_debug(" <- pseries_init()\n"); 1002 } 1003 1004 /** 1005 * pseries_power_off - tell firmware about how to power off the system. 1006 * 1007 * This function calls either the power-off rtas token in normal cases 1008 * or the ibm,power-off-ups token (if present & requested) in case of 1009 * a power failure. If power-off token is used, power on will only be 1010 * possible with power button press. If ibm,power-off-ups token is used 1011 * it will allow auto poweron after power is restored. 1012 */ 1013 static void pseries_power_off(void) 1014 { 1015 int rc; 1016 int rtas_poweroff_ups_token = rtas_token("ibm,power-off-ups"); 1017 1018 if (rtas_flash_term_hook) 1019 rtas_flash_term_hook(SYS_POWER_OFF); 1020 1021 if (rtas_poweron_auto == 0 || 1022 rtas_poweroff_ups_token == RTAS_UNKNOWN_SERVICE) { 1023 rc = rtas_call(rtas_token("power-off"), 2, 1, NULL, -1, -1); 1024 printk(KERN_INFO "RTAS power-off returned %d\n", rc); 1025 } else { 1026 rc = rtas_call(rtas_poweroff_ups_token, 0, 1, NULL); 1027 printk(KERN_INFO "RTAS ibm,power-off-ups returned %d\n", rc); 1028 } 1029 for (;;); 1030 } 1031 1032 static int __init pSeries_probe(void) 1033 { 1034 if (!of_node_is_type(of_root, "chrp")) 1035 return 0; 1036 1037 /* Cell blades firmware claims to be chrp while it's not. Until this 1038 * is fixed, we need to avoid those here. 1039 */ 1040 if (of_machine_is_compatible("IBM,CPBW-1.0") || 1041 of_machine_is_compatible("IBM,CBEA")) 1042 return 0; 1043 1044 pm_power_off = pseries_power_off; 1045 1046 pr_debug("Machine is%s LPAR !\n", 1047 (powerpc_firmware_features & FW_FEATURE_LPAR) ? "" : " not"); 1048 1049 pseries_init(); 1050 1051 return 1; 1052 } 1053 1054 static int pSeries_pci_probe_mode(struct pci_bus *bus) 1055 { 1056 if (firmware_has_feature(FW_FEATURE_LPAR)) 1057 return PCI_PROBE_DEVTREE; 1058 return PCI_PROBE_NORMAL; 1059 } 1060 1061 struct pci_controller_ops pseries_pci_controller_ops = { 1062 .probe_mode = pSeries_pci_probe_mode, 1063 }; 1064 1065 define_machine(pseries) { 1066 .name = "pSeries", 1067 .probe = pSeries_probe, 1068 .setup_arch = pSeries_setup_arch, 1069 .init_IRQ = pseries_init_irq, 1070 .show_cpuinfo = pSeries_show_cpuinfo, 1071 .log_error = pSeries_log_error, 1072 .discover_phbs = pSeries_discover_phbs, 1073 .pcibios_fixup = pSeries_final_fixup, 1074 .restart = rtas_restart, 1075 .halt = rtas_halt, 1076 .panic = pseries_panic, 1077 .get_boot_time = rtas_get_boot_time, 1078 .get_rtc_time = rtas_get_rtc_time, 1079 .set_rtc_time = rtas_set_rtc_time, 1080 .calibrate_decr = generic_calibrate_decr, 1081 .progress = rtas_progress, 1082 .system_reset_exception = pSeries_system_reset_exception, 1083 .machine_check_early = pseries_machine_check_realmode, 1084 .machine_check_exception = pSeries_machine_check_exception, 1085 #ifdef CONFIG_KEXEC_CORE 1086 .machine_kexec = pSeries_machine_kexec, 1087 .kexec_cpu_down = pseries_kexec_cpu_down, 1088 #endif 1089 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE 1090 .memory_block_size = pseries_memory_block_size, 1091 #endif 1092 }; 1093