1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *  64-bit pSeries and RS/6000 setup code.
4  *
5  *  Copyright (C) 1995  Linus Torvalds
6  *  Adapted from 'alpha' version by Gary Thomas
7  *  Modified by Cort Dougan (cort@cs.nmt.edu)
8  *  Modified by PPC64 Team, IBM Corp
9  */
10 
11 /*
12  * bootup setup stuff..
13  */
14 
15 #include <linux/cpu.h>
16 #include <linux/errno.h>
17 #include <linux/sched.h>
18 #include <linux/kernel.h>
19 #include <linux/mm.h>
20 #include <linux/stddef.h>
21 #include <linux/unistd.h>
22 #include <linux/user.h>
23 #include <linux/tty.h>
24 #include <linux/major.h>
25 #include <linux/interrupt.h>
26 #include <linux/reboot.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/console.h>
30 #include <linux/pci.h>
31 #include <linux/utsname.h>
32 #include <linux/adb.h>
33 #include <linux/export.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/seq_file.h>
37 #include <linux/root_dev.h>
38 #include <linux/of.h>
39 #include <linux/of_pci.h>
40 #include <linux/memblock.h>
41 #include <linux/swiotlb.h>
42 
43 #include <asm/mmu.h>
44 #include <asm/processor.h>
45 #include <asm/io.h>
46 #include <asm/prom.h>
47 #include <asm/rtas.h>
48 #include <asm/pci-bridge.h>
49 #include <asm/iommu.h>
50 #include <asm/dma.h>
51 #include <asm/machdep.h>
52 #include <asm/irq.h>
53 #include <asm/time.h>
54 #include <asm/nvram.h>
55 #include <asm/pmc.h>
56 #include <asm/xics.h>
57 #include <asm/xive.h>
58 #include <asm/ppc-pci.h>
59 #include <asm/i8259.h>
60 #include <asm/udbg.h>
61 #include <asm/smp.h>
62 #include <asm/firmware.h>
63 #include <asm/eeh.h>
64 #include <asm/reg.h>
65 #include <asm/plpar_wrappers.h>
66 #include <asm/kexec.h>
67 #include <asm/isa-bridge.h>
68 #include <asm/security_features.h>
69 #include <asm/asm-const.h>
70 #include <asm/idle.h>
71 #include <asm/swiotlb.h>
72 #include <asm/svm.h>
73 #include <asm/dtl.h>
74 
75 #include "pseries.h"
76 #include "../../../../drivers/pci/pci.h"
77 
78 DEFINE_STATIC_KEY_FALSE(shared_processor);
79 EXPORT_SYMBOL_GPL(shared_processor);
80 
81 int CMO_PrPSP = -1;
82 int CMO_SecPSP = -1;
83 unsigned long CMO_PageSize = (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K);
84 EXPORT_SYMBOL(CMO_PageSize);
85 
86 int fwnmi_active;  /* TRUE if an FWNMI handler is present */
87 int ibm_nmi_interlock_token;
88 
89 static void pSeries_show_cpuinfo(struct seq_file *m)
90 {
91 	struct device_node *root;
92 	const char *model = "";
93 
94 	root = of_find_node_by_path("/");
95 	if (root)
96 		model = of_get_property(root, "model", NULL);
97 	seq_printf(m, "machine\t\t: CHRP %s\n", model);
98 	of_node_put(root);
99 	if (radix_enabled())
100 		seq_printf(m, "MMU\t\t: Radix\n");
101 	else
102 		seq_printf(m, "MMU\t\t: Hash\n");
103 }
104 
105 /* Initialize firmware assisted non-maskable interrupts if
106  * the firmware supports this feature.
107  */
108 static void __init fwnmi_init(void)
109 {
110 	unsigned long system_reset_addr, machine_check_addr;
111 	u8 *mce_data_buf;
112 	unsigned int i;
113 	int nr_cpus = num_possible_cpus();
114 #ifdef CONFIG_PPC_BOOK3S_64
115 	struct slb_entry *slb_ptr;
116 	size_t size;
117 #endif
118 	int ibm_nmi_register_token;
119 
120 	ibm_nmi_register_token = rtas_token("ibm,nmi-register");
121 	if (ibm_nmi_register_token == RTAS_UNKNOWN_SERVICE)
122 		return;
123 
124 	ibm_nmi_interlock_token = rtas_token("ibm,nmi-interlock");
125 	if (WARN_ON(ibm_nmi_interlock_token == RTAS_UNKNOWN_SERVICE))
126 		return;
127 
128 	/* If the kernel's not linked at zero we point the firmware at low
129 	 * addresses anyway, and use a trampoline to get to the real code. */
130 	system_reset_addr  = __pa(system_reset_fwnmi) - PHYSICAL_START;
131 	machine_check_addr = __pa(machine_check_fwnmi) - PHYSICAL_START;
132 
133 	if (0 == rtas_call(ibm_nmi_register_token, 2, 1, NULL,
134 			   system_reset_addr, machine_check_addr))
135 		fwnmi_active = 1;
136 
137 	/*
138 	 * Allocate a chunk for per cpu buffer to hold rtas errorlog.
139 	 * It will be used in real mode mce handler, hence it needs to be
140 	 * below RMA.
141 	 */
142 	mce_data_buf = memblock_alloc_try_nid_raw(RTAS_ERROR_LOG_MAX * nr_cpus,
143 					RTAS_ERROR_LOG_MAX, MEMBLOCK_LOW_LIMIT,
144 					ppc64_rma_size, NUMA_NO_NODE);
145 	if (!mce_data_buf)
146 		panic("Failed to allocate %d bytes below %pa for MCE buffer\n",
147 		      RTAS_ERROR_LOG_MAX * nr_cpus, &ppc64_rma_size);
148 
149 	for_each_possible_cpu(i) {
150 		paca_ptrs[i]->mce_data_buf = mce_data_buf +
151 						(RTAS_ERROR_LOG_MAX * i);
152 	}
153 
154 #ifdef CONFIG_PPC_BOOK3S_64
155 	if (!radix_enabled()) {
156 		/* Allocate per cpu area to save old slb contents during MCE */
157 		size = sizeof(struct slb_entry) * mmu_slb_size * nr_cpus;
158 		slb_ptr = memblock_alloc_try_nid_raw(size,
159 				sizeof(struct slb_entry), MEMBLOCK_LOW_LIMIT,
160 				ppc64_rma_size, NUMA_NO_NODE);
161 		if (!slb_ptr)
162 			panic("Failed to allocate %zu bytes below %pa for slb area\n",
163 			      size, &ppc64_rma_size);
164 
165 		for_each_possible_cpu(i)
166 			paca_ptrs[i]->mce_faulty_slbs = slb_ptr + (mmu_slb_size * i);
167 	}
168 #endif
169 }
170 
171 static void pseries_8259_cascade(struct irq_desc *desc)
172 {
173 	struct irq_chip *chip = irq_desc_get_chip(desc);
174 	unsigned int cascade_irq = i8259_irq();
175 
176 	if (cascade_irq)
177 		generic_handle_irq(cascade_irq);
178 
179 	chip->irq_eoi(&desc->irq_data);
180 }
181 
182 static void __init pseries_setup_i8259_cascade(void)
183 {
184 	struct device_node *np, *old, *found = NULL;
185 	unsigned int cascade;
186 	const u32 *addrp;
187 	unsigned long intack = 0;
188 	int naddr;
189 
190 	for_each_node_by_type(np, "interrupt-controller") {
191 		if (of_device_is_compatible(np, "chrp,iic")) {
192 			found = np;
193 			break;
194 		}
195 	}
196 
197 	if (found == NULL) {
198 		printk(KERN_DEBUG "pic: no ISA interrupt controller\n");
199 		return;
200 	}
201 
202 	cascade = irq_of_parse_and_map(found, 0);
203 	if (!cascade) {
204 		printk(KERN_ERR "pic: failed to map cascade interrupt");
205 		return;
206 	}
207 	pr_debug("pic: cascade mapped to irq %d\n", cascade);
208 
209 	for (old = of_node_get(found); old != NULL ; old = np) {
210 		np = of_get_parent(old);
211 		of_node_put(old);
212 		if (np == NULL)
213 			break;
214 		if (!of_node_name_eq(np, "pci"))
215 			continue;
216 		addrp = of_get_property(np, "8259-interrupt-acknowledge", NULL);
217 		if (addrp == NULL)
218 			continue;
219 		naddr = of_n_addr_cells(np);
220 		intack = addrp[naddr-1];
221 		if (naddr > 1)
222 			intack |= ((unsigned long)addrp[naddr-2]) << 32;
223 	}
224 	if (intack)
225 		printk(KERN_DEBUG "pic: PCI 8259 intack at 0x%016lx\n", intack);
226 	i8259_init(found, intack);
227 	of_node_put(found);
228 	irq_set_chained_handler(cascade, pseries_8259_cascade);
229 }
230 
231 static void __init pseries_init_irq(void)
232 {
233 	/* Try using a XIVE if available, otherwise use a XICS */
234 	if (!xive_spapr_init()) {
235 		xics_init();
236 		pseries_setup_i8259_cascade();
237 	}
238 }
239 
240 static void pseries_lpar_enable_pmcs(void)
241 {
242 	unsigned long set, reset;
243 
244 	set = 1UL << 63;
245 	reset = 0;
246 	plpar_hcall_norets(H_PERFMON, set, reset);
247 }
248 
249 static int pci_dn_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data)
250 {
251 	struct of_reconfig_data *rd = data;
252 	struct device_node *parent, *np = rd->dn;
253 	struct pci_dn *pdn;
254 	int err = NOTIFY_OK;
255 
256 	switch (action) {
257 	case OF_RECONFIG_ATTACH_NODE:
258 		parent = of_get_parent(np);
259 		pdn = parent ? PCI_DN(parent) : NULL;
260 		if (pdn)
261 			pci_add_device_node_info(pdn->phb, np);
262 
263 		of_node_put(parent);
264 		break;
265 	case OF_RECONFIG_DETACH_NODE:
266 		pdn = PCI_DN(np);
267 		if (pdn)
268 			list_del(&pdn->list);
269 		break;
270 	default:
271 		err = NOTIFY_DONE;
272 		break;
273 	}
274 	return err;
275 }
276 
277 static struct notifier_block pci_dn_reconfig_nb = {
278 	.notifier_call = pci_dn_reconfig_notifier,
279 };
280 
281 struct kmem_cache *dtl_cache;
282 
283 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
284 /*
285  * Allocate space for the dispatch trace log for all possible cpus
286  * and register the buffers with the hypervisor.  This is used for
287  * computing time stolen by the hypervisor.
288  */
289 static int alloc_dispatch_logs(void)
290 {
291 	if (!firmware_has_feature(FW_FEATURE_SPLPAR))
292 		return 0;
293 
294 	if (!dtl_cache)
295 		return 0;
296 
297 	alloc_dtl_buffers(0);
298 
299 	/* Register the DTL for the current (boot) cpu */
300 	register_dtl_buffer(smp_processor_id());
301 
302 	return 0;
303 }
304 #else /* !CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
305 static inline int alloc_dispatch_logs(void)
306 {
307 	return 0;
308 }
309 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
310 
311 static int alloc_dispatch_log_kmem_cache(void)
312 {
313 	void (*ctor)(void *) = get_dtl_cache_ctor();
314 
315 	dtl_cache = kmem_cache_create("dtl", DISPATCH_LOG_BYTES,
316 						DISPATCH_LOG_BYTES, 0, ctor);
317 	if (!dtl_cache) {
318 		pr_warn("Failed to create dispatch trace log buffer cache\n");
319 		pr_warn("Stolen time statistics will be unreliable\n");
320 		return 0;
321 	}
322 
323 	return alloc_dispatch_logs();
324 }
325 machine_early_initcall(pseries, alloc_dispatch_log_kmem_cache);
326 
327 DEFINE_PER_CPU(u64, idle_spurr_cycles);
328 DEFINE_PER_CPU(u64, idle_entry_purr_snap);
329 DEFINE_PER_CPU(u64, idle_entry_spurr_snap);
330 static void pseries_lpar_idle(void)
331 {
332 	/*
333 	 * Default handler to go into low thread priority and possibly
334 	 * low power mode by ceding processor to hypervisor
335 	 */
336 
337 	if (!prep_irq_for_idle())
338 		return;
339 
340 	/* Indicate to hypervisor that we are idle. */
341 	pseries_idle_prolog();
342 
343 	/*
344 	 * Yield the processor to the hypervisor.  We return if
345 	 * an external interrupt occurs (which are driven prior
346 	 * to returning here) or if a prod occurs from another
347 	 * processor. When returning here, external interrupts
348 	 * are enabled.
349 	 */
350 	cede_processor();
351 
352 	pseries_idle_epilog();
353 }
354 
355 /*
356  * Enable relocation on during exceptions. This has partition wide scope and
357  * may take a while to complete, if it takes longer than one second we will
358  * just give up rather than wasting any more time on this - if that turns out
359  * to ever be a problem in practice we can move this into a kernel thread to
360  * finish off the process later in boot.
361  */
362 bool pseries_enable_reloc_on_exc(void)
363 {
364 	long rc;
365 	unsigned int delay, total_delay = 0;
366 
367 	while (1) {
368 		rc = enable_reloc_on_exceptions();
369 		if (!H_IS_LONG_BUSY(rc)) {
370 			if (rc == H_P2) {
371 				pr_info("Relocation on exceptions not"
372 					" supported\n");
373 				return false;
374 			} else if (rc != H_SUCCESS) {
375 				pr_warn("Unable to enable relocation"
376 					" on exceptions: %ld\n", rc);
377 				return false;
378 			}
379 			return true;
380 		}
381 
382 		delay = get_longbusy_msecs(rc);
383 		total_delay += delay;
384 		if (total_delay > 1000) {
385 			pr_warn("Warning: Giving up waiting to enable "
386 				"relocation on exceptions (%u msec)!\n",
387 				total_delay);
388 			return false;
389 		}
390 
391 		mdelay(delay);
392 	}
393 }
394 EXPORT_SYMBOL(pseries_enable_reloc_on_exc);
395 
396 void pseries_disable_reloc_on_exc(void)
397 {
398 	long rc;
399 
400 	while (1) {
401 		rc = disable_reloc_on_exceptions();
402 		if (!H_IS_LONG_BUSY(rc))
403 			break;
404 		mdelay(get_longbusy_msecs(rc));
405 	}
406 	if (rc != H_SUCCESS)
407 		pr_warn("Warning: Failed to disable relocation on exceptions: %ld\n",
408 			rc);
409 }
410 EXPORT_SYMBOL(pseries_disable_reloc_on_exc);
411 
412 #ifdef CONFIG_KEXEC_CORE
413 static void pSeries_machine_kexec(struct kimage *image)
414 {
415 	if (firmware_has_feature(FW_FEATURE_SET_MODE))
416 		pseries_disable_reloc_on_exc();
417 
418 	default_machine_kexec(image);
419 }
420 #endif
421 
422 #ifdef __LITTLE_ENDIAN__
423 void pseries_big_endian_exceptions(void)
424 {
425 	long rc;
426 
427 	while (1) {
428 		rc = enable_big_endian_exceptions();
429 		if (!H_IS_LONG_BUSY(rc))
430 			break;
431 		mdelay(get_longbusy_msecs(rc));
432 	}
433 
434 	/*
435 	 * At this point it is unlikely panic() will get anything
436 	 * out to the user, since this is called very late in kexec
437 	 * but at least this will stop us from continuing on further
438 	 * and creating an even more difficult to debug situation.
439 	 *
440 	 * There is a known problem when kdump'ing, if cpus are offline
441 	 * the above call will fail. Rather than panicking again, keep
442 	 * going and hope the kdump kernel is also little endian, which
443 	 * it usually is.
444 	 */
445 	if (rc && !kdump_in_progress())
446 		panic("Could not enable big endian exceptions");
447 }
448 
449 void pseries_little_endian_exceptions(void)
450 {
451 	long rc;
452 
453 	while (1) {
454 		rc = enable_little_endian_exceptions();
455 		if (!H_IS_LONG_BUSY(rc))
456 			break;
457 		mdelay(get_longbusy_msecs(rc));
458 	}
459 	if (rc) {
460 		ppc_md.progress("H_SET_MODE LE exception fail", 0);
461 		panic("Could not enable little endian exceptions");
462 	}
463 }
464 #endif
465 
466 static void __init pSeries_discover_phbs(void)
467 {
468 	struct device_node *node;
469 	struct pci_controller *phb;
470 	struct device_node *root = of_find_node_by_path("/");
471 
472 	for_each_child_of_node(root, node) {
473 		if (!of_node_is_type(node, "pci") &&
474 		    !of_node_is_type(node, "pciex"))
475 			continue;
476 
477 		phb = pcibios_alloc_controller(node);
478 		if (!phb)
479 			continue;
480 		rtas_setup_phb(phb);
481 		pci_process_bridge_OF_ranges(phb, node, 0);
482 		isa_bridge_find_early(phb);
483 		phb->controller_ops = pseries_pci_controller_ops;
484 
485 		/* create pci_dn's for DT nodes under this PHB */
486 		pci_devs_phb_init_dynamic(phb);
487 	}
488 
489 	of_node_put(root);
490 
491 	/*
492 	 * PCI_PROBE_ONLY and PCI_REASSIGN_ALL_BUS can be set via properties
493 	 * in chosen.
494 	 */
495 	of_pci_check_probe_only();
496 }
497 
498 static void init_cpu_char_feature_flags(struct h_cpu_char_result *result)
499 {
500 	/*
501 	 * The features below are disabled by default, so we instead look to see
502 	 * if firmware has *enabled* them, and set them if so.
503 	 */
504 	if (result->character & H_CPU_CHAR_SPEC_BAR_ORI31)
505 		security_ftr_set(SEC_FTR_SPEC_BAR_ORI31);
506 
507 	if (result->character & H_CPU_CHAR_BCCTRL_SERIALISED)
508 		security_ftr_set(SEC_FTR_BCCTRL_SERIALISED);
509 
510 	if (result->character & H_CPU_CHAR_L1D_FLUSH_ORI30)
511 		security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30);
512 
513 	if (result->character & H_CPU_CHAR_L1D_FLUSH_TRIG2)
514 		security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2);
515 
516 	if (result->character & H_CPU_CHAR_L1D_THREAD_PRIV)
517 		security_ftr_set(SEC_FTR_L1D_THREAD_PRIV);
518 
519 	if (result->character & H_CPU_CHAR_COUNT_CACHE_DISABLED)
520 		security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED);
521 
522 	if (result->character & H_CPU_CHAR_BCCTR_FLUSH_ASSIST)
523 		security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST);
524 
525 	if (result->character & H_CPU_CHAR_BCCTR_LINK_FLUSH_ASSIST)
526 		security_ftr_set(SEC_FTR_BCCTR_LINK_FLUSH_ASSIST);
527 
528 	if (result->behaviour & H_CPU_BEHAV_FLUSH_COUNT_CACHE)
529 		security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE);
530 
531 	if (result->behaviour & H_CPU_BEHAV_FLUSH_LINK_STACK)
532 		security_ftr_set(SEC_FTR_FLUSH_LINK_STACK);
533 
534 	/*
535 	 * The features below are enabled by default, so we instead look to see
536 	 * if firmware has *disabled* them, and clear them if so.
537 	 */
538 	if (!(result->behaviour & H_CPU_BEHAV_FAVOUR_SECURITY))
539 		security_ftr_clear(SEC_FTR_FAVOUR_SECURITY);
540 
541 	if (!(result->behaviour & H_CPU_BEHAV_L1D_FLUSH_PR))
542 		security_ftr_clear(SEC_FTR_L1D_FLUSH_PR);
543 
544 	if (!(result->behaviour & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR))
545 		security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR);
546 }
547 
548 void pseries_setup_security_mitigations(void)
549 {
550 	struct h_cpu_char_result result;
551 	enum l1d_flush_type types;
552 	bool enable;
553 	long rc;
554 
555 	/*
556 	 * Set features to the defaults assumed by init_cpu_char_feature_flags()
557 	 * so it can set/clear again any features that might have changed after
558 	 * migration, and in case the hypercall fails and it is not even called.
559 	 */
560 	powerpc_security_features = SEC_FTR_DEFAULT;
561 
562 	rc = plpar_get_cpu_characteristics(&result);
563 	if (rc == H_SUCCESS)
564 		init_cpu_char_feature_flags(&result);
565 
566 	/*
567 	 * We're the guest so this doesn't apply to us, clear it to simplify
568 	 * handling of it elsewhere.
569 	 */
570 	security_ftr_clear(SEC_FTR_L1D_FLUSH_HV);
571 
572 	types = L1D_FLUSH_FALLBACK;
573 
574 	if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2))
575 		types |= L1D_FLUSH_MTTRIG;
576 
577 	if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30))
578 		types |= L1D_FLUSH_ORI;
579 
580 	enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \
581 		 security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR);
582 
583 	setup_rfi_flush(types, enable);
584 	setup_count_cache_flush();
585 
586 	enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
587 		 security_ftr_enabled(SEC_FTR_L1D_FLUSH_ENTRY);
588 	setup_entry_flush(enable);
589 
590 	enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
591 		 security_ftr_enabled(SEC_FTR_L1D_FLUSH_UACCESS);
592 	setup_uaccess_flush(enable);
593 
594 	setup_stf_barrier();
595 }
596 
597 #ifdef CONFIG_PCI_IOV
598 enum rtas_iov_fw_value_map {
599 	NUM_RES_PROPERTY  = 0, /* Number of Resources */
600 	LOW_INT           = 1, /* Lowest 32 bits of Address */
601 	START_OF_ENTRIES  = 2, /* Always start of entry */
602 	APERTURE_PROPERTY = 2, /* Start of entry+ to  Aperture Size */
603 	WDW_SIZE_PROPERTY = 4, /* Start of entry+ to Window Size */
604 	NEXT_ENTRY        = 7  /* Go to next entry on array */
605 };
606 
607 enum get_iov_fw_value_index {
608 	BAR_ADDRS     = 1,    /*  Get Bar Address */
609 	APERTURE_SIZE = 2,    /*  Get Aperture Size */
610 	WDW_SIZE      = 3     /*  Get Window Size */
611 };
612 
613 static resource_size_t pseries_get_iov_fw_value(struct pci_dev *dev, int resno,
614 						enum get_iov_fw_value_index value)
615 {
616 	const int *indexes;
617 	struct device_node *dn = pci_device_to_OF_node(dev);
618 	int i, num_res, ret = 0;
619 
620 	indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL);
621 	if (!indexes)
622 		return  0;
623 
624 	/*
625 	 * First element in the array is the number of Bars
626 	 * returned.  Search through the list to find the matching
627 	 * bar
628 	 */
629 	num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1);
630 	if (resno >= num_res)
631 		return 0; /* or an errror */
632 
633 	i = START_OF_ENTRIES + NEXT_ENTRY * resno;
634 	switch (value) {
635 	case BAR_ADDRS:
636 		ret = of_read_number(&indexes[i], 2);
637 		break;
638 	case APERTURE_SIZE:
639 		ret = of_read_number(&indexes[i + APERTURE_PROPERTY], 2);
640 		break;
641 	case WDW_SIZE:
642 		ret = of_read_number(&indexes[i + WDW_SIZE_PROPERTY], 2);
643 		break;
644 	}
645 
646 	return ret;
647 }
648 
649 static void of_pci_set_vf_bar_size(struct pci_dev *dev, const int *indexes)
650 {
651 	struct resource *res;
652 	resource_size_t base, size;
653 	int i, r, num_res;
654 
655 	num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1);
656 	num_res = min_t(int, num_res, PCI_SRIOV_NUM_BARS);
657 	for (i = START_OF_ENTRIES, r = 0; r < num_res && r < PCI_SRIOV_NUM_BARS;
658 	     i += NEXT_ENTRY, r++) {
659 		res = &dev->resource[r + PCI_IOV_RESOURCES];
660 		base = of_read_number(&indexes[i], 2);
661 		size = of_read_number(&indexes[i + APERTURE_PROPERTY], 2);
662 		res->flags = pci_parse_of_flags(of_read_number
663 						(&indexes[i + LOW_INT], 1), 0);
664 		res->flags |= (IORESOURCE_MEM_64 | IORESOURCE_PCI_FIXED);
665 		res->name = pci_name(dev);
666 		res->start = base;
667 		res->end = base + size - 1;
668 	}
669 }
670 
671 static void of_pci_parse_iov_addrs(struct pci_dev *dev, const int *indexes)
672 {
673 	struct resource *res, *root, *conflict;
674 	resource_size_t base, size;
675 	int i, r, num_res;
676 
677 	/*
678 	 * First element in the array is the number of Bars
679 	 * returned.  Search through the list to find the matching
680 	 * bars assign them from firmware into resources structure.
681 	 */
682 	num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1);
683 	for (i = START_OF_ENTRIES, r = 0; r < num_res && r < PCI_SRIOV_NUM_BARS;
684 	     i += NEXT_ENTRY, r++) {
685 		res = &dev->resource[r + PCI_IOV_RESOURCES];
686 		base = of_read_number(&indexes[i], 2);
687 		size = of_read_number(&indexes[i + WDW_SIZE_PROPERTY], 2);
688 		res->name = pci_name(dev);
689 		res->start = base;
690 		res->end = base + size - 1;
691 		root = &iomem_resource;
692 		dev_dbg(&dev->dev,
693 			"pSeries IOV BAR %d: trying firmware assignment %pR\n",
694 			 r + PCI_IOV_RESOURCES, res);
695 		conflict = request_resource_conflict(root, res);
696 		if (conflict) {
697 			dev_info(&dev->dev,
698 				 "BAR %d: %pR conflicts with %s %pR\n",
699 				 r + PCI_IOV_RESOURCES, res,
700 				 conflict->name, conflict);
701 			res->flags |= IORESOURCE_UNSET;
702 		}
703 	}
704 }
705 
706 static void pseries_disable_sriov_resources(struct pci_dev *pdev)
707 {
708 	int i;
709 
710 	pci_warn(pdev, "No hypervisor support for SR-IOV on this device, IOV BARs disabled.\n");
711 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
712 		pdev->resource[i + PCI_IOV_RESOURCES].flags = 0;
713 }
714 
715 static void pseries_pci_fixup_resources(struct pci_dev *pdev)
716 {
717 	const int *indexes;
718 	struct device_node *dn = pci_device_to_OF_node(pdev);
719 
720 	/*Firmware must support open sriov otherwise dont configure*/
721 	indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL);
722 	if (indexes)
723 		of_pci_set_vf_bar_size(pdev, indexes);
724 	else
725 		pseries_disable_sriov_resources(pdev);
726 }
727 
728 static void pseries_pci_fixup_iov_resources(struct pci_dev *pdev)
729 {
730 	const int *indexes;
731 	struct device_node *dn = pci_device_to_OF_node(pdev);
732 
733 	if (!pdev->is_physfn || pci_dev_is_added(pdev))
734 		return;
735 	/*Firmware must support open sriov otherwise dont configure*/
736 	indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL);
737 	if (indexes)
738 		of_pci_parse_iov_addrs(pdev, indexes);
739 	else
740 		pseries_disable_sriov_resources(pdev);
741 }
742 
743 static resource_size_t pseries_pci_iov_resource_alignment(struct pci_dev *pdev,
744 							  int resno)
745 {
746 	const __be32 *reg;
747 	struct device_node *dn = pci_device_to_OF_node(pdev);
748 
749 	/*Firmware must support open sriov otherwise report regular alignment*/
750 	reg = of_get_property(dn, "ibm,is-open-sriov-pf", NULL);
751 	if (!reg)
752 		return pci_iov_resource_size(pdev, resno);
753 
754 	if (!pdev->is_physfn)
755 		return 0;
756 	return pseries_get_iov_fw_value(pdev,
757 					resno - PCI_IOV_RESOURCES,
758 					APERTURE_SIZE);
759 }
760 #endif
761 
762 static void __init pSeries_setup_arch(void)
763 {
764 	set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);
765 
766 	/* Discover PIC type and setup ppc_md accordingly */
767 	smp_init_pseries();
768 
769 
770 	if (radix_enabled() && !mmu_has_feature(MMU_FTR_GTSE))
771 		if (!firmware_has_feature(FW_FEATURE_RPT_INVALIDATE))
772 			panic("BUG: Radix support requires either GTSE or RPT_INVALIDATE\n");
773 
774 
775 	/* openpic global configuration register (64-bit format). */
776 	/* openpic Interrupt Source Unit pointer (64-bit format). */
777 	/* python0 facility area (mmio) (64-bit format) REAL address. */
778 
779 	/* init to some ~sane value until calibrate_delay() runs */
780 	loops_per_jiffy = 50000000;
781 
782 	fwnmi_init();
783 
784 	pseries_setup_security_mitigations();
785 	pseries_lpar_read_hblkrm_characteristics();
786 
787 	/* By default, only probe PCI (can be overridden by rtas_pci) */
788 	pci_add_flags(PCI_PROBE_ONLY);
789 
790 	/* Find and initialize PCI host bridges */
791 	init_pci_config_tokens();
792 	of_reconfig_notifier_register(&pci_dn_reconfig_nb);
793 
794 	pSeries_nvram_init();
795 
796 	if (firmware_has_feature(FW_FEATURE_LPAR)) {
797 		vpa_init(boot_cpuid);
798 
799 		if (lppaca_shared_proc(get_lppaca())) {
800 			static_branch_enable(&shared_processor);
801 			pv_spinlocks_init();
802 		}
803 
804 		ppc_md.power_save = pseries_lpar_idle;
805 		ppc_md.enable_pmcs = pseries_lpar_enable_pmcs;
806 #ifdef CONFIG_PCI_IOV
807 		ppc_md.pcibios_fixup_resources =
808 			pseries_pci_fixup_resources;
809 		ppc_md.pcibios_fixup_sriov =
810 			pseries_pci_fixup_iov_resources;
811 		ppc_md.pcibios_iov_resource_alignment =
812 			pseries_pci_iov_resource_alignment;
813 #endif
814 	} else {
815 		/* No special idle routine */
816 		ppc_md.enable_pmcs = power4_enable_pmcs;
817 	}
818 
819 	ppc_md.pcibios_root_bridge_prepare = pseries_root_bridge_prepare;
820 
821 	if (swiotlb_force == SWIOTLB_FORCE)
822 		ppc_swiotlb_enable = 1;
823 }
824 
825 static void pseries_panic(char *str)
826 {
827 	panic_flush_kmsg_end();
828 	rtas_os_term(str);
829 }
830 
831 static int __init pSeries_init_panel(void)
832 {
833 	/* Manually leave the kernel version on the panel. */
834 #ifdef __BIG_ENDIAN__
835 	ppc_md.progress("Linux ppc64\n", 0);
836 #else
837 	ppc_md.progress("Linux ppc64le\n", 0);
838 #endif
839 	ppc_md.progress(init_utsname()->version, 0);
840 
841 	return 0;
842 }
843 machine_arch_initcall(pseries, pSeries_init_panel);
844 
845 static int pseries_set_dabr(unsigned long dabr, unsigned long dabrx)
846 {
847 	return plpar_hcall_norets(H_SET_DABR, dabr);
848 }
849 
850 static int pseries_set_xdabr(unsigned long dabr, unsigned long dabrx)
851 {
852 	/* Have to set at least one bit in the DABRX according to PAPR */
853 	if (dabrx == 0 && dabr == 0)
854 		dabrx = DABRX_USER;
855 	/* PAPR says we can only set kernel and user bits */
856 	dabrx &= DABRX_KERNEL | DABRX_USER;
857 
858 	return plpar_hcall_norets(H_SET_XDABR, dabr, dabrx);
859 }
860 
861 static int pseries_set_dawr(int nr, unsigned long dawr, unsigned long dawrx)
862 {
863 	/* PAPR says we can't set HYP */
864 	dawrx &= ~DAWRX_HYP;
865 
866 	if (nr == 0)
867 		return plpar_set_watchpoint0(dawr, dawrx);
868 	else
869 		return plpar_set_watchpoint1(dawr, dawrx);
870 }
871 
872 #define CMO_CHARACTERISTICS_TOKEN 44
873 #define CMO_MAXLENGTH 1026
874 
875 void pSeries_coalesce_init(void)
876 {
877 	struct hvcall_mpp_x_data mpp_x_data;
878 
879 	if (firmware_has_feature(FW_FEATURE_CMO) && !h_get_mpp_x(&mpp_x_data))
880 		powerpc_firmware_features |= FW_FEATURE_XCMO;
881 	else
882 		powerpc_firmware_features &= ~FW_FEATURE_XCMO;
883 }
884 
885 /**
886  * fw_cmo_feature_init - FW_FEATURE_CMO is not stored in ibm,hypertas-functions,
887  * handle that here. (Stolen from parse_system_parameter_string)
888  */
889 static void pSeries_cmo_feature_init(void)
890 {
891 	char *ptr, *key, *value, *end;
892 	int call_status;
893 	int page_order = IOMMU_PAGE_SHIFT_4K;
894 
895 	pr_debug(" -> fw_cmo_feature_init()\n");
896 	spin_lock(&rtas_data_buf_lock);
897 	memset(rtas_data_buf, 0, RTAS_DATA_BUF_SIZE);
898 	call_status = rtas_call(rtas_token("ibm,get-system-parameter"), 3, 1,
899 				NULL,
900 				CMO_CHARACTERISTICS_TOKEN,
901 				__pa(rtas_data_buf),
902 				RTAS_DATA_BUF_SIZE);
903 
904 	if (call_status != 0) {
905 		spin_unlock(&rtas_data_buf_lock);
906 		pr_debug("CMO not available\n");
907 		pr_debug(" <- fw_cmo_feature_init()\n");
908 		return;
909 	}
910 
911 	end = rtas_data_buf + CMO_MAXLENGTH - 2;
912 	ptr = rtas_data_buf + 2;	/* step over strlen value */
913 	key = value = ptr;
914 
915 	while (*ptr && (ptr <= end)) {
916 		/* Separate the key and value by replacing '=' with '\0' and
917 		 * point the value at the string after the '='
918 		 */
919 		if (ptr[0] == '=') {
920 			ptr[0] = '\0';
921 			value = ptr + 1;
922 		} else if (ptr[0] == '\0' || ptr[0] == ',') {
923 			/* Terminate the string containing the key/value pair */
924 			ptr[0] = '\0';
925 
926 			if (key == value) {
927 				pr_debug("Malformed key/value pair\n");
928 				/* Never found a '=', end processing */
929 				break;
930 			}
931 
932 			if (0 == strcmp(key, "CMOPageSize"))
933 				page_order = simple_strtol(value, NULL, 10);
934 			else if (0 == strcmp(key, "PrPSP"))
935 				CMO_PrPSP = simple_strtol(value, NULL, 10);
936 			else if (0 == strcmp(key, "SecPSP"))
937 				CMO_SecPSP = simple_strtol(value, NULL, 10);
938 			value = key = ptr + 1;
939 		}
940 		ptr++;
941 	}
942 
943 	/* Page size is returned as the power of 2 of the page size,
944 	 * convert to the page size in bytes before returning
945 	 */
946 	CMO_PageSize = 1 << page_order;
947 	pr_debug("CMO_PageSize = %lu\n", CMO_PageSize);
948 
949 	if (CMO_PrPSP != -1 || CMO_SecPSP != -1) {
950 		pr_info("CMO enabled\n");
951 		pr_debug("CMO enabled, PrPSP=%d, SecPSP=%d\n", CMO_PrPSP,
952 		         CMO_SecPSP);
953 		powerpc_firmware_features |= FW_FEATURE_CMO;
954 		pSeries_coalesce_init();
955 	} else
956 		pr_debug("CMO not enabled, PrPSP=%d, SecPSP=%d\n", CMO_PrPSP,
957 		         CMO_SecPSP);
958 	spin_unlock(&rtas_data_buf_lock);
959 	pr_debug(" <- fw_cmo_feature_init()\n");
960 }
961 
962 /*
963  * Early initialization.  Relocation is on but do not reference unbolted pages
964  */
965 static void __init pseries_init(void)
966 {
967 	pr_debug(" -> pseries_init()\n");
968 
969 #ifdef CONFIG_HVC_CONSOLE
970 	if (firmware_has_feature(FW_FEATURE_LPAR))
971 		hvc_vio_init_early();
972 #endif
973 	if (firmware_has_feature(FW_FEATURE_XDABR))
974 		ppc_md.set_dabr = pseries_set_xdabr;
975 	else if (firmware_has_feature(FW_FEATURE_DABR))
976 		ppc_md.set_dabr = pseries_set_dabr;
977 
978 	if (firmware_has_feature(FW_FEATURE_SET_MODE))
979 		ppc_md.set_dawr = pseries_set_dawr;
980 
981 	pSeries_cmo_feature_init();
982 	iommu_init_early_pSeries();
983 
984 	pr_debug(" <- pseries_init()\n");
985 }
986 
987 /**
988  * pseries_power_off - tell firmware about how to power off the system.
989  *
990  * This function calls either the power-off rtas token in normal cases
991  * or the ibm,power-off-ups token (if present & requested) in case of
992  * a power failure. If power-off token is used, power on will only be
993  * possible with power button press. If ibm,power-off-ups token is used
994  * it will allow auto poweron after power is restored.
995  */
996 static void pseries_power_off(void)
997 {
998 	int rc;
999 	int rtas_poweroff_ups_token = rtas_token("ibm,power-off-ups");
1000 
1001 	if (rtas_flash_term_hook)
1002 		rtas_flash_term_hook(SYS_POWER_OFF);
1003 
1004 	if (rtas_poweron_auto == 0 ||
1005 		rtas_poweroff_ups_token == RTAS_UNKNOWN_SERVICE) {
1006 		rc = rtas_call(rtas_token("power-off"), 2, 1, NULL, -1, -1);
1007 		printk(KERN_INFO "RTAS power-off returned %d\n", rc);
1008 	} else {
1009 		rc = rtas_call(rtas_poweroff_ups_token, 0, 1, NULL);
1010 		printk(KERN_INFO "RTAS ibm,power-off-ups returned %d\n", rc);
1011 	}
1012 	for (;;);
1013 }
1014 
1015 static int __init pSeries_probe(void)
1016 {
1017 	if (!of_node_is_type(of_root, "chrp"))
1018 		return 0;
1019 
1020 	/* Cell blades firmware claims to be chrp while it's not. Until this
1021 	 * is fixed, we need to avoid those here.
1022 	 */
1023 	if (of_machine_is_compatible("IBM,CPBW-1.0") ||
1024 	    of_machine_is_compatible("IBM,CBEA"))
1025 		return 0;
1026 
1027 	pm_power_off = pseries_power_off;
1028 
1029 	pr_debug("Machine is%s LPAR !\n",
1030 	         (powerpc_firmware_features & FW_FEATURE_LPAR) ? "" : " not");
1031 
1032 	pseries_init();
1033 
1034 	return 1;
1035 }
1036 
1037 static int pSeries_pci_probe_mode(struct pci_bus *bus)
1038 {
1039 	if (firmware_has_feature(FW_FEATURE_LPAR))
1040 		return PCI_PROBE_DEVTREE;
1041 	return PCI_PROBE_NORMAL;
1042 }
1043 
1044 struct pci_controller_ops pseries_pci_controller_ops = {
1045 	.probe_mode		= pSeries_pci_probe_mode,
1046 };
1047 
1048 define_machine(pseries) {
1049 	.name			= "pSeries",
1050 	.probe			= pSeries_probe,
1051 	.setup_arch		= pSeries_setup_arch,
1052 	.init_IRQ		= pseries_init_irq,
1053 	.show_cpuinfo		= pSeries_show_cpuinfo,
1054 	.log_error		= pSeries_log_error,
1055 	.discover_phbs		= pSeries_discover_phbs,
1056 	.pcibios_fixup		= pSeries_final_fixup,
1057 	.restart		= rtas_restart,
1058 	.halt			= rtas_halt,
1059 	.panic			= pseries_panic,
1060 	.get_boot_time		= rtas_get_boot_time,
1061 	.get_rtc_time		= rtas_get_rtc_time,
1062 	.set_rtc_time		= rtas_set_rtc_time,
1063 	.calibrate_decr		= generic_calibrate_decr,
1064 	.progress		= rtas_progress,
1065 	.system_reset_exception = pSeries_system_reset_exception,
1066 	.machine_check_early	= pseries_machine_check_realmode,
1067 	.machine_check_exception = pSeries_machine_check_exception,
1068 #ifdef CONFIG_KEXEC_CORE
1069 	.machine_kexec          = pSeries_machine_kexec,
1070 	.kexec_cpu_down         = pseries_kexec_cpu_down,
1071 #endif
1072 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
1073 	.memory_block_size	= pseries_memory_block_size,
1074 #endif
1075 };
1076