1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
4  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
5  *
6  * pSeries specific routines for PCI.
7  */
8 
9 #include <linux/init.h>
10 #include <linux/ioport.h>
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/string.h>
14 
15 #include <asm/eeh.h>
16 #include <asm/pci-bridge.h>
17 #include <asm/prom.h>
18 #include <asm/ppc-pci.h>
19 #include <asm/pci.h>
20 #include "pseries.h"
21 
22 #if 0
23 void pcibios_name_device(struct pci_dev *dev)
24 {
25 	struct device_node *dn;
26 
27 	/*
28 	 * Add IBM loc code (slot) as a prefix to the device names for service
29 	 */
30 	dn = pci_device_to_OF_node(dev);
31 	if (dn) {
32 		const char *loc_code = of_get_property(dn, "ibm,loc-code",
33 				NULL);
34 		if (loc_code) {
35 			int loc_len = strlen(loc_code);
36 			if (loc_len < sizeof(dev->dev.name)) {
37 				memmove(dev->dev.name+loc_len+1, dev->dev.name,
38 					sizeof(dev->dev.name)-loc_len-1);
39 				memcpy(dev->dev.name, loc_code, loc_len);
40 				dev->dev.name[loc_len] = ' ';
41 				dev->dev.name[sizeof(dev->dev.name)-1] = '\0';
42 			}
43 		}
44 	}
45 }
46 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_name_device);
47 #endif
48 
49 #ifdef CONFIG_PCI_IOV
50 #define MAX_VFS_FOR_MAP_PE 256
51 struct pe_map_bar_entry {
52 	__be64     bar;       /* Input:  Virtual Function BAR */
53 	__be16     rid;       /* Input:  Virtual Function Router ID */
54 	__be16     pe_num;    /* Output: Virtual Function PE Number */
55 	__be32     reserved;  /* Reserved Space */
56 };
57 
58 int pseries_send_map_pe(struct pci_dev *pdev,
59 			u16 num_vfs,
60 			struct pe_map_bar_entry *vf_pe_array)
61 {
62 	struct pci_dn *pdn;
63 	int rc;
64 	unsigned long buid, addr;
65 	int ibm_map_pes = rtas_token("ibm,open-sriov-map-pe-number");
66 
67 	if (ibm_map_pes == RTAS_UNKNOWN_SERVICE)
68 		return -EINVAL;
69 
70 	pdn = pci_get_pdn(pdev);
71 	addr = rtas_config_addr(pdn->busno, pdn->devfn, 0);
72 	buid = pdn->phb->buid;
73 	spin_lock(&rtas_data_buf_lock);
74 	memcpy(rtas_data_buf, vf_pe_array,
75 	       RTAS_DATA_BUF_SIZE);
76 	rc = rtas_call(ibm_map_pes, 5, 1, NULL, addr,
77 		       BUID_HI(buid), BUID_LO(buid),
78 		       rtas_data_buf,
79 		       num_vfs * sizeof(struct pe_map_bar_entry));
80 	memcpy(vf_pe_array, rtas_data_buf, RTAS_DATA_BUF_SIZE);
81 	spin_unlock(&rtas_data_buf_lock);
82 
83 	if (rc)
84 		dev_err(&pdev->dev,
85 			"%s: Failed to associate pes PE#%lx, rc=%x\n",
86 			__func__,  addr, rc);
87 
88 	return rc;
89 }
90 
91 void pseries_set_pe_num(struct pci_dev *pdev, u16 vf_index, __be16 pe_num)
92 {
93 	struct pci_dn *pdn;
94 
95 	pdn = pci_get_pdn(pdev);
96 	pdn->pe_num_map[vf_index] = be16_to_cpu(pe_num);
97 	dev_dbg(&pdev->dev, "VF %04x:%02x:%02x.%x associated with PE#%x\n",
98 		pci_domain_nr(pdev->bus),
99 		pdev->bus->number,
100 		PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
101 		PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)),
102 		pdn->pe_num_map[vf_index]);
103 }
104 
105 int pseries_associate_pes(struct pci_dev *pdev, u16 num_vfs)
106 {
107 	struct pci_dn *pdn;
108 	int i, rc, vf_index;
109 	struct pe_map_bar_entry *vf_pe_array;
110 	struct resource *res;
111 	u64 size;
112 
113 	vf_pe_array = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
114 	if (!vf_pe_array)
115 		return -ENOMEM;
116 
117 	pdn = pci_get_pdn(pdev);
118 	/* create firmware structure to associate pes */
119 	for (vf_index = 0; vf_index < num_vfs; vf_index++) {
120 		pdn->pe_num_map[vf_index] = IODA_INVALID_PE;
121 		for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
122 			res = &pdev->resource[i + PCI_IOV_RESOURCES];
123 			if (!res->parent)
124 				continue;
125 			size = pcibios_iov_resource_alignment(pdev, i +
126 					PCI_IOV_RESOURCES);
127 			vf_pe_array[vf_index].bar =
128 				cpu_to_be64(res->start + size * vf_index);
129 			vf_pe_array[vf_index].rid =
130 				cpu_to_be16((pci_iov_virtfn_bus(pdev, vf_index)
131 					    << 8) | pci_iov_virtfn_devfn(pdev,
132 					    vf_index));
133 			vf_pe_array[vf_index].pe_num =
134 				cpu_to_be16(IODA_INVALID_PE);
135 		}
136 	}
137 
138 	rc = pseries_send_map_pe(pdev, num_vfs, vf_pe_array);
139 	/* Only zero is success */
140 	if (!rc)
141 		for (vf_index = 0; vf_index < num_vfs; vf_index++)
142 			pseries_set_pe_num(pdev, vf_index,
143 					   vf_pe_array[vf_index].pe_num);
144 
145 	kfree(vf_pe_array);
146 	return rc;
147 }
148 
149 int pseries_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
150 {
151 	struct pci_dn         *pdn;
152 	int                    rc;
153 	const int *max_vfs;
154 	int max_config_vfs;
155 	struct device_node *dn = pci_device_to_OF_node(pdev);
156 
157 	max_vfs = of_get_property(dn, "ibm,number-of-configurable-vfs", NULL);
158 
159 	if (!max_vfs)
160 		return -EINVAL;
161 
162 	/* First integer stores max config */
163 	max_config_vfs = of_read_number(&max_vfs[0], 1);
164 	if (max_config_vfs < num_vfs && num_vfs > MAX_VFS_FOR_MAP_PE) {
165 		dev_err(&pdev->dev,
166 			"Num VFs %x > %x Configurable VFs\n",
167 			num_vfs, (num_vfs > MAX_VFS_FOR_MAP_PE) ?
168 			MAX_VFS_FOR_MAP_PE : max_config_vfs);
169 		return -EINVAL;
170 	}
171 
172 	pdn = pci_get_pdn(pdev);
173 	pdn->pe_num_map = kmalloc_array(num_vfs,
174 					sizeof(*pdn->pe_num_map),
175 					GFP_KERNEL);
176 	if (!pdn->pe_num_map)
177 		return -ENOMEM;
178 
179 	rc = pseries_associate_pes(pdev, num_vfs);
180 
181 	/* Anything other than zero is failure */
182 	if (rc) {
183 		dev_err(&pdev->dev, "Failure to enable sriov: %x\n", rc);
184 		kfree(pdn->pe_num_map);
185 	} else {
186 		pci_vf_drivers_autoprobe(pdev, false);
187 	}
188 
189 	return rc;
190 }
191 
192 int pseries_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
193 {
194 	/* Allocate PCI data */
195 	add_dev_pci_data(pdev);
196 	return pseries_pci_sriov_enable(pdev, num_vfs);
197 }
198 
199 int pseries_pcibios_sriov_disable(struct pci_dev *pdev)
200 {
201 	struct pci_dn         *pdn;
202 
203 	pdn = pci_get_pdn(pdev);
204 	/* Releasing pe_num_map */
205 	kfree(pdn->pe_num_map);
206 	/* Release PCI data */
207 	remove_dev_pci_data(pdev);
208 	pci_vf_drivers_autoprobe(pdev, true);
209 	return 0;
210 }
211 #endif
212 
213 static void __init pSeries_request_regions(void)
214 {
215 	if (!isa_io_base)
216 		return;
217 
218 	request_region(0x20,0x20,"pic1");
219 	request_region(0xa0,0x20,"pic2");
220 	request_region(0x00,0x20,"dma1");
221 	request_region(0x40,0x20,"timer");
222 	request_region(0x80,0x10,"dma page reg");
223 	request_region(0xc0,0x20,"dma2");
224 }
225 
226 void __init pSeries_final_fixup(void)
227 {
228 	struct pci_controller *hose;
229 
230 	pSeries_request_regions();
231 
232 	eeh_show_enabled();
233 
234 #ifdef CONFIG_PCI_IOV
235 	ppc_md.pcibios_sriov_enable = pseries_pcibios_sriov_enable;
236 	ppc_md.pcibios_sriov_disable = pseries_pcibios_sriov_disable;
237 #endif
238 	list_for_each_entry(hose, &hose_list, list_node) {
239 		struct device_node *dn = hose->dn, *nvdn;
240 
241 		while (1) {
242 			dn = of_find_all_nodes(dn);
243 			if (!dn)
244 				break;
245 			nvdn = of_parse_phandle(dn, "ibm,nvlink", 0);
246 			if (!nvdn)
247 				continue;
248 			if (!of_device_is_compatible(nvdn, "ibm,npu-link"))
249 				continue;
250 			if (!of_device_is_compatible(nvdn->parent,
251 						"ibm,power9-npu"))
252 				continue;
253 #ifdef CONFIG_PPC_POWERNV
254 			WARN_ON_ONCE(pnv_npu2_init(hose));
255 #endif
256 			break;
257 		}
258 	}
259 }
260 
261 /*
262  * Assume the winbond 82c105 is the IDE controller on a
263  * p610/p615/p630. We should probably be more careful in case
264  * someone tries to plug in a similar adapter.
265  */
266 static void fixup_winbond_82c105(struct pci_dev* dev)
267 {
268 	int i;
269 	unsigned int reg;
270 
271 	if (!machine_is(pseries))
272 		return;
273 
274 	printk("Using INTC for W82c105 IDE controller.\n");
275 	pci_read_config_dword(dev, 0x40, &reg);
276 	/* Enable LEGIRQ to use INTC instead of ISA interrupts */
277 	pci_write_config_dword(dev, 0x40, reg | (1<<11));
278 
279 	for (i = 0; i < DEVICE_COUNT_RESOURCE; ++i) {
280 		/* zap the 2nd function of the winbond chip */
281 		if (dev->resource[i].flags & IORESOURCE_IO
282 		    && dev->bus->number == 0 && dev->devfn == 0x81)
283 			dev->resource[i].flags &= ~IORESOURCE_IO;
284 		if (dev->resource[i].start == 0 && dev->resource[i].end) {
285 			dev->resource[i].flags = 0;
286 			dev->resource[i].end = 0;
287 		}
288 	}
289 }
290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
291 			 fixup_winbond_82c105);
292 
293 int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
294 {
295 	struct device_node *dn, *pdn;
296 	struct pci_bus *bus;
297 	u32 pcie_link_speed_stats[2];
298 	int rc;
299 
300 	bus = bridge->bus;
301 
302 	/* Rely on the pcibios_free_controller_deferred() callback. */
303 	pci_set_host_bridge_release(bridge, pcibios_free_controller_deferred,
304 					(void *) pci_bus_to_host(bus));
305 
306 	dn = pcibios_get_phb_of_node(bus);
307 	if (!dn)
308 		return 0;
309 
310 	for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) {
311 		rc = of_property_read_u32_array(pdn,
312 				"ibm,pcie-link-speed-stats",
313 				&pcie_link_speed_stats[0], 2);
314 		if (!rc)
315 			break;
316 	}
317 
318 	of_node_put(pdn);
319 
320 	if (rc) {
321 		pr_debug("no ibm,pcie-link-speed-stats property\n");
322 		return 0;
323 	}
324 
325 	switch (pcie_link_speed_stats[0]) {
326 	case 0x01:
327 		bus->max_bus_speed = PCIE_SPEED_2_5GT;
328 		break;
329 	case 0x02:
330 		bus->max_bus_speed = PCIE_SPEED_5_0GT;
331 		break;
332 	case 0x04:
333 		bus->max_bus_speed = PCIE_SPEED_8_0GT;
334 		break;
335 	default:
336 		bus->max_bus_speed = PCI_SPEED_UNKNOWN;
337 		break;
338 	}
339 
340 	switch (pcie_link_speed_stats[1]) {
341 	case 0x01:
342 		bus->cur_bus_speed = PCIE_SPEED_2_5GT;
343 		break;
344 	case 0x02:
345 		bus->cur_bus_speed = PCIE_SPEED_5_0GT;
346 		break;
347 	case 0x04:
348 		bus->cur_bus_speed = PCIE_SPEED_8_0GT;
349 		break;
350 	default:
351 		bus->cur_bus_speed = PCI_SPEED_UNKNOWN;
352 		break;
353 	}
354 
355 	return 0;
356 }
357