1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
4  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
5  *
6  * pSeries specific routines for PCI.
7  */
8 
9 #include <linux/init.h>
10 #include <linux/ioport.h>
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/string.h>
14 
15 #include <asm/eeh.h>
16 #include <asm/pci-bridge.h>
17 #include <asm/prom.h>
18 #include <asm/ppc-pci.h>
19 #include <asm/pci.h>
20 #include "pseries.h"
21 
22 #if 0
23 void pcibios_name_device(struct pci_dev *dev)
24 {
25 	struct device_node *dn;
26 
27 	/*
28 	 * Add IBM loc code (slot) as a prefix to the device names for service
29 	 */
30 	dn = pci_device_to_OF_node(dev);
31 	if (dn) {
32 		const char *loc_code = of_get_property(dn, "ibm,loc-code",
33 				NULL);
34 		if (loc_code) {
35 			int loc_len = strlen(loc_code);
36 			if (loc_len < sizeof(dev->dev.name)) {
37 				memmove(dev->dev.name+loc_len+1, dev->dev.name,
38 					sizeof(dev->dev.name)-loc_len-1);
39 				memcpy(dev->dev.name, loc_code, loc_len);
40 				dev->dev.name[loc_len] = ' ';
41 				dev->dev.name[sizeof(dev->dev.name)-1] = '\0';
42 			}
43 		}
44 	}
45 }
46 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_name_device);
47 #endif
48 
49 #ifdef CONFIG_PCI_IOV
50 #define MAX_VFS_FOR_MAP_PE 256
51 struct pe_map_bar_entry {
52 	__be64     bar;       /* Input:  Virtual Function BAR */
53 	__be16     rid;       /* Input:  Virtual Function Router ID */
54 	__be16     pe_num;    /* Output: Virtual Function PE Number */
55 	__be32     reserved;  /* Reserved Space */
56 };
57 
58 static int pseries_send_map_pe(struct pci_dev *pdev, u16 num_vfs,
59 			       struct pe_map_bar_entry *vf_pe_array)
60 {
61 	struct pci_dn *pdn;
62 	int rc;
63 	unsigned long buid, addr;
64 	int ibm_map_pes = rtas_token("ibm,open-sriov-map-pe-number");
65 
66 	if (ibm_map_pes == RTAS_UNKNOWN_SERVICE)
67 		return -EINVAL;
68 
69 	pdn = pci_get_pdn(pdev);
70 	addr = rtas_config_addr(pdn->busno, pdn->devfn, 0);
71 	buid = pdn->phb->buid;
72 	spin_lock(&rtas_data_buf_lock);
73 	memcpy(rtas_data_buf, vf_pe_array,
74 	       RTAS_DATA_BUF_SIZE);
75 	rc = rtas_call(ibm_map_pes, 5, 1, NULL, addr,
76 		       BUID_HI(buid), BUID_LO(buid),
77 		       rtas_data_buf,
78 		       num_vfs * sizeof(struct pe_map_bar_entry));
79 	memcpy(vf_pe_array, rtas_data_buf, RTAS_DATA_BUF_SIZE);
80 	spin_unlock(&rtas_data_buf_lock);
81 
82 	if (rc)
83 		dev_err(&pdev->dev,
84 			"%s: Failed to associate pes PE#%lx, rc=%x\n",
85 			__func__,  addr, rc);
86 
87 	return rc;
88 }
89 
90 static void pseries_set_pe_num(struct pci_dev *pdev, u16 vf_index, __be16 pe_num)
91 {
92 	struct pci_dn *pdn;
93 
94 	pdn = pci_get_pdn(pdev);
95 	pdn->pe_num_map[vf_index] = be16_to_cpu(pe_num);
96 	dev_dbg(&pdev->dev, "VF %04x:%02x:%02x.%x associated with PE#%x\n",
97 		pci_domain_nr(pdev->bus),
98 		pdev->bus->number,
99 		PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
100 		PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)),
101 		pdn->pe_num_map[vf_index]);
102 }
103 
104 static int pseries_associate_pes(struct pci_dev *pdev, u16 num_vfs)
105 {
106 	struct pci_dn *pdn;
107 	int i, rc, vf_index;
108 	struct pe_map_bar_entry *vf_pe_array;
109 	struct resource *res;
110 	u64 size;
111 
112 	vf_pe_array = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
113 	if (!vf_pe_array)
114 		return -ENOMEM;
115 
116 	pdn = pci_get_pdn(pdev);
117 	/* create firmware structure to associate pes */
118 	for (vf_index = 0; vf_index < num_vfs; vf_index++) {
119 		pdn->pe_num_map[vf_index] = IODA_INVALID_PE;
120 		for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
121 			res = &pdev->resource[i + PCI_IOV_RESOURCES];
122 			if (!res->parent)
123 				continue;
124 			size = pcibios_iov_resource_alignment(pdev, i +
125 					PCI_IOV_RESOURCES);
126 			vf_pe_array[vf_index].bar =
127 				cpu_to_be64(res->start + size * vf_index);
128 			vf_pe_array[vf_index].rid =
129 				cpu_to_be16((pci_iov_virtfn_bus(pdev, vf_index)
130 					    << 8) | pci_iov_virtfn_devfn(pdev,
131 					    vf_index));
132 			vf_pe_array[vf_index].pe_num =
133 				cpu_to_be16(IODA_INVALID_PE);
134 		}
135 	}
136 
137 	rc = pseries_send_map_pe(pdev, num_vfs, vf_pe_array);
138 	/* Only zero is success */
139 	if (!rc)
140 		for (vf_index = 0; vf_index < num_vfs; vf_index++)
141 			pseries_set_pe_num(pdev, vf_index,
142 					   vf_pe_array[vf_index].pe_num);
143 
144 	kfree(vf_pe_array);
145 	return rc;
146 }
147 
148 static int pseries_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
149 {
150 	struct pci_dn         *pdn;
151 	int                    rc;
152 	const int *max_vfs;
153 	int max_config_vfs;
154 	struct device_node *dn = pci_device_to_OF_node(pdev);
155 
156 	max_vfs = of_get_property(dn, "ibm,number-of-configurable-vfs", NULL);
157 
158 	if (!max_vfs)
159 		return -EINVAL;
160 
161 	/* First integer stores max config */
162 	max_config_vfs = of_read_number(&max_vfs[0], 1);
163 	if (max_config_vfs < num_vfs && num_vfs > MAX_VFS_FOR_MAP_PE) {
164 		dev_err(&pdev->dev,
165 			"Num VFs %x > %x Configurable VFs\n",
166 			num_vfs, (num_vfs > MAX_VFS_FOR_MAP_PE) ?
167 			MAX_VFS_FOR_MAP_PE : max_config_vfs);
168 		return -EINVAL;
169 	}
170 
171 	pdn = pci_get_pdn(pdev);
172 	pdn->pe_num_map = kmalloc_array(num_vfs,
173 					sizeof(*pdn->pe_num_map),
174 					GFP_KERNEL);
175 	if (!pdn->pe_num_map)
176 		return -ENOMEM;
177 
178 	rc = pseries_associate_pes(pdev, num_vfs);
179 
180 	/* Anything other than zero is failure */
181 	if (rc) {
182 		dev_err(&pdev->dev, "Failure to enable sriov: %x\n", rc);
183 		kfree(pdn->pe_num_map);
184 	} else {
185 		pci_vf_drivers_autoprobe(pdev, false);
186 	}
187 
188 	return rc;
189 }
190 
191 static int pseries_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
192 {
193 	/* Allocate PCI data */
194 	add_sriov_vf_pdns(pdev);
195 	return pseries_pci_sriov_enable(pdev, num_vfs);
196 }
197 
198 static int pseries_pcibios_sriov_disable(struct pci_dev *pdev)
199 {
200 	struct pci_dn         *pdn;
201 
202 	pdn = pci_get_pdn(pdev);
203 	/* Releasing pe_num_map */
204 	kfree(pdn->pe_num_map);
205 	/* Release PCI data */
206 	remove_sriov_vf_pdns(pdev);
207 	pci_vf_drivers_autoprobe(pdev, true);
208 	return 0;
209 }
210 #endif
211 
212 static void __init pSeries_request_regions(void)
213 {
214 	if (!isa_io_base)
215 		return;
216 
217 	request_region(0x20,0x20,"pic1");
218 	request_region(0xa0,0x20,"pic2");
219 	request_region(0x00,0x20,"dma1");
220 	request_region(0x40,0x20,"timer");
221 	request_region(0x80,0x10,"dma page reg");
222 	request_region(0xc0,0x20,"dma2");
223 }
224 
225 void __init pSeries_final_fixup(void)
226 {
227 	pSeries_request_regions();
228 
229 	eeh_show_enabled();
230 
231 #ifdef CONFIG_PCI_IOV
232 	ppc_md.pcibios_sriov_enable = pseries_pcibios_sriov_enable;
233 	ppc_md.pcibios_sriov_disable = pseries_pcibios_sriov_disable;
234 #endif
235 }
236 
237 /*
238  * Assume the winbond 82c105 is the IDE controller on a
239  * p610/p615/p630. We should probably be more careful in case
240  * someone tries to plug in a similar adapter.
241  */
242 static void fixup_winbond_82c105(struct pci_dev* dev)
243 {
244 	int i;
245 	unsigned int reg;
246 
247 	if (!machine_is(pseries))
248 		return;
249 
250 	printk("Using INTC for W82c105 IDE controller.\n");
251 	pci_read_config_dword(dev, 0x40, &reg);
252 	/* Enable LEGIRQ to use INTC instead of ISA interrupts */
253 	pci_write_config_dword(dev, 0x40, reg | (1<<11));
254 
255 	for (i = 0; i < DEVICE_COUNT_RESOURCE; ++i) {
256 		/* zap the 2nd function of the winbond chip */
257 		if (dev->resource[i].flags & IORESOURCE_IO
258 		    && dev->bus->number == 0 && dev->devfn == 0x81)
259 			dev->resource[i].flags &= ~IORESOURCE_IO;
260 		if (dev->resource[i].start == 0 && dev->resource[i].end) {
261 			dev->resource[i].flags = 0;
262 			dev->resource[i].end = 0;
263 		}
264 	}
265 }
266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
267 			 fixup_winbond_82c105);
268 
269 static enum pci_bus_speed prop_to_pci_speed(u32 prop)
270 {
271 	switch (prop) {
272 	case 0x01:
273 		return PCIE_SPEED_2_5GT;
274 	case 0x02:
275 		return PCIE_SPEED_5_0GT;
276 	case 0x04:
277 		return PCIE_SPEED_8_0GT;
278 	case 0x08:
279 		return PCIE_SPEED_16_0GT;
280 	case 0x10:
281 		return PCIE_SPEED_32_0GT;
282 	default:
283 		pr_debug("Unexpected PCI link speed property value\n");
284 		return PCI_SPEED_UNKNOWN;
285 	}
286 }
287 
288 int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
289 {
290 	struct device_node *dn, *pdn;
291 	struct pci_bus *bus;
292 	u32 pcie_link_speed_stats[2];
293 	int rc;
294 
295 	bus = bridge->bus;
296 
297 	/* Rely on the pcibios_free_controller_deferred() callback. */
298 	pci_set_host_bridge_release(bridge, pcibios_free_controller_deferred,
299 					(void *) pci_bus_to_host(bus));
300 
301 	dn = pcibios_get_phb_of_node(bus);
302 	if (!dn)
303 		return 0;
304 
305 	for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) {
306 		rc = of_property_read_u32_array(pdn,
307 				"ibm,pcie-link-speed-stats",
308 				&pcie_link_speed_stats[0], 2);
309 		if (!rc)
310 			break;
311 	}
312 
313 	of_node_put(pdn);
314 
315 	if (rc) {
316 		pr_debug("no ibm,pcie-link-speed-stats property\n");
317 		return 0;
318 	}
319 
320 	bus->max_bus_speed = prop_to_pci_speed(pcie_link_speed_stats[0]);
321 	bus->cur_bus_speed = prop_to_pci_speed(pcie_link_speed_stats[1]);
322 	return 0;
323 }
324