1 /* 2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation 3 * 4 * Rewrite, cleanup: 5 * 6 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation 7 * Copyright (C) 2006 Olof Johansson <olof@lixom.net> 8 * 9 * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR. 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 */ 26 27 #include <linux/init.h> 28 #include <linux/types.h> 29 #include <linux/slab.h> 30 #include <linux/mm.h> 31 #include <linux/spinlock.h> 32 #include <linux/string.h> 33 #include <linux/pci.h> 34 #include <linux/dma-mapping.h> 35 #include <asm/io.h> 36 #include <asm/prom.h> 37 #include <asm/rtas.h> 38 #include <asm/iommu.h> 39 #include <asm/pci-bridge.h> 40 #include <asm/machdep.h> 41 #include <asm/abs_addr.h> 42 #include <asm/pSeries_reconfig.h> 43 #include <asm/firmware.h> 44 #include <asm/tce.h> 45 #include <asm/ppc-pci.h> 46 #include <asm/udbg.h> 47 48 #include "plpar_wrappers.h" 49 50 51 static int tce_build_pSeries(struct iommu_table *tbl, long index, 52 long npages, unsigned long uaddr, 53 enum dma_data_direction direction, 54 struct dma_attrs *attrs) 55 { 56 u64 proto_tce; 57 u64 *tcep; 58 u64 rpn; 59 60 proto_tce = TCE_PCI_READ; // Read allowed 61 62 if (direction != DMA_TO_DEVICE) 63 proto_tce |= TCE_PCI_WRITE; 64 65 tcep = ((u64 *)tbl->it_base) + index; 66 67 while (npages--) { 68 /* can't move this out since we might cross LMB boundary */ 69 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; 70 *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; 71 72 uaddr += TCE_PAGE_SIZE; 73 tcep++; 74 } 75 return 0; 76 } 77 78 79 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages) 80 { 81 u64 *tcep; 82 83 tcep = ((u64 *)tbl->it_base) + index; 84 85 while (npages--) 86 *(tcep++) = 0; 87 } 88 89 static unsigned long tce_get_pseries(struct iommu_table *tbl, long index) 90 { 91 u64 *tcep; 92 93 tcep = ((u64 *)tbl->it_base) + index; 94 95 return *tcep; 96 } 97 98 static void tce_free_pSeriesLP(struct iommu_table*, long, long); 99 static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long); 100 101 static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum, 102 long npages, unsigned long uaddr, 103 enum dma_data_direction direction, 104 struct dma_attrs *attrs) 105 { 106 u64 rc = 0; 107 u64 proto_tce, tce; 108 u64 rpn; 109 int ret = 0; 110 long tcenum_start = tcenum, npages_start = npages; 111 112 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; 113 proto_tce = TCE_PCI_READ; 114 if (direction != DMA_TO_DEVICE) 115 proto_tce |= TCE_PCI_WRITE; 116 117 while (npages--) { 118 tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; 119 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce); 120 121 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) { 122 ret = (int)rc; 123 tce_free_pSeriesLP(tbl, tcenum_start, 124 (npages_start - (npages + 1))); 125 break; 126 } 127 128 if (rc && printk_ratelimit()) { 129 printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); 130 printk("\tindex = 0x%lx\n", (u64)tbl->it_index); 131 printk("\ttcenum = 0x%lx\n", (u64)tcenum); 132 printk("\ttce val = 0x%lx\n", tce ); 133 show_stack(current, (unsigned long *)__get_SP()); 134 } 135 136 tcenum++; 137 rpn++; 138 } 139 return ret; 140 } 141 142 static DEFINE_PER_CPU(u64 *, tce_page) = NULL; 143 144 static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, 145 long npages, unsigned long uaddr, 146 enum dma_data_direction direction, 147 struct dma_attrs *attrs) 148 { 149 u64 rc = 0; 150 u64 proto_tce; 151 u64 *tcep; 152 u64 rpn; 153 long l, limit; 154 long tcenum_start = tcenum, npages_start = npages; 155 int ret = 0; 156 157 if (npages == 1) { 158 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, 159 direction, attrs); 160 } 161 162 tcep = __get_cpu_var(tce_page); 163 164 /* This is safe to do since interrupts are off when we're called 165 * from iommu_alloc{,_sg}() 166 */ 167 if (!tcep) { 168 tcep = (u64 *)__get_free_page(GFP_ATOMIC); 169 /* If allocation fails, fall back to the loop implementation */ 170 if (!tcep) { 171 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, 172 direction, attrs); 173 } 174 __get_cpu_var(tce_page) = tcep; 175 } 176 177 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; 178 proto_tce = TCE_PCI_READ; 179 if (direction != DMA_TO_DEVICE) 180 proto_tce |= TCE_PCI_WRITE; 181 182 /* We can map max one pageful of TCEs at a time */ 183 do { 184 /* 185 * Set up the page with TCE data, looping through and setting 186 * the values. 187 */ 188 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE); 189 190 for (l = 0; l < limit; l++) { 191 tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; 192 rpn++; 193 } 194 195 rc = plpar_tce_put_indirect((u64)tbl->it_index, 196 (u64)tcenum << 12, 197 (u64)virt_to_abs(tcep), 198 limit); 199 200 npages -= limit; 201 tcenum += limit; 202 } while (npages > 0 && !rc); 203 204 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) { 205 ret = (int)rc; 206 tce_freemulti_pSeriesLP(tbl, tcenum_start, 207 (npages_start - (npages + limit))); 208 return ret; 209 } 210 211 if (rc && printk_ratelimit()) { 212 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); 213 printk("\tindex = 0x%lx\n", (u64)tbl->it_index); 214 printk("\tnpages = 0x%lx\n", (u64)npages); 215 printk("\ttce[0] val = 0x%lx\n", tcep[0]); 216 show_stack(current, (unsigned long *)__get_SP()); 217 } 218 return ret; 219 } 220 221 static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) 222 { 223 u64 rc; 224 225 while (npages--) { 226 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0); 227 228 if (rc && printk_ratelimit()) { 229 printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); 230 printk("\tindex = 0x%lx\n", (u64)tbl->it_index); 231 printk("\ttcenum = 0x%lx\n", (u64)tcenum); 232 show_stack(current, (unsigned long *)__get_SP()); 233 } 234 235 tcenum++; 236 } 237 } 238 239 240 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) 241 { 242 u64 rc; 243 244 rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages); 245 246 if (rc && printk_ratelimit()) { 247 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n"); 248 printk("\trc = %ld\n", rc); 249 printk("\tindex = 0x%lx\n", (u64)tbl->it_index); 250 printk("\tnpages = 0x%lx\n", (u64)npages); 251 show_stack(current, (unsigned long *)__get_SP()); 252 } 253 } 254 255 static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum) 256 { 257 u64 rc; 258 unsigned long tce_ret; 259 260 rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret); 261 262 if (rc && printk_ratelimit()) { 263 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%ld\n", 264 rc); 265 printk("\tindex = 0x%lx\n", (u64)tbl->it_index); 266 printk("\ttcenum = 0x%lx\n", (u64)tcenum); 267 show_stack(current, (unsigned long *)__get_SP()); 268 } 269 270 return tce_ret; 271 } 272 273 #ifdef CONFIG_PCI 274 static void iommu_table_setparms(struct pci_controller *phb, 275 struct device_node *dn, 276 struct iommu_table *tbl) 277 { 278 struct device_node *node; 279 const unsigned long *basep; 280 const u32 *sizep; 281 282 node = phb->dn; 283 284 basep = of_get_property(node, "linux,tce-base", NULL); 285 sizep = of_get_property(node, "linux,tce-size", NULL); 286 if (basep == NULL || sizep == NULL) { 287 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has " 288 "missing tce entries !\n", dn->full_name); 289 return; 290 } 291 292 tbl->it_base = (unsigned long)__va(*basep); 293 294 #ifndef CONFIG_CRASH_DUMP 295 memset((void *)tbl->it_base, 0, *sizep); 296 #endif 297 298 tbl->it_busno = phb->bus->number; 299 300 /* Units of tce entries */ 301 tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT; 302 303 /* Test if we are going over 2GB of DMA space */ 304 if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) { 305 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); 306 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); 307 } 308 309 phb->dma_window_base_cur += phb->dma_window_size; 310 311 /* Set the tce table size - measured in entries */ 312 tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT; 313 314 tbl->it_index = 0; 315 tbl->it_blocksize = 16; 316 tbl->it_type = TCE_PCI; 317 } 318 319 /* 320 * iommu_table_setparms_lpar 321 * 322 * Function: On pSeries LPAR systems, return TCE table info, given a pci bus. 323 */ 324 static void iommu_table_setparms_lpar(struct pci_controller *phb, 325 struct device_node *dn, 326 struct iommu_table *tbl, 327 const void *dma_window, 328 int bussubno) 329 { 330 unsigned long offset, size; 331 332 tbl->it_busno = bussubno; 333 of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size); 334 335 tbl->it_base = 0; 336 tbl->it_blocksize = 16; 337 tbl->it_type = TCE_PCI; 338 tbl->it_offset = offset >> IOMMU_PAGE_SHIFT; 339 tbl->it_size = size >> IOMMU_PAGE_SHIFT; 340 } 341 342 static void pci_dma_bus_setup_pSeries(struct pci_bus *bus) 343 { 344 struct device_node *dn; 345 struct iommu_table *tbl; 346 struct device_node *isa_dn, *isa_dn_orig; 347 struct device_node *tmp; 348 struct pci_dn *pci; 349 int children; 350 351 dn = pci_bus_to_OF_node(bus); 352 353 pr_debug("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name); 354 355 if (bus->self) { 356 /* This is not a root bus, any setup will be done for the 357 * device-side of the bridge in iommu_dev_setup_pSeries(). 358 */ 359 return; 360 } 361 pci = PCI_DN(dn); 362 363 /* Check if the ISA bus on the system is under 364 * this PHB. 365 */ 366 isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa"); 367 368 while (isa_dn && isa_dn != dn) 369 isa_dn = isa_dn->parent; 370 371 if (isa_dn_orig) 372 of_node_put(isa_dn_orig); 373 374 /* Count number of direct PCI children of the PHB. */ 375 for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling) 376 children++; 377 378 pr_debug("Children: %d\n", children); 379 380 /* Calculate amount of DMA window per slot. Each window must be 381 * a power of two (due to pci_alloc_consistent requirements). 382 * 383 * Keep 256MB aside for PHBs with ISA. 384 */ 385 386 if (!isa_dn) { 387 /* No ISA/IDE - just set window size and return */ 388 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */ 389 390 while (pci->phb->dma_window_size * children > 0x80000000ul) 391 pci->phb->dma_window_size >>= 1; 392 pr_debug("No ISA/IDE, window size is 0x%lx\n", 393 pci->phb->dma_window_size); 394 pci->phb->dma_window_base_cur = 0; 395 396 return; 397 } 398 399 /* If we have ISA, then we probably have an IDE 400 * controller too. Allocate a 128MB table but 401 * skip the first 128MB to avoid stepping on ISA 402 * space. 403 */ 404 pci->phb->dma_window_size = 0x8000000ul; 405 pci->phb->dma_window_base_cur = 0x8000000ul; 406 407 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, 408 pci->phb->node); 409 410 iommu_table_setparms(pci->phb, dn, tbl); 411 pci->iommu_table = iommu_init_table(tbl, pci->phb->node); 412 413 /* Divide the rest (1.75GB) among the children */ 414 pci->phb->dma_window_size = 0x80000000ul; 415 while (pci->phb->dma_window_size * children > 0x70000000ul) 416 pci->phb->dma_window_size >>= 1; 417 418 pr_debug("ISA/IDE, window size is 0x%lx\n", pci->phb->dma_window_size); 419 } 420 421 422 static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus) 423 { 424 struct iommu_table *tbl; 425 struct device_node *dn, *pdn; 426 struct pci_dn *ppci; 427 const void *dma_window = NULL; 428 429 dn = pci_bus_to_OF_node(bus); 430 431 pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n", 432 dn->full_name); 433 434 /* Find nearest ibm,dma-window, walking up the device tree */ 435 for (pdn = dn; pdn != NULL; pdn = pdn->parent) { 436 dma_window = of_get_property(pdn, "ibm,dma-window", NULL); 437 if (dma_window != NULL) 438 break; 439 } 440 441 if (dma_window == NULL) { 442 pr_debug(" no ibm,dma-window property !\n"); 443 return; 444 } 445 446 ppci = PCI_DN(pdn); 447 448 pr_debug(" parent is %s, iommu_table: 0x%p\n", 449 pdn->full_name, ppci->iommu_table); 450 451 if (!ppci->iommu_table) { 452 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, 453 ppci->phb->node); 454 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window, 455 bus->number); 456 ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node); 457 pr_debug(" created table: %p\n", ppci->iommu_table); 458 } 459 460 if (pdn != dn) 461 PCI_DN(dn)->iommu_table = ppci->iommu_table; 462 } 463 464 465 static void pci_dma_dev_setup_pSeries(struct pci_dev *dev) 466 { 467 struct device_node *dn; 468 struct iommu_table *tbl; 469 470 pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev)); 471 472 dn = dev->dev.archdata.of_node; 473 474 /* If we're the direct child of a root bus, then we need to allocate 475 * an iommu table ourselves. The bus setup code should have setup 476 * the window sizes already. 477 */ 478 if (!dev->bus->self) { 479 struct pci_controller *phb = PCI_DN(dn)->phb; 480 481 pr_debug(" --> first child, no bridge. Allocating iommu table.\n"); 482 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, 483 phb->node); 484 iommu_table_setparms(phb, dn, tbl); 485 PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node); 486 dev->dev.archdata.dma_data = PCI_DN(dn)->iommu_table; 487 return; 488 } 489 490 /* If this device is further down the bus tree, search upwards until 491 * an already allocated iommu table is found and use that. 492 */ 493 494 while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL) 495 dn = dn->parent; 496 497 if (dn && PCI_DN(dn)) 498 dev->dev.archdata.dma_data = PCI_DN(dn)->iommu_table; 499 else 500 printk(KERN_WARNING "iommu: Device %s has no iommu table\n", 501 pci_name(dev)); 502 } 503 504 static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev) 505 { 506 struct device_node *pdn, *dn; 507 struct iommu_table *tbl; 508 const void *dma_window = NULL; 509 struct pci_dn *pci; 510 511 pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev)); 512 513 /* dev setup for LPAR is a little tricky, since the device tree might 514 * contain the dma-window properties per-device and not neccesarily 515 * for the bus. So we need to search upwards in the tree until we 516 * either hit a dma-window property, OR find a parent with a table 517 * already allocated. 518 */ 519 dn = pci_device_to_OF_node(dev); 520 pr_debug(" node is %s\n", dn->full_name); 521 522 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table; 523 pdn = pdn->parent) { 524 dma_window = of_get_property(pdn, "ibm,dma-window", NULL); 525 if (dma_window) 526 break; 527 } 528 529 if (!pdn || !PCI_DN(pdn)) { 530 printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: " 531 "no DMA window found for pci dev=%s dn=%s\n", 532 pci_name(dev), dn? dn->full_name : "<null>"); 533 return; 534 } 535 pr_debug(" parent is %s\n", pdn->full_name); 536 537 /* Check for parent == NULL so we don't try to setup the empty EADS 538 * slots on POWER4 machines. 539 */ 540 if (dma_window == NULL || pdn->parent == NULL) { 541 pr_debug(" no dma window for device, linking to parent\n"); 542 dev->dev.archdata.dma_data = PCI_DN(pdn)->iommu_table; 543 return; 544 } 545 546 pci = PCI_DN(pdn); 547 if (!pci->iommu_table) { 548 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, 549 pci->phb->node); 550 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window, 551 pci->phb->bus->number); 552 pci->iommu_table = iommu_init_table(tbl, pci->phb->node); 553 pr_debug(" created table: %p\n", pci->iommu_table); 554 } else { 555 pr_debug(" found DMA window, table: %p\n", pci->iommu_table); 556 } 557 558 dev->dev.archdata.dma_data = pci->iommu_table; 559 } 560 #else /* CONFIG_PCI */ 561 #define pci_dma_bus_setup_pSeries NULL 562 #define pci_dma_dev_setup_pSeries NULL 563 #define pci_dma_bus_setup_pSeriesLP NULL 564 #define pci_dma_dev_setup_pSeriesLP NULL 565 #endif /* !CONFIG_PCI */ 566 567 static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node) 568 { 569 int err = NOTIFY_OK; 570 struct device_node *np = node; 571 struct pci_dn *pci = PCI_DN(np); 572 573 switch (action) { 574 case PSERIES_RECONFIG_REMOVE: 575 if (pci && pci->iommu_table && 576 of_get_property(np, "ibm,dma-window", NULL)) 577 iommu_free_table(pci->iommu_table, np->full_name); 578 break; 579 default: 580 err = NOTIFY_DONE; 581 break; 582 } 583 return err; 584 } 585 586 static struct notifier_block iommu_reconfig_nb = { 587 .notifier_call = iommu_reconfig_notifier, 588 }; 589 590 /* These are called very early. */ 591 void iommu_init_early_pSeries(void) 592 { 593 if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL)) { 594 /* Direct I/O, IOMMU off */ 595 ppc_md.pci_dma_dev_setup = NULL; 596 ppc_md.pci_dma_bus_setup = NULL; 597 set_pci_dma_ops(&dma_direct_ops); 598 return; 599 } 600 601 if (firmware_has_feature(FW_FEATURE_LPAR)) { 602 if (firmware_has_feature(FW_FEATURE_MULTITCE)) { 603 ppc_md.tce_build = tce_buildmulti_pSeriesLP; 604 ppc_md.tce_free = tce_freemulti_pSeriesLP; 605 } else { 606 ppc_md.tce_build = tce_build_pSeriesLP; 607 ppc_md.tce_free = tce_free_pSeriesLP; 608 } 609 ppc_md.tce_get = tce_get_pSeriesLP; 610 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP; 611 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP; 612 } else { 613 ppc_md.tce_build = tce_build_pSeries; 614 ppc_md.tce_free = tce_free_pSeries; 615 ppc_md.tce_get = tce_get_pseries; 616 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeries; 617 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeries; 618 } 619 620 621 pSeries_reconfig_notifier_register(&iommu_reconfig_nb); 622 623 set_pci_dma_ops(&dma_iommu_ops); 624 } 625 626