1 /* 2 * PS3 Platform spu routines. 3 * 4 * Copyright (C) 2006 Sony Computer Entertainment Inc. 5 * Copyright 2006 Sony Corp. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 */ 20 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/mmzone.h> 24 #include <linux/io.h> 25 #include <linux/mm.h> 26 27 #include <asm/spu.h> 28 #include <asm/spu_priv1.h> 29 #include <asm/lv1call.h> 30 #include <asm/ps3.h> 31 32 #include "../cell/spufs/spufs.h" 33 #include "platform.h" 34 35 /* spu_management_ops */ 36 37 /** 38 * enum spe_type - Type of spe to create. 39 * @spe_type_logical: Standard logical spe. 40 * 41 * For use with lv1_construct_logical_spe(). The current HV does not support 42 * any types other than those listed. 43 */ 44 45 enum spe_type { 46 SPE_TYPE_LOGICAL = 0, 47 }; 48 49 /** 50 * struct spe_shadow - logical spe shadow register area. 51 * 52 * Read-only shadow of spe registers. 53 */ 54 55 struct spe_shadow { 56 u8 padding_0140[0x0140]; 57 u64 int_status_class0_RW; /* 0x0140 */ 58 u64 int_status_class1_RW; /* 0x0148 */ 59 u64 int_status_class2_RW; /* 0x0150 */ 60 u8 padding_0158[0x0610-0x0158]; 61 u64 mfc_dsisr_RW; /* 0x0610 */ 62 u8 padding_0618[0x0620-0x0618]; 63 u64 mfc_dar_RW; /* 0x0620 */ 64 u8 padding_0628[0x0800-0x0628]; 65 u64 mfc_dsipr_R; /* 0x0800 */ 66 u8 padding_0808[0x0810-0x0808]; 67 u64 mfc_lscrr_R; /* 0x0810 */ 68 u8 padding_0818[0x0c00-0x0818]; 69 u64 mfc_cer_R; /* 0x0c00 */ 70 u8 padding_0c08[0x0f00-0x0c08]; 71 u64 spe_execution_status; /* 0x0f00 */ 72 u8 padding_0f08[0x1000-0x0f08]; 73 }; 74 75 /** 76 * enum spe_ex_state - Logical spe execution state. 77 * @spe_ex_state_unexecutable: Uninitialized. 78 * @spe_ex_state_executable: Enabled, not ready. 79 * @spe_ex_state_executed: Ready for use. 80 * 81 * The execution state (status) of the logical spe as reported in 82 * struct spe_shadow:spe_execution_status. 83 */ 84 85 enum spe_ex_state { 86 SPE_EX_STATE_UNEXECUTABLE = 0, 87 SPE_EX_STATE_EXECUTABLE = 2, 88 SPE_EX_STATE_EXECUTED = 3, 89 }; 90 91 /** 92 * struct priv1_cache - Cached values of priv1 registers. 93 * @masks[]: Array of cached spe interrupt masks, indexed by class. 94 * @sr1: Cached mfc_sr1 register. 95 * @tclass_id: Cached mfc_tclass_id register. 96 */ 97 98 struct priv1_cache { 99 u64 masks[3]; 100 u64 sr1; 101 u64 tclass_id; 102 }; 103 104 /** 105 * struct spu_pdata - Platform state variables. 106 * @spe_id: HV spe id returned by lv1_construct_logical_spe(). 107 * @resource_id: HV spe resource id returned by 108 * ps3_repository_read_spe_resource_id(). 109 * @priv2_addr: lpar address of spe priv2 area returned by 110 * lv1_construct_logical_spe(). 111 * @shadow_addr: lpar address of spe register shadow area returned by 112 * lv1_construct_logical_spe(). 113 * @shadow: Virtual (ioremap) address of spe register shadow area. 114 * @cache: Cached values of priv1 registers. 115 */ 116 117 struct spu_pdata { 118 u64 spe_id; 119 u64 resource_id; 120 u64 priv2_addr; 121 u64 shadow_addr; 122 struct spe_shadow __iomem *shadow; 123 struct priv1_cache cache; 124 }; 125 126 static struct spu_pdata *spu_pdata(struct spu *spu) 127 { 128 return spu->pdata; 129 } 130 131 #define dump_areas(_a, _b, _c, _d, _e) \ 132 _dump_areas(_a, _b, _c, _d, _e, __func__, __LINE__) 133 static void _dump_areas(unsigned int spe_id, unsigned long priv2, 134 unsigned long problem, unsigned long ls, unsigned long shadow, 135 const char* func, int line) 136 { 137 pr_debug("%s:%d: spe_id: %xh (%u)\n", func, line, spe_id, spe_id); 138 pr_debug("%s:%d: priv2: %lxh\n", func, line, priv2); 139 pr_debug("%s:%d: problem: %lxh\n", func, line, problem); 140 pr_debug("%s:%d: ls: %lxh\n", func, line, ls); 141 pr_debug("%s:%d: shadow: %lxh\n", func, line, shadow); 142 } 143 144 inline u64 ps3_get_spe_id(void *arg) 145 { 146 return spu_pdata(arg)->spe_id; 147 } 148 EXPORT_SYMBOL_GPL(ps3_get_spe_id); 149 150 static unsigned long get_vas_id(void) 151 { 152 unsigned long id; 153 154 lv1_get_logical_ppe_id(&id); 155 lv1_get_virtual_address_space_id_of_ppe(id, &id); 156 157 return id; 158 } 159 160 static int __init construct_spu(struct spu *spu) 161 { 162 int result; 163 unsigned long unused; 164 165 result = lv1_construct_logical_spe(PAGE_SHIFT, PAGE_SHIFT, PAGE_SHIFT, 166 PAGE_SHIFT, PAGE_SHIFT, get_vas_id(), SPE_TYPE_LOGICAL, 167 &spu_pdata(spu)->priv2_addr, &spu->problem_phys, 168 &spu->local_store_phys, &unused, 169 &spu_pdata(spu)->shadow_addr, 170 &spu_pdata(spu)->spe_id); 171 172 if (result) { 173 pr_debug("%s:%d: lv1_construct_logical_spe failed: %s\n", 174 __func__, __LINE__, ps3_result(result)); 175 return result; 176 } 177 178 return result; 179 } 180 181 static void spu_unmap(struct spu *spu) 182 { 183 iounmap(spu->priv2); 184 iounmap(spu->problem); 185 iounmap((__force u8 __iomem *)spu->local_store); 186 iounmap(spu_pdata(spu)->shadow); 187 } 188 189 static int __init setup_areas(struct spu *spu) 190 { 191 struct table {char* name; unsigned long addr; unsigned long size;}; 192 193 spu_pdata(spu)->shadow = ioremap_flags(spu_pdata(spu)->shadow_addr, 194 sizeof(struct spe_shadow), 195 pgprot_val(PAGE_READONLY) | 196 _PAGE_NO_CACHE); 197 if (!spu_pdata(spu)->shadow) { 198 pr_debug("%s:%d: ioremap shadow failed\n", __func__, __LINE__); 199 goto fail_ioremap; 200 } 201 202 spu->local_store = (__force void *)ioremap_flags(spu->local_store_phys, 203 LS_SIZE, _PAGE_NO_CACHE); 204 205 if (!spu->local_store) { 206 pr_debug("%s:%d: ioremap local_store failed\n", 207 __func__, __LINE__); 208 goto fail_ioremap; 209 } 210 211 spu->problem = ioremap(spu->problem_phys, 212 sizeof(struct spu_problem)); 213 214 if (!spu->problem) { 215 pr_debug("%s:%d: ioremap problem failed\n", __func__, __LINE__); 216 goto fail_ioremap; 217 } 218 219 spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr, 220 sizeof(struct spu_priv2)); 221 222 if (!spu->priv2) { 223 pr_debug("%s:%d: ioremap priv2 failed\n", __func__, __LINE__); 224 goto fail_ioremap; 225 } 226 227 dump_areas(spu_pdata(spu)->spe_id, spu_pdata(spu)->priv2_addr, 228 spu->problem_phys, spu->local_store_phys, 229 spu_pdata(spu)->shadow_addr); 230 dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2, 231 (unsigned long)spu->problem, (unsigned long)spu->local_store, 232 (unsigned long)spu_pdata(spu)->shadow); 233 234 return 0; 235 236 fail_ioremap: 237 spu_unmap(spu); 238 239 return -ENOMEM; 240 } 241 242 static int __init setup_interrupts(struct spu *spu) 243 { 244 int result; 245 246 result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id, 247 0, &spu->irqs[0]); 248 249 if (result) 250 goto fail_alloc_0; 251 252 result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id, 253 1, &spu->irqs[1]); 254 255 if (result) 256 goto fail_alloc_1; 257 258 result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id, 259 2, &spu->irqs[2]); 260 261 if (result) 262 goto fail_alloc_2; 263 264 return result; 265 266 fail_alloc_2: 267 ps3_spe_irq_destroy(spu->irqs[1]); 268 fail_alloc_1: 269 ps3_spe_irq_destroy(spu->irqs[0]); 270 fail_alloc_0: 271 spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ; 272 return result; 273 } 274 275 static int __init enable_spu(struct spu *spu) 276 { 277 int result; 278 279 result = lv1_enable_logical_spe(spu_pdata(spu)->spe_id, 280 spu_pdata(spu)->resource_id); 281 282 if (result) { 283 pr_debug("%s:%d: lv1_enable_logical_spe failed: %s\n", 284 __func__, __LINE__, ps3_result(result)); 285 goto fail_enable; 286 } 287 288 result = setup_areas(spu); 289 290 if (result) 291 goto fail_areas; 292 293 result = setup_interrupts(spu); 294 295 if (result) 296 goto fail_interrupts; 297 298 return 0; 299 300 fail_interrupts: 301 spu_unmap(spu); 302 fail_areas: 303 lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0); 304 fail_enable: 305 return result; 306 } 307 308 static int ps3_destroy_spu(struct spu *spu) 309 { 310 int result; 311 312 pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number); 313 314 result = lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0); 315 BUG_ON(result); 316 317 ps3_spe_irq_destroy(spu->irqs[2]); 318 ps3_spe_irq_destroy(spu->irqs[1]); 319 ps3_spe_irq_destroy(spu->irqs[0]); 320 321 spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ; 322 323 spu_unmap(spu); 324 325 result = lv1_destruct_logical_spe(spu_pdata(spu)->spe_id); 326 BUG_ON(result); 327 328 kfree(spu->pdata); 329 spu->pdata = NULL; 330 331 return 0; 332 } 333 334 static int __init ps3_create_spu(struct spu *spu, void *data) 335 { 336 int result; 337 338 pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number); 339 340 spu->pdata = kzalloc(sizeof(struct spu_pdata), 341 GFP_KERNEL); 342 343 if (!spu->pdata) { 344 result = -ENOMEM; 345 goto fail_malloc; 346 } 347 348 spu_pdata(spu)->resource_id = (unsigned long)data; 349 350 /* Init cached reg values to HV defaults. */ 351 352 spu_pdata(spu)->cache.sr1 = 0x33; 353 354 result = construct_spu(spu); 355 356 if (result) 357 goto fail_construct; 358 359 /* For now, just go ahead and enable it. */ 360 361 result = enable_spu(spu); 362 363 if (result) 364 goto fail_enable; 365 366 /* Make sure the spu is in SPE_EX_STATE_EXECUTED. */ 367 368 /* need something better here!!! */ 369 while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status) 370 != SPE_EX_STATE_EXECUTED) 371 (void)0; 372 373 return result; 374 375 fail_enable: 376 fail_construct: 377 ps3_destroy_spu(spu); 378 fail_malloc: 379 return result; 380 } 381 382 static int __init ps3_enumerate_spus(int (*fn)(void *data)) 383 { 384 int result; 385 unsigned int num_resource_id; 386 unsigned int i; 387 388 result = ps3_repository_read_num_spu_resource_id(&num_resource_id); 389 390 pr_debug("%s:%d: num_resource_id %u\n", __func__, __LINE__, 391 num_resource_id); 392 393 /* 394 * For now, just create logical spus equal to the number 395 * of physical spus reserved for the partition. 396 */ 397 398 for (i = 0; i < num_resource_id; i++) { 399 enum ps3_spu_resource_type resource_type; 400 unsigned int resource_id; 401 402 result = ps3_repository_read_spu_resource_id(i, 403 &resource_type, &resource_id); 404 405 if (result) 406 break; 407 408 if (resource_type == PS3_SPU_RESOURCE_TYPE_EXCLUSIVE) { 409 result = fn((void*)(unsigned long)resource_id); 410 411 if (result) 412 break; 413 } 414 } 415 416 if (result) { 417 printk(KERN_WARNING "%s:%d: Error initializing spus\n", 418 __func__, __LINE__); 419 return result; 420 } 421 422 return num_resource_id; 423 } 424 425 static int ps3_init_affinity(void) 426 { 427 return 0; 428 } 429 430 /** 431 * ps3_enable_spu - Enable SPU run control. 432 * 433 * An outstanding enhancement for the PS3 would be to add a guard to check 434 * for incorrect access to the spu problem state when the spu context is 435 * disabled. This check could be implemented with a flag added to the spu 436 * context that would inhibit mapping problem state pages, and a routine 437 * to unmap spu problem state pages. When the spu is enabled with 438 * ps3_enable_spu() the flag would be set allowing pages to be mapped, 439 * and when the spu is disabled with ps3_disable_spu() the flag would be 440 * cleared and the mapped problem state pages would be unmapped. 441 */ 442 443 static void ps3_enable_spu(struct spu_context *ctx) 444 { 445 } 446 447 static void ps3_disable_spu(struct spu_context *ctx) 448 { 449 ctx->ops->runcntl_stop(ctx); 450 } 451 452 const struct spu_management_ops spu_management_ps3_ops = { 453 .enumerate_spus = ps3_enumerate_spus, 454 .create_spu = ps3_create_spu, 455 .destroy_spu = ps3_destroy_spu, 456 .enable_spu = ps3_enable_spu, 457 .disable_spu = ps3_disable_spu, 458 .init_affinity = ps3_init_affinity, 459 }; 460 461 /* spu_priv1_ops */ 462 463 static void int_mask_and(struct spu *spu, int class, u64 mask) 464 { 465 u64 old_mask; 466 467 /* are these serialized by caller??? */ 468 old_mask = spu_int_mask_get(spu, class); 469 spu_int_mask_set(spu, class, old_mask & mask); 470 } 471 472 static void int_mask_or(struct spu *spu, int class, u64 mask) 473 { 474 u64 old_mask; 475 476 old_mask = spu_int_mask_get(spu, class); 477 spu_int_mask_set(spu, class, old_mask | mask); 478 } 479 480 static void int_mask_set(struct spu *spu, int class, u64 mask) 481 { 482 spu_pdata(spu)->cache.masks[class] = mask; 483 lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class, 484 spu_pdata(spu)->cache.masks[class]); 485 } 486 487 static u64 int_mask_get(struct spu *spu, int class) 488 { 489 return spu_pdata(spu)->cache.masks[class]; 490 } 491 492 static void int_stat_clear(struct spu *spu, int class, u64 stat) 493 { 494 /* Note that MFC_DSISR will be cleared when class1[MF] is set. */ 495 496 lv1_clear_spe_interrupt_status(spu_pdata(spu)->spe_id, class, 497 stat, 0); 498 } 499 500 static u64 int_stat_get(struct spu *spu, int class) 501 { 502 u64 stat; 503 504 lv1_get_spe_interrupt_status(spu_pdata(spu)->spe_id, class, &stat); 505 return stat; 506 } 507 508 static void cpu_affinity_set(struct spu *spu, int cpu) 509 { 510 /* No support. */ 511 } 512 513 static u64 mfc_dar_get(struct spu *spu) 514 { 515 return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW); 516 } 517 518 static void mfc_dsisr_set(struct spu *spu, u64 dsisr) 519 { 520 /* Nothing to do, cleared in int_stat_clear(). */ 521 } 522 523 static u64 mfc_dsisr_get(struct spu *spu) 524 { 525 return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW); 526 } 527 528 static void mfc_sdr_setup(struct spu *spu) 529 { 530 /* Nothing to do. */ 531 } 532 533 static void mfc_sr1_set(struct spu *spu, u64 sr1) 534 { 535 /* Check bits allowed by HV. */ 536 537 static const u64 allowed = ~(MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 538 | MFC_STATE1_PROBLEM_STATE_MASK); 539 540 BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed)); 541 542 spu_pdata(spu)->cache.sr1 = sr1; 543 lv1_set_spe_privilege_state_area_1_register( 544 spu_pdata(spu)->spe_id, 545 offsetof(struct spu_priv1, mfc_sr1_RW), 546 spu_pdata(spu)->cache.sr1); 547 } 548 549 static u64 mfc_sr1_get(struct spu *spu) 550 { 551 return spu_pdata(spu)->cache.sr1; 552 } 553 554 static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id) 555 { 556 spu_pdata(spu)->cache.tclass_id = tclass_id; 557 lv1_set_spe_privilege_state_area_1_register( 558 spu_pdata(spu)->spe_id, 559 offsetof(struct spu_priv1, mfc_tclass_id_RW), 560 spu_pdata(spu)->cache.tclass_id); 561 } 562 563 static u64 mfc_tclass_id_get(struct spu *spu) 564 { 565 return spu_pdata(spu)->cache.tclass_id; 566 } 567 568 static void tlb_invalidate(struct spu *spu) 569 { 570 /* Nothing to do. */ 571 } 572 573 static void resource_allocation_groupID_set(struct spu *spu, u64 id) 574 { 575 /* No support. */ 576 } 577 578 static u64 resource_allocation_groupID_get(struct spu *spu) 579 { 580 return 0; /* No support. */ 581 } 582 583 static void resource_allocation_enable_set(struct spu *spu, u64 enable) 584 { 585 /* No support. */ 586 } 587 588 static u64 resource_allocation_enable_get(struct spu *spu) 589 { 590 return 0; /* No support. */ 591 } 592 593 const struct spu_priv1_ops spu_priv1_ps3_ops = { 594 .int_mask_and = int_mask_and, 595 .int_mask_or = int_mask_or, 596 .int_mask_set = int_mask_set, 597 .int_mask_get = int_mask_get, 598 .int_stat_clear = int_stat_clear, 599 .int_stat_get = int_stat_get, 600 .cpu_affinity_set = cpu_affinity_set, 601 .mfc_dar_get = mfc_dar_get, 602 .mfc_dsisr_set = mfc_dsisr_set, 603 .mfc_dsisr_get = mfc_dsisr_get, 604 .mfc_sdr_setup = mfc_sdr_setup, 605 .mfc_sr1_set = mfc_sr1_set, 606 .mfc_sr1_get = mfc_sr1_get, 607 .mfc_tclass_id_set = mfc_tclass_id_set, 608 .mfc_tclass_id_get = mfc_tclass_id_get, 609 .tlb_invalidate = tlb_invalidate, 610 .resource_allocation_groupID_set = resource_allocation_groupID_set, 611 .resource_allocation_groupID_get = resource_allocation_groupID_get, 612 .resource_allocation_enable_set = resource_allocation_enable_set, 613 .resource_allocation_enable_get = resource_allocation_enable_get, 614 }; 615 616 void ps3_spu_set_platform(void) 617 { 618 spu_priv1_ops = &spu_priv1_ps3_ops; 619 spu_management_ops = &spu_management_ps3_ops; 620 } 621