1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright 2016-17 IBM Corp. 4 */ 5 6 #ifndef _VAS_H 7 #define _VAS_H 8 #include <linux/atomic.h> 9 #include <linux/idr.h> 10 #include <asm/vas.h> 11 #include <linux/io.h> 12 #include <linux/dcache.h> 13 #include <linux/mutex.h> 14 #include <linux/stringify.h> 15 16 /* 17 * Overview of Virtual Accelerator Switchboard (VAS). 18 * 19 * VAS is a hardware "switchboard" that allows senders and receivers to 20 * exchange messages with _minimal_ kernel involvment. The receivers are 21 * typically NX coprocessor engines that perform compression or encryption 22 * in hardware, but receivers can also be other software threads. 23 * 24 * Senders are user/kernel threads that submit compression/encryption or 25 * other requests to the receivers. Senders must format their messages as 26 * Coprocessor Request Blocks (CRB)s and submit them using the "copy" and 27 * "paste" instructions which were introduced in Power9. 28 * 29 * A Power node can have (upto?) 8 Power chips. There is one instance of 30 * VAS in each Power9 chip. Each instance of VAS has 64K windows or ports, 31 * Senders and receivers must each connect to a separate window before they 32 * can exchange messages through the switchboard. 33 * 34 * Each window is described by two types of window contexts: 35 * 36 * Hypervisor Window Context (HVWC) of size VAS_HVWC_SIZE bytes 37 * 38 * OS/User Window Context (UWC) of size VAS_UWC_SIZE bytes. 39 * 40 * A window context can be viewed as a set of 64-bit registers. The settings 41 * in these registers configure/control/determine the behavior of the VAS 42 * hardware when messages are sent/received through the window. The registers 43 * in the HVWC are configured by the kernel while the registers in the UWC can 44 * be configured by the kernel or by the user space application that is using 45 * the window. 46 * 47 * The HVWCs for all windows on a specific instance of VAS are in a contiguous 48 * range of hardware addresses or Base address region (BAR) referred to as the 49 * HVWC BAR for the instance. Similarly the UWCs for all windows on an instance 50 * are referred to as the UWC BAR for the instance. 51 * 52 * The two BARs for each instance are defined Power9 MMIO Ranges spreadsheet 53 * and available to the kernel in the VAS node's "reg" property in the device 54 * tree: 55 * 56 * /proc/device-tree/vasm@.../reg 57 * 58 * (see vas_probe() for details on the reg property). 59 * 60 * The kernel maps the HVWC and UWC BAR regions into the kernel address 61 * space (hvwc_map and uwc_map). The kernel can then access the window 62 * contexts of a specific window using: 63 * 64 * hvwc = hvwc_map + winid * VAS_HVWC_SIZE. 65 * uwc = uwc_map + winid * VAS_UWC_SIZE. 66 * 67 * where winid is the window index (0..64K). 68 * 69 * As mentioned, a window context is used to "configure" a window. Besides 70 * this configuration address, each _send_ window also has a unique hardware 71 * "paste" address that is used to submit requests/CRBs (see vas_paste_crb()). 72 * 73 * The hardware paste address for a window is computed using the "paste 74 * base address" and "paste win id shift" reg properties in the VAS device 75 * tree node using: 76 * 77 * paste_addr = paste_base + ((winid << paste_win_id_shift)) 78 * 79 * (again, see vas_probe() for ->paste_base_addr and ->paste_win_id_shift). 80 * 81 * The kernel maps this hardware address into the sender's address space 82 * after which they can use the 'paste' instruction (new in Power9) to 83 * send a message (submit a request aka CRB) to the coprocessor. 84 * 85 * NOTE: In the initial version, senders can only in-kernel drivers/threads. 86 * Support for user space threads will be added in follow-on patches. 87 * 88 * TODO: Do we need to map the UWC into user address space so they can return 89 * credits? Its NA for NX but may be needed for other receive windows. 90 * 91 */ 92 93 #define VAS_WINDOWS_PER_CHIP (64 << 10) 94 95 /* 96 * Hypervisor and OS/USer Window Context sizes 97 */ 98 #define VAS_HVWC_SIZE 512 99 #define VAS_UWC_SIZE PAGE_SIZE 100 101 /* 102 * Initial per-process credits. 103 * Max send window credits: 4K-1 (12-bits in VAS_TX_WCRED) 104 * Max receive window credits: 64K-1 (16 bits in VAS_LRX_WCRED) 105 * 106 * TODO: Needs tuning for per-process credits 107 */ 108 #define VAS_RX_WCREDS_MAX ((64 << 10) - 1) 109 #define VAS_TX_WCREDS_MAX ((4 << 10) - 1) 110 #define VAS_WCREDS_DEFAULT (1 << 10) 111 112 /* 113 * VAS Window Context Register Offsets and bitmasks. 114 * See Section 3.1.4 of VAS Work book 115 */ 116 #define VAS_LPID_OFFSET 0x010 117 #define VAS_LPID PPC_BITMASK(0, 11) 118 119 #define VAS_PID_OFFSET 0x018 120 #define VAS_PID_ID PPC_BITMASK(0, 19) 121 122 #define VAS_XLATE_MSR_OFFSET 0x020 123 #define VAS_XLATE_MSR_DR PPC_BIT(0) 124 #define VAS_XLATE_MSR_TA PPC_BIT(1) 125 #define VAS_XLATE_MSR_PR PPC_BIT(2) 126 #define VAS_XLATE_MSR_US PPC_BIT(3) 127 #define VAS_XLATE_MSR_HV PPC_BIT(4) 128 #define VAS_XLATE_MSR_SF PPC_BIT(5) 129 130 #define VAS_XLATE_LPCR_OFFSET 0x028 131 #define VAS_XLATE_LPCR_PAGE_SIZE PPC_BITMASK(0, 2) 132 #define VAS_XLATE_LPCR_ISL PPC_BIT(3) 133 #define VAS_XLATE_LPCR_TC PPC_BIT(4) 134 #define VAS_XLATE_LPCR_SC PPC_BIT(5) 135 136 #define VAS_XLATE_CTL_OFFSET 0x030 137 #define VAS_XLATE_MODE PPC_BITMASK(0, 1) 138 139 #define VAS_AMR_OFFSET 0x040 140 #define VAS_AMR PPC_BITMASK(0, 63) 141 142 #define VAS_SEIDR_OFFSET 0x048 143 #define VAS_SEIDR PPC_BITMASK(0, 63) 144 145 #define VAS_FAULT_TX_WIN_OFFSET 0x050 146 #define VAS_FAULT_TX_WIN PPC_BITMASK(48, 63) 147 148 #define VAS_OSU_INTR_SRC_RA_OFFSET 0x060 149 #define VAS_OSU_INTR_SRC_RA PPC_BITMASK(8, 63) 150 151 #define VAS_HV_INTR_SRC_RA_OFFSET 0x070 152 #define VAS_HV_INTR_SRC_RA PPC_BITMASK(8, 63) 153 154 #define VAS_PSWID_OFFSET 0x078 155 #define VAS_PSWID_EA_HANDLE PPC_BITMASK(0, 31) 156 157 #define VAS_SPARE1_OFFSET 0x080 158 #define VAS_SPARE2_OFFSET 0x088 159 #define VAS_SPARE3_OFFSET 0x090 160 #define VAS_SPARE4_OFFSET 0x130 161 #define VAS_SPARE5_OFFSET 0x160 162 #define VAS_SPARE6_OFFSET 0x188 163 164 #define VAS_LFIFO_BAR_OFFSET 0x0A0 165 #define VAS_LFIFO_BAR PPC_BITMASK(8, 53) 166 #define VAS_PAGE_MIGRATION_SELECT PPC_BITMASK(54, 56) 167 168 #define VAS_LDATA_STAMP_CTL_OFFSET 0x0A8 169 #define VAS_LDATA_STAMP PPC_BITMASK(0, 1) 170 #define VAS_XTRA_WRITE PPC_BIT(2) 171 172 #define VAS_LDMA_CACHE_CTL_OFFSET 0x0B0 173 #define VAS_LDMA_TYPE PPC_BITMASK(0, 1) 174 #define VAS_LDMA_FIFO_DISABLE PPC_BIT(2) 175 176 #define VAS_LRFIFO_PUSH_OFFSET 0x0B8 177 #define VAS_LRFIFO_PUSH PPC_BITMASK(0, 15) 178 179 #define VAS_CURR_MSG_COUNT_OFFSET 0x0C0 180 #define VAS_CURR_MSG_COUNT PPC_BITMASK(0, 7) 181 182 #define VAS_LNOTIFY_AFTER_COUNT_OFFSET 0x0C8 183 #define VAS_LNOTIFY_AFTER_COUNT PPC_BITMASK(0, 7) 184 185 #define VAS_LRX_WCRED_OFFSET 0x0E0 186 #define VAS_LRX_WCRED PPC_BITMASK(0, 15) 187 188 #define VAS_LRX_WCRED_ADDER_OFFSET 0x190 189 #define VAS_LRX_WCRED_ADDER PPC_BITMASK(0, 15) 190 191 #define VAS_TX_WCRED_OFFSET 0x0F0 192 #define VAS_TX_WCRED PPC_BITMASK(4, 15) 193 194 #define VAS_TX_WCRED_ADDER_OFFSET 0x1A0 195 #define VAS_TX_WCRED_ADDER PPC_BITMASK(4, 15) 196 197 #define VAS_LFIFO_SIZE_OFFSET 0x100 198 #define VAS_LFIFO_SIZE PPC_BITMASK(0, 3) 199 200 #define VAS_WINCTL_OFFSET 0x108 201 #define VAS_WINCTL_OPEN PPC_BIT(0) 202 #define VAS_WINCTL_REJ_NO_CREDIT PPC_BIT(1) 203 #define VAS_WINCTL_PIN PPC_BIT(2) 204 #define VAS_WINCTL_TX_WCRED_MODE PPC_BIT(3) 205 #define VAS_WINCTL_RX_WCRED_MODE PPC_BIT(4) 206 #define VAS_WINCTL_TX_WORD_MODE PPC_BIT(5) 207 #define VAS_WINCTL_RX_WORD_MODE PPC_BIT(6) 208 #define VAS_WINCTL_RSVD_TXBUF PPC_BIT(7) 209 #define VAS_WINCTL_THRESH_CTL PPC_BITMASK(8, 9) 210 #define VAS_WINCTL_FAULT_WIN PPC_BIT(10) 211 #define VAS_WINCTL_NX_WIN PPC_BIT(11) 212 213 #define VAS_WIN_STATUS_OFFSET 0x110 214 #define VAS_WIN_BUSY PPC_BIT(1) 215 216 #define VAS_WIN_CTX_CACHING_CTL_OFFSET 0x118 217 #define VAS_CASTOUT_REQ PPC_BIT(0) 218 #define VAS_PUSH_TO_MEM PPC_BIT(1) 219 #define VAS_WIN_CACHE_STATUS PPC_BIT(4) 220 221 #define VAS_TX_RSVD_BUF_COUNT_OFFSET 0x120 222 #define VAS_RXVD_BUF_COUNT PPC_BITMASK(58, 63) 223 224 #define VAS_LRFIFO_WIN_PTR_OFFSET 0x128 225 #define VAS_LRX_WIN_ID PPC_BITMASK(0, 15) 226 227 /* 228 * Local Notification Control Register controls what happens in _response_ 229 * to a paste command and hence applies only to receive windows. 230 */ 231 #define VAS_LNOTIFY_CTL_OFFSET 0x138 232 #define VAS_NOTIFY_DISABLE PPC_BIT(0) 233 #define VAS_INTR_DISABLE PPC_BIT(1) 234 #define VAS_NOTIFY_EARLY PPC_BIT(2) 235 #define VAS_NOTIFY_OSU_INTR PPC_BIT(3) 236 237 #define VAS_LNOTIFY_PID_OFFSET 0x140 238 #define VAS_LNOTIFY_PID PPC_BITMASK(0, 19) 239 240 #define VAS_LNOTIFY_LPID_OFFSET 0x148 241 #define VAS_LNOTIFY_LPID PPC_BITMASK(0, 11) 242 243 #define VAS_LNOTIFY_TID_OFFSET 0x150 244 #define VAS_LNOTIFY_TID PPC_BITMASK(0, 15) 245 246 #define VAS_LNOTIFY_SCOPE_OFFSET 0x158 247 #define VAS_LNOTIFY_MIN_SCOPE PPC_BITMASK(0, 1) 248 #define VAS_LNOTIFY_MAX_SCOPE PPC_BITMASK(2, 3) 249 250 #define VAS_NX_UTIL_OFFSET 0x1B0 251 #define VAS_NX_UTIL PPC_BITMASK(0, 63) 252 253 /* SE: Side effects */ 254 #define VAS_NX_UTIL_SE_OFFSET 0x1B8 255 #define VAS_NX_UTIL_SE PPC_BITMASK(0, 63) 256 257 #define VAS_NX_UTIL_ADDER_OFFSET 0x180 258 #define VAS_NX_UTIL_ADDER PPC_BITMASK(32, 63) 259 260 /* 261 * VREG(x): 262 * Expand a register's short name (eg: LPID) into two parameters: 263 * - the register's short name in string form ("LPID"), and 264 * - the name of the macro (eg: VAS_LPID_OFFSET), defining the 265 * register's offset in the window context 266 */ 267 #define VREG_SFX(n, s) __stringify(n), VAS_##n##s 268 #define VREG(r) VREG_SFX(r, _OFFSET) 269 270 /* 271 * Local Notify Scope Control Register. (Receive windows only). 272 */ 273 enum vas_notify_scope { 274 VAS_SCOPE_LOCAL, 275 VAS_SCOPE_GROUP, 276 VAS_SCOPE_VECTORED_GROUP, 277 VAS_SCOPE_UNUSED, 278 }; 279 280 /* 281 * Local DMA Cache Control Register (Receive windows only). 282 */ 283 enum vas_dma_type { 284 VAS_DMA_TYPE_INJECT, 285 VAS_DMA_TYPE_WRITE, 286 }; 287 288 /* 289 * Local Notify Scope Control Register. (Receive windows only). 290 * Not applicable to NX receive windows. 291 */ 292 enum vas_notify_after_count { 293 VAS_NOTIFY_AFTER_256 = 0, 294 VAS_NOTIFY_NONE, 295 VAS_NOTIFY_AFTER_2 296 }; 297 298 /* 299 * NX can generate an interrupt for multiple faults and expects kernel 300 * to process all of them. So read all valid CRB entries until find the 301 * invalid one. So use pswid which is pasted by NX and ccw[0] (reserved 302 * bit in BE) to check valid CRB. CCW[0] will not be touched by user 303 * space. Application gets CRB formt error if it updates this bit. 304 * 305 * Invalidate FIFO during allocation and process all entries from last 306 * successful read until finds invalid pswid and ccw[0] values. 307 * After reading each CRB entry from fault FIFO, the kernel invalidate 308 * it by updating pswid with FIFO_INVALID_ENTRY and CCW[0] with 309 * CCW0_INVALID. 310 */ 311 #define FIFO_INVALID_ENTRY 0xffffffff 312 #define CCW0_INVALID 1 313 314 /* 315 * One per instance of VAS. Each instance will have a separate set of 316 * receive windows, one per coprocessor type. 317 * 318 * See also function header of set_vinst_win() for details on ->windows[] 319 * and ->rxwin[] tables. 320 */ 321 struct vas_instance { 322 int vas_id; 323 struct ida ida; 324 struct list_head node; 325 struct platform_device *pdev; 326 327 u64 hvwc_bar_start; 328 u64 uwc_bar_start; 329 u64 paste_base_addr; 330 u64 paste_win_id_shift; 331 332 u64 irq_port; 333 int virq; 334 int fault_crbs; 335 int fault_fifo_size; 336 int fifo_in_progress; /* To wake up thread or return IRQ_HANDLED */ 337 spinlock_t fault_lock; /* Protects fifo_in_progress update */ 338 void *fault_fifo; 339 struct vas_window *fault_win; /* Fault window */ 340 341 struct mutex mutex; 342 struct vas_window *rxwin[VAS_COP_TYPE_MAX]; 343 struct vas_window *windows[VAS_WINDOWS_PER_CHIP]; 344 345 char *dbgname; 346 struct dentry *dbgdir; 347 }; 348 349 /* 350 * In-kernel state a VAS window. One per window. 351 */ 352 struct vas_window { 353 /* Fields common to send and receive windows */ 354 struct vas_instance *vinst; 355 int winid; 356 bool tx_win; /* True if send window */ 357 bool nx_win; /* True if NX window */ 358 bool user_win; /* True if user space window */ 359 void *hvwc_map; /* HV window context */ 360 void *uwc_map; /* OS/User window context */ 361 struct pid *pid; /* Linux process id of owner */ 362 struct pid *tgid; /* Thread group ID of owner */ 363 struct mm_struct *mm; /* Linux process mm_struct */ 364 int wcreds_max; /* Window credits */ 365 366 char *dbgname; 367 struct dentry *dbgdir; 368 369 /* Fields applicable only to send windows */ 370 void *paste_kaddr; 371 char *paste_addr_name; 372 struct vas_window *rxwin; 373 374 /* Feilds applicable only to receive windows */ 375 enum vas_cop_type cop; 376 atomic_t num_txwins; 377 }; 378 379 /* 380 * Container for the hardware state of a window. One per-window. 381 * 382 * A VAS Window context is a 512-byte area in the hardware that contains 383 * a set of 64-bit registers. Individual bit-fields in these registers 384 * determine the configuration/operation of the hardware. struct vas_winctx 385 * is a container for the register fields in the window context. 386 */ 387 struct vas_winctx { 388 void *rx_fifo; 389 int rx_fifo_size; 390 int wcreds_max; 391 int rsvd_txbuf_count; 392 393 bool user_win; 394 bool nx_win; 395 bool fault_win; 396 bool rsvd_txbuf_enable; 397 bool pin_win; 398 bool rej_no_credit; 399 bool tx_wcred_mode; 400 bool rx_wcred_mode; 401 bool tx_word_mode; 402 bool rx_word_mode; 403 bool data_stamp; 404 bool xtra_write; 405 bool notify_disable; 406 bool intr_disable; 407 bool fifo_disable; 408 bool notify_early; 409 bool notify_os_intr_reg; 410 411 int lpid; 412 int pidr; /* value from SPRN_PID, not linux pid */ 413 int lnotify_lpid; 414 int lnotify_pid; 415 int lnotify_tid; 416 u32 pswid; 417 int rx_win_id; 418 int fault_win_id; 419 int tc_mode; 420 421 u64 irq_port; 422 423 enum vas_dma_type dma_type; 424 enum vas_notify_scope min_scope; 425 enum vas_notify_scope max_scope; 426 enum vas_notify_after_count notify_after_count; 427 }; 428 429 extern struct mutex vas_mutex; 430 431 extern struct vas_instance *find_vas_instance(int vasid); 432 extern void vas_init_dbgdir(void); 433 extern void vas_instance_init_dbgdir(struct vas_instance *vinst); 434 extern void vas_window_init_dbgdir(struct vas_window *win); 435 extern void vas_window_free_dbgdir(struct vas_window *win); 436 extern int vas_setup_fault_window(struct vas_instance *vinst); 437 extern irqreturn_t vas_fault_thread_fn(int irq, void *data); 438 extern irqreturn_t vas_fault_handler(int irq, void *dev_id); 439 extern struct vas_window *vas_pswid_to_window(struct vas_instance *vinst, 440 uint32_t pswid); 441 442 static inline int vas_window_pid(struct vas_window *window) 443 { 444 return pid_vnr(window->pid); 445 } 446 447 static inline void vas_log_write(struct vas_window *win, char *name, 448 void *regptr, u64 val) 449 { 450 if (val) 451 pr_debug("%swin #%d: %s reg %p, val 0x%016llx\n", 452 win->tx_win ? "Tx" : "Rx", win->winid, name, 453 regptr, val); 454 } 455 456 static inline void write_uwc_reg(struct vas_window *win, char *name, 457 s32 reg, u64 val) 458 { 459 void *regptr; 460 461 regptr = win->uwc_map + reg; 462 vas_log_write(win, name, regptr, val); 463 464 out_be64(regptr, val); 465 } 466 467 static inline void write_hvwc_reg(struct vas_window *win, char *name, 468 s32 reg, u64 val) 469 { 470 void *regptr; 471 472 regptr = win->hvwc_map + reg; 473 vas_log_write(win, name, regptr, val); 474 475 out_be64(regptr, val); 476 } 477 478 static inline u64 read_hvwc_reg(struct vas_window *win, 479 char *name __maybe_unused, s32 reg) 480 { 481 return in_be64(win->hvwc_map+reg); 482 } 483 484 /* 485 * Encode/decode the Partition Send Window ID (PSWID) for a window in 486 * a way that we can uniquely identify any window in the system. i.e. 487 * we should be able to locate the 'struct vas_window' given the PSWID. 488 * 489 * Bits Usage 490 * 0:7 VAS id (8 bits) 491 * 8:15 Unused, 0 (3 bits) 492 * 16:31 Window id (16 bits) 493 */ 494 static inline u32 encode_pswid(int vasid, int winid) 495 { 496 return ((u32)winid | (vasid << (31 - 7))); 497 } 498 499 static inline void decode_pswid(u32 pswid, int *vasid, int *winid) 500 { 501 if (vasid) 502 *vasid = pswid >> (31 - 7) & 0xFF; 503 504 if (winid) 505 *winid = pswid & 0xFFFF; 506 } 507 #endif /* _VAS_H */ 508