196768914SSukadev Bhattiprolu /* 296768914SSukadev Bhattiprolu * Copyright 2016-17 IBM Corp. 396768914SSukadev Bhattiprolu * 496768914SSukadev Bhattiprolu * This program is free software; you can redistribute it and/or 596768914SSukadev Bhattiprolu * modify it under the terms of the GNU General Public License 696768914SSukadev Bhattiprolu * as published by the Free Software Foundation; either version 796768914SSukadev Bhattiprolu * 2 of the License, or (at your option) any later version. 896768914SSukadev Bhattiprolu */ 996768914SSukadev Bhattiprolu 1096768914SSukadev Bhattiprolu #ifndef _VAS_H 1196768914SSukadev Bhattiprolu #define _VAS_H 1296768914SSukadev Bhattiprolu #include <linux/atomic.h> 1396768914SSukadev Bhattiprolu #include <linux/idr.h> 1496768914SSukadev Bhattiprolu #include <asm/vas.h> 15b25b33acSSukadev Bhattiprolu #include <linux/io.h> 1696768914SSukadev Bhattiprolu 1796768914SSukadev Bhattiprolu /* 1896768914SSukadev Bhattiprolu * Overview of Virtual Accelerator Switchboard (VAS). 1996768914SSukadev Bhattiprolu * 2096768914SSukadev Bhattiprolu * VAS is a hardware "switchboard" that allows senders and receivers to 2196768914SSukadev Bhattiprolu * exchange messages with _minimal_ kernel involvment. The receivers are 2296768914SSukadev Bhattiprolu * typically NX coprocessor engines that perform compression or encryption 2396768914SSukadev Bhattiprolu * in hardware, but receivers can also be other software threads. 2496768914SSukadev Bhattiprolu * 2596768914SSukadev Bhattiprolu * Senders are user/kernel threads that submit compression/encryption or 2696768914SSukadev Bhattiprolu * other requests to the receivers. Senders must format their messages as 2796768914SSukadev Bhattiprolu * Coprocessor Request Blocks (CRB)s and submit them using the "copy" and 2896768914SSukadev Bhattiprolu * "paste" instructions which were introduced in Power9. 2996768914SSukadev Bhattiprolu * 3096768914SSukadev Bhattiprolu * A Power node can have (upto?) 8 Power chips. There is one instance of 3196768914SSukadev Bhattiprolu * VAS in each Power9 chip. Each instance of VAS has 64K windows or ports, 3296768914SSukadev Bhattiprolu * Senders and receivers must each connect to a separate window before they 3396768914SSukadev Bhattiprolu * can exchange messages through the switchboard. 3496768914SSukadev Bhattiprolu * 3596768914SSukadev Bhattiprolu * Each window is described by two types of window contexts: 3696768914SSukadev Bhattiprolu * 3796768914SSukadev Bhattiprolu * Hypervisor Window Context (HVWC) of size VAS_HVWC_SIZE bytes 3896768914SSukadev Bhattiprolu * 3996768914SSukadev Bhattiprolu * OS/User Window Context (UWC) of size VAS_UWC_SIZE bytes. 4096768914SSukadev Bhattiprolu * 4196768914SSukadev Bhattiprolu * A window context can be viewed as a set of 64-bit registers. The settings 4296768914SSukadev Bhattiprolu * in these registers configure/control/determine the behavior of the VAS 4396768914SSukadev Bhattiprolu * hardware when messages are sent/received through the window. The registers 4496768914SSukadev Bhattiprolu * in the HVWC are configured by the kernel while the registers in the UWC can 4596768914SSukadev Bhattiprolu * be configured by the kernel or by the user space application that is using 4696768914SSukadev Bhattiprolu * the window. 4796768914SSukadev Bhattiprolu * 4896768914SSukadev Bhattiprolu * The HVWCs for all windows on a specific instance of VAS are in a contiguous 4996768914SSukadev Bhattiprolu * range of hardware addresses or Base address region (BAR) referred to as the 5096768914SSukadev Bhattiprolu * HVWC BAR for the instance. Similarly the UWCs for all windows on an instance 5196768914SSukadev Bhattiprolu * are referred to as the UWC BAR for the instance. 5296768914SSukadev Bhattiprolu * 5396768914SSukadev Bhattiprolu * The two BARs for each instance are defined Power9 MMIO Ranges spreadsheet 5496768914SSukadev Bhattiprolu * and available to the kernel in the VAS node's "reg" property in the device 5596768914SSukadev Bhattiprolu * tree: 5696768914SSukadev Bhattiprolu * 5796768914SSukadev Bhattiprolu * /proc/device-tree/vasm@.../reg 5896768914SSukadev Bhattiprolu * 5996768914SSukadev Bhattiprolu * (see vas_probe() for details on the reg property). 6096768914SSukadev Bhattiprolu * 6196768914SSukadev Bhattiprolu * The kernel maps the HVWC and UWC BAR regions into the kernel address 6296768914SSukadev Bhattiprolu * space (hvwc_map and uwc_map). The kernel can then access the window 6396768914SSukadev Bhattiprolu * contexts of a specific window using: 6496768914SSukadev Bhattiprolu * 6596768914SSukadev Bhattiprolu * hvwc = hvwc_map + winid * VAS_HVWC_SIZE. 6696768914SSukadev Bhattiprolu * uwc = uwc_map + winid * VAS_UWC_SIZE. 6796768914SSukadev Bhattiprolu * 6896768914SSukadev Bhattiprolu * where winid is the window index (0..64K). 6996768914SSukadev Bhattiprolu * 7096768914SSukadev Bhattiprolu * As mentioned, a window context is used to "configure" a window. Besides 7196768914SSukadev Bhattiprolu * this configuration address, each _send_ window also has a unique hardware 7296768914SSukadev Bhattiprolu * "paste" address that is used to submit requests/CRBs (see vas_paste_crb()). 7396768914SSukadev Bhattiprolu * 7496768914SSukadev Bhattiprolu * The hardware paste address for a window is computed using the "paste 7596768914SSukadev Bhattiprolu * base address" and "paste win id shift" reg properties in the VAS device 7696768914SSukadev Bhattiprolu * tree node using: 7796768914SSukadev Bhattiprolu * 7896768914SSukadev Bhattiprolu * paste_addr = paste_base + ((winid << paste_win_id_shift)) 7996768914SSukadev Bhattiprolu * 8096768914SSukadev Bhattiprolu * (again, see vas_probe() for ->paste_base_addr and ->paste_win_id_shift). 8196768914SSukadev Bhattiprolu * 8296768914SSukadev Bhattiprolu * The kernel maps this hardware address into the sender's address space 8396768914SSukadev Bhattiprolu * after which they can use the 'paste' instruction (new in Power9) to 8496768914SSukadev Bhattiprolu * send a message (submit a request aka CRB) to the coprocessor. 8596768914SSukadev Bhattiprolu * 8696768914SSukadev Bhattiprolu * NOTE: In the initial version, senders can only in-kernel drivers/threads. 8796768914SSukadev Bhattiprolu * Support for user space threads will be added in follow-on patches. 8896768914SSukadev Bhattiprolu * 8996768914SSukadev Bhattiprolu * TODO: Do we need to map the UWC into user address space so they can return 9096768914SSukadev Bhattiprolu * credits? Its NA for NX but may be needed for other receive windows. 9196768914SSukadev Bhattiprolu * 9296768914SSukadev Bhattiprolu */ 9396768914SSukadev Bhattiprolu 9496768914SSukadev Bhattiprolu #define VAS_WINDOWS_PER_CHIP (64 << 10) 9596768914SSukadev Bhattiprolu 9696768914SSukadev Bhattiprolu /* 9796768914SSukadev Bhattiprolu * Hypervisor and OS/USer Window Context sizes 9896768914SSukadev Bhattiprolu */ 9996768914SSukadev Bhattiprolu #define VAS_HVWC_SIZE 512 10096768914SSukadev Bhattiprolu #define VAS_UWC_SIZE PAGE_SIZE 10196768914SSukadev Bhattiprolu 10296768914SSukadev Bhattiprolu /* 10396768914SSukadev Bhattiprolu * Initial per-process credits. 10496768914SSukadev Bhattiprolu * Max send window credits: 4K-1 (12-bits in VAS_TX_WCRED) 10596768914SSukadev Bhattiprolu * Max receive window credits: 64K-1 (16 bits in VAS_LRX_WCRED) 10696768914SSukadev Bhattiprolu * 10796768914SSukadev Bhattiprolu * TODO: Needs tuning for per-process credits 10896768914SSukadev Bhattiprolu */ 10996768914SSukadev Bhattiprolu #define VAS_WCREDS_MIN 16 11096768914SSukadev Bhattiprolu #define VAS_WCREDS_MAX ((64 << 10) - 1) 11196768914SSukadev Bhattiprolu #define VAS_WCREDS_DEFAULT (1 << 10) 11296768914SSukadev Bhattiprolu 11396768914SSukadev Bhattiprolu /* 11496768914SSukadev Bhattiprolu * VAS Window Context Register Offsets and bitmasks. 11596768914SSukadev Bhattiprolu * See Section 3.1.4 of VAS Work book 11696768914SSukadev Bhattiprolu */ 11796768914SSukadev Bhattiprolu #define VAS_LPID_OFFSET 0x010 11896768914SSukadev Bhattiprolu #define VAS_LPID PPC_BITMASK(0, 11) 11996768914SSukadev Bhattiprolu 12096768914SSukadev Bhattiprolu #define VAS_PID_OFFSET 0x018 12196768914SSukadev Bhattiprolu #define VAS_PID_ID PPC_BITMASK(0, 19) 12296768914SSukadev Bhattiprolu 12396768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_OFFSET 0x020 12496768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_DR PPC_BIT(0) 12596768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_TA PPC_BIT(1) 12696768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_PR PPC_BIT(2) 12796768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_US PPC_BIT(3) 12896768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_HV PPC_BIT(4) 12996768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_SF PPC_BIT(5) 13096768914SSukadev Bhattiprolu 13196768914SSukadev Bhattiprolu #define VAS_XLATE_LPCR_OFFSET 0x028 13296768914SSukadev Bhattiprolu #define VAS_XLATE_LPCR_PAGE_SIZE PPC_BITMASK(0, 2) 13396768914SSukadev Bhattiprolu #define VAS_XLATE_LPCR_ISL PPC_BIT(3) 13496768914SSukadev Bhattiprolu #define VAS_XLATE_LPCR_TC PPC_BIT(4) 13596768914SSukadev Bhattiprolu #define VAS_XLATE_LPCR_SC PPC_BIT(5) 13696768914SSukadev Bhattiprolu 13796768914SSukadev Bhattiprolu #define VAS_XLATE_CTL_OFFSET 0x030 13896768914SSukadev Bhattiprolu #define VAS_XLATE_MODE PPC_BITMASK(0, 1) 13996768914SSukadev Bhattiprolu 14096768914SSukadev Bhattiprolu #define VAS_AMR_OFFSET 0x040 14196768914SSukadev Bhattiprolu #define VAS_AMR PPC_BITMASK(0, 63) 14296768914SSukadev Bhattiprolu 14396768914SSukadev Bhattiprolu #define VAS_SEIDR_OFFSET 0x048 14496768914SSukadev Bhattiprolu #define VAS_SEIDR PPC_BITMASK(0, 63) 14596768914SSukadev Bhattiprolu 14696768914SSukadev Bhattiprolu #define VAS_FAULT_TX_WIN_OFFSET 0x050 14796768914SSukadev Bhattiprolu #define VAS_FAULT_TX_WIN PPC_BITMASK(48, 63) 14896768914SSukadev Bhattiprolu 14996768914SSukadev Bhattiprolu #define VAS_OSU_INTR_SRC_RA_OFFSET 0x060 15096768914SSukadev Bhattiprolu #define VAS_OSU_INTR_SRC_RA PPC_BITMASK(8, 63) 15196768914SSukadev Bhattiprolu 15296768914SSukadev Bhattiprolu #define VAS_HV_INTR_SRC_RA_OFFSET 0x070 15396768914SSukadev Bhattiprolu #define VAS_HV_INTR_SRC_RA PPC_BITMASK(8, 63) 15496768914SSukadev Bhattiprolu 15596768914SSukadev Bhattiprolu #define VAS_PSWID_OFFSET 0x078 15696768914SSukadev Bhattiprolu #define VAS_PSWID_EA_HANDLE PPC_BITMASK(0, 31) 15796768914SSukadev Bhattiprolu 15896768914SSukadev Bhattiprolu #define VAS_SPARE1_OFFSET 0x080 15996768914SSukadev Bhattiprolu #define VAS_SPARE2_OFFSET 0x088 16096768914SSukadev Bhattiprolu #define VAS_SPARE3_OFFSET 0x090 16196768914SSukadev Bhattiprolu #define VAS_SPARE4_OFFSET 0x130 16296768914SSukadev Bhattiprolu #define VAS_SPARE5_OFFSET 0x160 16396768914SSukadev Bhattiprolu #define VAS_SPARE6_OFFSET 0x188 16496768914SSukadev Bhattiprolu 16596768914SSukadev Bhattiprolu #define VAS_LFIFO_BAR_OFFSET 0x0A0 16696768914SSukadev Bhattiprolu #define VAS_LFIFO_BAR PPC_BITMASK(8, 53) 16796768914SSukadev Bhattiprolu #define VAS_PAGE_MIGRATION_SELECT PPC_BITMASK(54, 56) 16896768914SSukadev Bhattiprolu 16996768914SSukadev Bhattiprolu #define VAS_LDATA_STAMP_CTL_OFFSET 0x0A8 17096768914SSukadev Bhattiprolu #define VAS_LDATA_STAMP PPC_BITMASK(0, 1) 17196768914SSukadev Bhattiprolu #define VAS_XTRA_WRITE PPC_BIT(2) 17296768914SSukadev Bhattiprolu 17396768914SSukadev Bhattiprolu #define VAS_LDMA_CACHE_CTL_OFFSET 0x0B0 17496768914SSukadev Bhattiprolu #define VAS_LDMA_TYPE PPC_BITMASK(0, 1) 17596768914SSukadev Bhattiprolu #define VAS_LDMA_FIFO_DISABLE PPC_BIT(2) 17696768914SSukadev Bhattiprolu 17796768914SSukadev Bhattiprolu #define VAS_LRFIFO_PUSH_OFFSET 0x0B8 17896768914SSukadev Bhattiprolu #define VAS_LRFIFO_PUSH PPC_BITMASK(0, 15) 17996768914SSukadev Bhattiprolu 18096768914SSukadev Bhattiprolu #define VAS_CURR_MSG_COUNT_OFFSET 0x0C0 18196768914SSukadev Bhattiprolu #define VAS_CURR_MSG_COUNT PPC_BITMASK(0, 7) 18296768914SSukadev Bhattiprolu 18396768914SSukadev Bhattiprolu #define VAS_LNOTIFY_AFTER_COUNT_OFFSET 0x0C8 18496768914SSukadev Bhattiprolu #define VAS_LNOTIFY_AFTER_COUNT PPC_BITMASK(0, 7) 18596768914SSukadev Bhattiprolu 18696768914SSukadev Bhattiprolu #define VAS_LRX_WCRED_OFFSET 0x0E0 18796768914SSukadev Bhattiprolu #define VAS_LRX_WCRED PPC_BITMASK(0, 15) 18896768914SSukadev Bhattiprolu 18996768914SSukadev Bhattiprolu #define VAS_LRX_WCRED_ADDER_OFFSET 0x190 19096768914SSukadev Bhattiprolu #define VAS_LRX_WCRED_ADDER PPC_BITMASK(0, 15) 19196768914SSukadev Bhattiprolu 19296768914SSukadev Bhattiprolu #define VAS_TX_WCRED_OFFSET 0x0F0 19396768914SSukadev Bhattiprolu #define VAS_TX_WCRED PPC_BITMASK(4, 15) 19496768914SSukadev Bhattiprolu 19596768914SSukadev Bhattiprolu #define VAS_TX_WCRED_ADDER_OFFSET 0x1A0 19696768914SSukadev Bhattiprolu #define VAS_TX_WCRED_ADDER PPC_BITMASK(4, 15) 19796768914SSukadev Bhattiprolu 19896768914SSukadev Bhattiprolu #define VAS_LFIFO_SIZE_OFFSET 0x100 19996768914SSukadev Bhattiprolu #define VAS_LFIFO_SIZE PPC_BITMASK(0, 3) 20096768914SSukadev Bhattiprolu 20196768914SSukadev Bhattiprolu #define VAS_WINCTL_OFFSET 0x108 20296768914SSukadev Bhattiprolu #define VAS_WINCTL_OPEN PPC_BIT(0) 20396768914SSukadev Bhattiprolu #define VAS_WINCTL_REJ_NO_CREDIT PPC_BIT(1) 20496768914SSukadev Bhattiprolu #define VAS_WINCTL_PIN PPC_BIT(2) 20596768914SSukadev Bhattiprolu #define VAS_WINCTL_TX_WCRED_MODE PPC_BIT(3) 20696768914SSukadev Bhattiprolu #define VAS_WINCTL_RX_WCRED_MODE PPC_BIT(4) 20796768914SSukadev Bhattiprolu #define VAS_WINCTL_TX_WORD_MODE PPC_BIT(5) 20896768914SSukadev Bhattiprolu #define VAS_WINCTL_RX_WORD_MODE PPC_BIT(6) 20996768914SSukadev Bhattiprolu #define VAS_WINCTL_RSVD_TXBUF PPC_BIT(7) 21096768914SSukadev Bhattiprolu #define VAS_WINCTL_THRESH_CTL PPC_BITMASK(8, 9) 21196768914SSukadev Bhattiprolu #define VAS_WINCTL_FAULT_WIN PPC_BIT(10) 21296768914SSukadev Bhattiprolu #define VAS_WINCTL_NX_WIN PPC_BIT(11) 21396768914SSukadev Bhattiprolu 21496768914SSukadev Bhattiprolu #define VAS_WIN_STATUS_OFFSET 0x110 21596768914SSukadev Bhattiprolu #define VAS_WIN_BUSY PPC_BIT(1) 21696768914SSukadev Bhattiprolu 21796768914SSukadev Bhattiprolu #define VAS_WIN_CTX_CACHING_CTL_OFFSET 0x118 21896768914SSukadev Bhattiprolu #define VAS_CASTOUT_REQ PPC_BIT(0) 21996768914SSukadev Bhattiprolu #define VAS_PUSH_TO_MEM PPC_BIT(1) 22096768914SSukadev Bhattiprolu #define VAS_WIN_CACHE_STATUS PPC_BIT(4) 22196768914SSukadev Bhattiprolu 22296768914SSukadev Bhattiprolu #define VAS_TX_RSVD_BUF_COUNT_OFFSET 0x120 22396768914SSukadev Bhattiprolu #define VAS_RXVD_BUF_COUNT PPC_BITMASK(58, 63) 22496768914SSukadev Bhattiprolu 22596768914SSukadev Bhattiprolu #define VAS_LRFIFO_WIN_PTR_OFFSET 0x128 22696768914SSukadev Bhattiprolu #define VAS_LRX_WIN_ID PPC_BITMASK(0, 15) 22796768914SSukadev Bhattiprolu 22896768914SSukadev Bhattiprolu /* 22996768914SSukadev Bhattiprolu * Local Notification Control Register controls what happens in _response_ 23096768914SSukadev Bhattiprolu * to a paste command and hence applies only to receive windows. 23196768914SSukadev Bhattiprolu */ 23296768914SSukadev Bhattiprolu #define VAS_LNOTIFY_CTL_OFFSET 0x138 23396768914SSukadev Bhattiprolu #define VAS_NOTIFY_DISABLE PPC_BIT(0) 23496768914SSukadev Bhattiprolu #define VAS_INTR_DISABLE PPC_BIT(1) 23596768914SSukadev Bhattiprolu #define VAS_NOTIFY_EARLY PPC_BIT(2) 23696768914SSukadev Bhattiprolu #define VAS_NOTIFY_OSU_INTR PPC_BIT(3) 23796768914SSukadev Bhattiprolu 23896768914SSukadev Bhattiprolu #define VAS_LNOTIFY_PID_OFFSET 0x140 23996768914SSukadev Bhattiprolu #define VAS_LNOTIFY_PID PPC_BITMASK(0, 19) 24096768914SSukadev Bhattiprolu 24196768914SSukadev Bhattiprolu #define VAS_LNOTIFY_LPID_OFFSET 0x148 24296768914SSukadev Bhattiprolu #define VAS_LNOTIFY_LPID PPC_BITMASK(0, 11) 24396768914SSukadev Bhattiprolu 24496768914SSukadev Bhattiprolu #define VAS_LNOTIFY_TID_OFFSET 0x150 24596768914SSukadev Bhattiprolu #define VAS_LNOTIFY_TID PPC_BITMASK(0, 15) 24696768914SSukadev Bhattiprolu 24796768914SSukadev Bhattiprolu #define VAS_LNOTIFY_SCOPE_OFFSET 0x158 24896768914SSukadev Bhattiprolu #define VAS_LNOTIFY_MIN_SCOPE PPC_BITMASK(0, 1) 24996768914SSukadev Bhattiprolu #define VAS_LNOTIFY_MAX_SCOPE PPC_BITMASK(2, 3) 25096768914SSukadev Bhattiprolu 25196768914SSukadev Bhattiprolu #define VAS_NX_UTIL_OFFSET 0x1B0 25296768914SSukadev Bhattiprolu #define VAS_NX_UTIL PPC_BITMASK(0, 63) 25396768914SSukadev Bhattiprolu 25496768914SSukadev Bhattiprolu /* SE: Side effects */ 25596768914SSukadev Bhattiprolu #define VAS_NX_UTIL_SE_OFFSET 0x1B8 25696768914SSukadev Bhattiprolu #define VAS_NX_UTIL_SE PPC_BITMASK(0, 63) 25796768914SSukadev Bhattiprolu 25896768914SSukadev Bhattiprolu #define VAS_NX_UTIL_ADDER_OFFSET 0x180 25996768914SSukadev Bhattiprolu #define VAS_NX_UTIL_ADDER PPC_BITMASK(32, 63) 26096768914SSukadev Bhattiprolu 26196768914SSukadev Bhattiprolu /* 26296768914SSukadev Bhattiprolu * Local Notify Scope Control Register. (Receive windows only). 26396768914SSukadev Bhattiprolu */ 26496768914SSukadev Bhattiprolu enum vas_notify_scope { 26596768914SSukadev Bhattiprolu VAS_SCOPE_LOCAL, 26696768914SSukadev Bhattiprolu VAS_SCOPE_GROUP, 26796768914SSukadev Bhattiprolu VAS_SCOPE_VECTORED_GROUP, 26896768914SSukadev Bhattiprolu VAS_SCOPE_UNUSED, 26996768914SSukadev Bhattiprolu }; 27096768914SSukadev Bhattiprolu 27196768914SSukadev Bhattiprolu /* 27296768914SSukadev Bhattiprolu * Local DMA Cache Control Register (Receive windows only). 27396768914SSukadev Bhattiprolu */ 27496768914SSukadev Bhattiprolu enum vas_dma_type { 27596768914SSukadev Bhattiprolu VAS_DMA_TYPE_INJECT, 27696768914SSukadev Bhattiprolu VAS_DMA_TYPE_WRITE, 27796768914SSukadev Bhattiprolu }; 27896768914SSukadev Bhattiprolu 27996768914SSukadev Bhattiprolu /* 28096768914SSukadev Bhattiprolu * Local Notify Scope Control Register. (Receive windows only). 28196768914SSukadev Bhattiprolu * Not applicable to NX receive windows. 28296768914SSukadev Bhattiprolu */ 28396768914SSukadev Bhattiprolu enum vas_notify_after_count { 28496768914SSukadev Bhattiprolu VAS_NOTIFY_AFTER_256 = 0, 28596768914SSukadev Bhattiprolu VAS_NOTIFY_NONE, 28696768914SSukadev Bhattiprolu VAS_NOTIFY_AFTER_2 28796768914SSukadev Bhattiprolu }; 28896768914SSukadev Bhattiprolu 28996768914SSukadev Bhattiprolu /* 29096768914SSukadev Bhattiprolu * One per instance of VAS. Each instance will have a separate set of 29196768914SSukadev Bhattiprolu * receive windows, one per coprocessor type. 29262c4eda4SSukadev Bhattiprolu * 29362c4eda4SSukadev Bhattiprolu * See also function header of set_vinst_win() for details on ->windows[] 29462c4eda4SSukadev Bhattiprolu * and ->rxwin[] tables. 29596768914SSukadev Bhattiprolu */ 29696768914SSukadev Bhattiprolu struct vas_instance { 29796768914SSukadev Bhattiprolu int vas_id; 29896768914SSukadev Bhattiprolu struct ida ida; 29996768914SSukadev Bhattiprolu struct list_head node; 30096768914SSukadev Bhattiprolu struct platform_device *pdev; 30196768914SSukadev Bhattiprolu 30296768914SSukadev Bhattiprolu u64 hvwc_bar_start; 30396768914SSukadev Bhattiprolu u64 uwc_bar_start; 30496768914SSukadev Bhattiprolu u64 paste_base_addr; 30596768914SSukadev Bhattiprolu u64 paste_win_id_shift; 30696768914SSukadev Bhattiprolu 30796768914SSukadev Bhattiprolu struct mutex mutex; 30896768914SSukadev Bhattiprolu struct vas_window *rxwin[VAS_COP_TYPE_MAX]; 30996768914SSukadev Bhattiprolu struct vas_window *windows[VAS_WINDOWS_PER_CHIP]; 31096768914SSukadev Bhattiprolu }; 31196768914SSukadev Bhattiprolu 31296768914SSukadev Bhattiprolu /* 31396768914SSukadev Bhattiprolu * In-kernel state a VAS window. One per window. 31496768914SSukadev Bhattiprolu */ 31596768914SSukadev Bhattiprolu struct vas_window { 31696768914SSukadev Bhattiprolu /* Fields common to send and receive windows */ 31796768914SSukadev Bhattiprolu struct vas_instance *vinst; 31896768914SSukadev Bhattiprolu int winid; 31996768914SSukadev Bhattiprolu bool tx_win; /* True if send window */ 32096768914SSukadev Bhattiprolu bool nx_win; /* True if NX window */ 32196768914SSukadev Bhattiprolu bool user_win; /* True if user space window */ 32296768914SSukadev Bhattiprolu void *hvwc_map; /* HV window context */ 32396768914SSukadev Bhattiprolu void *uwc_map; /* OS/User window context */ 32496768914SSukadev Bhattiprolu pid_t pid; /* Linux process id of owner */ 32596768914SSukadev Bhattiprolu 32696768914SSukadev Bhattiprolu /* Fields applicable only to send windows */ 32796768914SSukadev Bhattiprolu void *paste_kaddr; 32896768914SSukadev Bhattiprolu char *paste_addr_name; 32996768914SSukadev Bhattiprolu struct vas_window *rxwin; 33096768914SSukadev Bhattiprolu 33196768914SSukadev Bhattiprolu /* Feilds applicable only to receive windows */ 33296768914SSukadev Bhattiprolu enum vas_cop_type cop; 33396768914SSukadev Bhattiprolu atomic_t num_txwins; 33496768914SSukadev Bhattiprolu }; 33596768914SSukadev Bhattiprolu 33696768914SSukadev Bhattiprolu /* 33796768914SSukadev Bhattiprolu * Container for the hardware state of a window. One per-window. 33896768914SSukadev Bhattiprolu * 33996768914SSukadev Bhattiprolu * A VAS Window context is a 512-byte area in the hardware that contains 34096768914SSukadev Bhattiprolu * a set of 64-bit registers. Individual bit-fields in these registers 34196768914SSukadev Bhattiprolu * determine the configuration/operation of the hardware. struct vas_winctx 34296768914SSukadev Bhattiprolu * is a container for the register fields in the window context. 34396768914SSukadev Bhattiprolu */ 34496768914SSukadev Bhattiprolu struct vas_winctx { 34596768914SSukadev Bhattiprolu void *rx_fifo; 34696768914SSukadev Bhattiprolu int rx_fifo_size; 34796768914SSukadev Bhattiprolu int wcreds_max; 34896768914SSukadev Bhattiprolu int rsvd_txbuf_count; 34996768914SSukadev Bhattiprolu 35096768914SSukadev Bhattiprolu bool user_win; 35196768914SSukadev Bhattiprolu bool nx_win; 35296768914SSukadev Bhattiprolu bool fault_win; 35396768914SSukadev Bhattiprolu bool rsvd_txbuf_enable; 35496768914SSukadev Bhattiprolu bool pin_win; 35596768914SSukadev Bhattiprolu bool rej_no_credit; 35696768914SSukadev Bhattiprolu bool tx_wcred_mode; 35796768914SSukadev Bhattiprolu bool rx_wcred_mode; 35896768914SSukadev Bhattiprolu bool tx_word_mode; 35996768914SSukadev Bhattiprolu bool rx_word_mode; 36096768914SSukadev Bhattiprolu bool data_stamp; 36196768914SSukadev Bhattiprolu bool xtra_write; 36296768914SSukadev Bhattiprolu bool notify_disable; 36396768914SSukadev Bhattiprolu bool intr_disable; 36496768914SSukadev Bhattiprolu bool fifo_disable; 36596768914SSukadev Bhattiprolu bool notify_early; 36696768914SSukadev Bhattiprolu bool notify_os_intr_reg; 36796768914SSukadev Bhattiprolu 36896768914SSukadev Bhattiprolu int lpid; 36996768914SSukadev Bhattiprolu int pidr; /* value from SPRN_PID, not linux pid */ 37096768914SSukadev Bhattiprolu int lnotify_lpid; 37196768914SSukadev Bhattiprolu int lnotify_pid; 37296768914SSukadev Bhattiprolu int lnotify_tid; 37396768914SSukadev Bhattiprolu u32 pswid; 37496768914SSukadev Bhattiprolu int rx_win_id; 37596768914SSukadev Bhattiprolu int fault_win_id; 37696768914SSukadev Bhattiprolu int tc_mode; 37796768914SSukadev Bhattiprolu 37896768914SSukadev Bhattiprolu u64 irq_port; 37996768914SSukadev Bhattiprolu 38096768914SSukadev Bhattiprolu enum vas_dma_type dma_type; 38196768914SSukadev Bhattiprolu enum vas_notify_scope min_scope; 38296768914SSukadev Bhattiprolu enum vas_notify_scope max_scope; 38396768914SSukadev Bhattiprolu enum vas_notify_after_count notify_after_count; 38496768914SSukadev Bhattiprolu }; 38596768914SSukadev Bhattiprolu 3864dea2d1aSSukadev Bhattiprolu extern struct vas_instance *find_vas_instance(int vasid); 3874dea2d1aSSukadev Bhattiprolu 388b25b33acSSukadev Bhattiprolu /* 389b25b33acSSukadev Bhattiprolu * VREG(x): 390b25b33acSSukadev Bhattiprolu * Expand a register's short name (eg: LPID) into two parameters: 391b25b33acSSukadev Bhattiprolu * - the register's short name in string form ("LPID"), and 392b25b33acSSukadev Bhattiprolu * - the name of the macro (eg: VAS_LPID_OFFSET), defining the 393b25b33acSSukadev Bhattiprolu * register's offset in the window context 394b25b33acSSukadev Bhattiprolu */ 395b25b33acSSukadev Bhattiprolu #define VREG_SFX(n, s) __stringify(n), VAS_##n##s 396b25b33acSSukadev Bhattiprolu #define VREG(r) VREG_SFX(r, _OFFSET) 397b25b33acSSukadev Bhattiprolu 398b25b33acSSukadev Bhattiprolu #ifdef vas_debug 39962c4eda4SSukadev Bhattiprolu static inline void dump_rx_win_attr(struct vas_rx_win_attr *attr) 40062c4eda4SSukadev Bhattiprolu { 40162c4eda4SSukadev Bhattiprolu pr_err("VAS: fault %d, notify %d, intr %d early %d\n", 40262c4eda4SSukadev Bhattiprolu attr->fault_win, attr->notify_disable, 40362c4eda4SSukadev Bhattiprolu attr->intr_disable, attr->notify_early); 40462c4eda4SSukadev Bhattiprolu 40562c4eda4SSukadev Bhattiprolu pr_err("VAS: rx_fifo_size %d, max value %d\n", 40662c4eda4SSukadev Bhattiprolu attr->rx_fifo_size, VAS_RX_FIFO_SIZE_MAX); 40762c4eda4SSukadev Bhattiprolu } 40862c4eda4SSukadev Bhattiprolu 409b25b33acSSukadev Bhattiprolu static inline void vas_log_write(struct vas_window *win, char *name, 410b25b33acSSukadev Bhattiprolu void *regptr, u64 val) 411b25b33acSSukadev Bhattiprolu { 412b25b33acSSukadev Bhattiprolu if (val) 413b25b33acSSukadev Bhattiprolu pr_err("%swin #%d: %s reg %p, val 0x%016llx\n", 414b25b33acSSukadev Bhattiprolu win->tx_win ? "Tx" : "Rx", win->winid, name, 415b25b33acSSukadev Bhattiprolu regptr, val); 416b25b33acSSukadev Bhattiprolu } 417b25b33acSSukadev Bhattiprolu 418b25b33acSSukadev Bhattiprolu #else /* vas_debug */ 419b25b33acSSukadev Bhattiprolu 420b25b33acSSukadev Bhattiprolu #define vas_log_write(win, name, reg, val) 42162c4eda4SSukadev Bhattiprolu #define dump_rx_win_attr(attr) 422b25b33acSSukadev Bhattiprolu 423b25b33acSSukadev Bhattiprolu #endif /* vas_debug */ 424b25b33acSSukadev Bhattiprolu 425b25b33acSSukadev Bhattiprolu static inline void write_uwc_reg(struct vas_window *win, char *name, 426b25b33acSSukadev Bhattiprolu s32 reg, u64 val) 427b25b33acSSukadev Bhattiprolu { 428b25b33acSSukadev Bhattiprolu void *regptr; 429b25b33acSSukadev Bhattiprolu 430b25b33acSSukadev Bhattiprolu regptr = win->uwc_map + reg; 431b25b33acSSukadev Bhattiprolu vas_log_write(win, name, regptr, val); 432b25b33acSSukadev Bhattiprolu 433b25b33acSSukadev Bhattiprolu out_be64(regptr, val); 434b25b33acSSukadev Bhattiprolu } 435b25b33acSSukadev Bhattiprolu 436b25b33acSSukadev Bhattiprolu static inline void write_hvwc_reg(struct vas_window *win, char *name, 437b25b33acSSukadev Bhattiprolu s32 reg, u64 val) 438b25b33acSSukadev Bhattiprolu { 439b25b33acSSukadev Bhattiprolu void *regptr; 440b25b33acSSukadev Bhattiprolu 441b25b33acSSukadev Bhattiprolu regptr = win->hvwc_map + reg; 442b25b33acSSukadev Bhattiprolu vas_log_write(win, name, regptr, val); 443b25b33acSSukadev Bhattiprolu 444b25b33acSSukadev Bhattiprolu out_be64(regptr, val); 445b25b33acSSukadev Bhattiprolu } 446b25b33acSSukadev Bhattiprolu 447b25b33acSSukadev Bhattiprolu static inline u64 read_hvwc_reg(struct vas_window *win, 448b25b33acSSukadev Bhattiprolu char *name __maybe_unused, s32 reg) 449b25b33acSSukadev Bhattiprolu { 450b25b33acSSukadev Bhattiprolu return in_be64(win->hvwc_map+reg); 451b25b33acSSukadev Bhattiprolu } 452b25b33acSSukadev Bhattiprolu 45396768914SSukadev Bhattiprolu #endif /* _VAS_H */ 454